CN106933319A - A kind of current transformer DSP electrification reset control methods - Google Patents

Abstract

A kind of current transformer DSP electrification reset control methods, dual processor monitoring chip U1 is connected with CPLD chips U2, CPLD chips U2 is connected with dsp chip U3, after electricity on current transformer, when 1.9V supply voltages are not up to 1.68V, dual processor monitoring chip U1 produces low level, and the state assignment of dual processor monitoring chip U1 is caused that DSP core U3 pieces are in reset state by CPLD chips U2 collections by logical algorithm to dsp chip U3；When 1.9V supply voltages reach 1.68V, dual processor monitoring chip U1 postpones 200ms, it is high level to overturn, it is 21us that the low-speed clock signal CLK that CPLD chips U2 is provided according to the rising edge and dsp chip U3 of collection produces 1 high level to carry out step-by-step counting algorithm, low level is the reset pulse of 34us, reset pulse is exported to dsp chip U3 to be resetted 1 time to dsp chip U3 by CPLD chips U2, and the level state of double treatment monitoring chip U1 is assigned to dsp chip U3 by the CPLD chips U2 after completing that resets.

Description

A kind of current transformer DSP electrification reset control methods

Technical field

The present invention relates to a kind of DSP electrification reset control methods for being applied to wind-force generating converter.

Background technology

Dsp chip, also referred to as digital signal processor, are a kind of micro- places for being particularly suitable for carrying out Digital Signal Processing computing Reason device, it is mainly using being to realize various digital signal processing algorithms real-time, and the current transformer in current wind-power electricity generation is exhausted Most of dsp chip for being all use is used as processor.

CPLD (Complex Programmable Logic Device) CPLD, mainly by can Programmable interconnection matrix unit of the programmed logic macroelement (MC, Macro Cell) around center is constituted, predictable with time delay, Speed is fast and editable characteristic, in current wind-force generating converter the overwhelming majority all using CPLD as coprocessor.

Used as a kind of regenerative resource of cleaning, shared ratio is improved wind energy year by year in the power system of China, is become Stream device is widely used, because wind power generating set is typically all pacified as the core component of wind power generation electric control system Mounted in remoteness, the abundant area of wind-resources, and unit is also very remote with the distance between unit, therefore when unit due to When going up electricity again after some reason power down, the dsp chip for having part current transformer can cause journey after upper electricity because reset is insufficient Sequence is not run.The method of the DSP electrification resets of existing solution be it is upper electricity after carry out artificial hand-reset, this method labor intensive Cost is more, is not suitable for the running environment of wind-power electricity generation；Still an alternative is that the special observation circuit of design, when monitoring After DSP power-up routines do not run, resetted to dsp chip again by reset circuit, run it, this method is relatively costly, Complex structure, and need manually to stop using the partial circuit during more new procedures, it is extremely complex.

The content of the invention

It is an object of the invention to the journey that the DSP power up for overcoming existing current transformer is caused due to insufficient reason that resets The shortcoming that sequence is not run, proposes a kind of current transformer DSP electrification reset control methods.

The technical solution adopted for the present invention to solve the technical problems is：

Current transformer DSP electrification resets control method of the present invention is based on following circuit realiration.The circuit is supervised comprising dual processor Control chip U1, CPLD chip U2 and dsp chip U3.The effect of dual processor monitoring chip U1 is monitoring 1.9V power source changes, is produced The effect of raw reset signal RST, CPLD chip U2 is to receive reset signal and clock signal, carries out algorithm computing, dsp chip The effect of U3 is to produce clock signal and receive reset signal to produce homing action.Treatment dual processor monitoring chip U1 with CPLD chips U2 is connected, and CPLD chips U2 and dsp chip U3 is connected.

Current transformer DSP electrification reset control methods of the present invention comprise the following steps：

1st, when current transformer is started power up, the 1.9V power supplys of power supply start to rise from 0V.When dual processor monitoring chip U1 inspections Measure 1.9V supply voltage value reach 1.68V before, dual processor monitoring chip U1 sends low level signal and gives CPLD chip U2, CPLD chips U2 sends low level signal and gives dsp chip U3 by logical algorithm, keeps dsp chip U3 to be in reset state；When Dual processor monitoring chip U1 detect 1.9V supply voltage reach 1.68V after, dual processor monitoring chip U1 postpones 200ms, it is high level that the signal for sending overturns from low level；

2nd, one 7 bit register QS of CPLD chips U2 internal distributions and 2 bit register HS, a CPLD chip U2 are detected After the signal that dual processor monitoring chip U1 sends is high level from low level upset, start to gather what dsp chip U3 sent CLK signal, while 7 bit register QS and 2 bit register HS are reset, since first CLK signal rising edge is received, 2 Bit register HS set " 01 ", is now 1 by the reset signal set of dsp chip U3；

3rd, when meeting CPLD chips U2 and receiving second rising edge of CLK signal, 7 bit register QS set " 0000010 ", The like, it is 0 by the reset signal set of dsp chip U3 when 7 bit register QS numerical value are " 1000000 "；

4th, it is 1 by the reset signal set of dsp chip, while by 2 when 7 bit register QS numerical value are " 1111111 " Register HS set be " 01 ", CPLD chip U2 algorithms detect 2 bit register HS not be 1 when, reset algorithm is jumped out, by double places The value of the reset signal of reason device monitoring chip U1 is directly assigned to the reset signal of dsp chip (U3).

The current transformer DSP powering methods that the present invention is used have following beneficial effect compared with the prior art：

1st, simple structure, required signal only reset signal and clock signal, it is necessary to circuit be all existing circuit.

2nd, fast response time, can carry out second reset in us ranks for dsp chip, be prevented effectively from program operation, Wrong report failure.

3rd, low cost, algorithm is placed in CPLD, it is not necessary to additional processor, without increasing extra circuit.

Brief description of the drawings

Fig. 1 electrical schematic diagrams of the invention；

Fig. 2 logical flow charts of the invention；

Specific embodiment

The present invention is further described with reference to the accompanying drawings and detailed description.

As shown in figure 1, the present invention is based on following circuit realiration, the circuit includes：Dual processor monitoring chip U1, CPLD core 2 pins of piece U2 and dsp chip U3, dual processor monitoring chip U1 are monitoring 1.9V voltage functions, and 5 pins are RST reset letters Number produce pin；137 pins of CPLD chips U2 are that RST reset signals receive pin, and 142 pins send for XRST reset signals Pin, 31 pins are that clock signal clk receives pin；80 pins of dsp chip U3 are that XRST reset signals receive pin, 138 Pin is that clock signal clk sends pin.2 pins of dual processor monitoring chip U1 are linked with 1.9V voltages, 5 pin CPLD 137 pins of chip U2 are connected, and 142 pins of CPLD chips U2 are connected with 80 pins of dsp chip U3, dsp chip U3 138 pins be connected with 31 pins of CPLD chips U2.

As shown in Fig. 2 current transformer DSP electrification reset control methods of the present invention comprise the following steps：

1st, when current transformer is started power up, the 1.9V power supplys of power supply start to rise from 0V.When the 2 of dual processor monitoring chip U1 Pin detect 1.9V supply voltage value reach 1.68V before, 5 pins of dual processor monitoring chip U1 send low level signal To 137 pins of CPLD chips U2, CPLD chips U2 sends low level signal and gives DSP cores by 142 pins by logical algorithm 80 pins of piece U3, keep dsp chip U3 to be in reset state；When 2 pins of dual processor monitoring chip U1 detect 1.9V Supply voltage reach 1.68V after, dual processor monitoring chip U1 postpones signal that 200ms sent from 5 pins from low level It is high level to overturn；

2nd, one 7 bit register QS of CPLD chips U2 internal distributions and one the 137 of 2 bit register HS, CPLD chip U2 The RST signal that 5 pins that pin detects dual processor monitoring chip U1 send is overturn after high level, to start by low level The CLK signal that 138 pins for gathering dsp chip U3 by 31 pins of CPLD chips U2 send, at the same by 7 bit register QS and 2 bit register HS reset, since first CLK signal rising edge is received, 2 bit register HS set " 01 ", now by DSP The 80 pin reset signal XRST set of chip U3 are 1；

3rd, when 31 pins for meeting CPLD chips U2 receive second rising edge of CLK signal, QS register set " 0000010 ", the like, when QS register values are " 1000000 ", by the 80 pin reset signals of dsp chip U3 XRST set is 0；

4th, it is 1 by the 80 pin reset signal XRST set of dsp chip U3 when QS register values are " 1111111 ", Simultaneously by 2 bit register HS set be " 01 ", CPLD chip U2 algorithms detect 2 bit register HS not be 1 when, jump out reset calculate Method, 80 pins that the value of the 5 pin reset signal RST of dual processor monitoring chip U1 is directly assigned to dsp chip U3 is resetted and is believed Number XRST.

Claims (1)

1. a kind of current transformer DSP electrification reset control methods, based on following circuit realiration, the circuit includes that dual processor monitors core Piece U1, CPLD chip U2 and dsp chip U3, CPLD chip U2 are connected with double treatment monitoring chip U1 and dsp chip U3 respectively, its It is characterised by：The current transformer DSP electrification reset control methods comprise the following steps：

Step 1, started power up when current transformer is in, the 1.9V power supplys of power supply start to rise from 0V；Dual processor monitoring chip U1 Before the supply voltage value for detecting 1.9V reaches 1.68V, send low level signal and pass through to CPLD chips U2, CPLD chip U2 Logical algorithm sends low level signal and gives dsp chip U3, keeps dsp chip U3 to be in reset state；When dual processor monitors electricity Road U1 detect 1.9V supply voltage reach 1.68V after, dual processor monitoring chip U1 postpones 200ms, the signal for sending It is high level from low level upset.

Step 2, one 7 bit register QS of CPLD chip U2 internal distributions and 2 bit register HS, a CPLD chip U2 are detected The signal that dual processor monitoring chip U1 sends is from low level upset for after high level, internal algorithm starts to gather dsp chip The clock signal that U3 sends, while 7 bit register QS and 2 bit register HS are reset, from receiving in first clock signal Rise along 2 bit register HS set " 01 " are started, be now 1 by the reset signal set of dsp chip U3；

Step 3, when received second rising edge of clock signal when, 7 bit register QS set " 0000010 ", the like, when It is 0 by the reset signal set of dsp chip U3 when 9 bit register QS numerical value are " 1000000 "；

Step 4, when 7 bit register QS numerical value are " 1111111 ", be 1 by the reset signal set of dsp chip U3, while by 2 Bit register HS set is " 01 "；Algorithm detect 2 bit register HS not be 1 when, jump out reset algorithm, dual processor is monitored The value of the reset signal of chip U1 is directly assigned to the reset signal of dsp chip U3.