CN1510565A - Reset circuit and control method for embedded system - Google Patents
Reset circuit and control method for embedded system Download PDFInfo
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- CN1510565A CN1510565A CNA031233333A CN03123333A CN1510565A CN 1510565 A CN1510565 A CN 1510565A CN A031233333 A CNA031233333 A CN A031233333A CN 03123333 A CN03123333 A CN 03123333A CN 1510565 A CN1510565 A CN 1510565A
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Abstract
The method is as the follows: 1) on power and reset, low level reset signal outputted by watchdog to CPU; 2) interlinking for watchdog output and CPU input to be disconnected after reset level being lifted up; 3) programmable component to caunt reset times of watchdog and at the same time to detect variation of watchdog level; a) CPU being started up within time N to output dog feeding signal, watchdog output and CPU input to be connected to have system operated normally; b) other wise, system being reset after time T and 4) watchdog output being connected to CPU in normal operation at once soft reset of CPU and reset output being generated by watchdog after time T.
Description
Technical field
The invention belongs to electronic component and circuit class, relate in particular to the resetting means of embedded Control and disposal system.
Background technology
At present, embedded Control and disposal system more and more are widely used in various fields such as communication, testing apparatus, Medical Instruments and information household appliances.Along with improving constantly of user's request, the function of embedded system is also more and more abundanter, thereby it is more and more to take storage unit in the software version of system, lengthening start-up time of system.Since usually a large amount of system software releases will be behind system initialization by network from downloaded, the version amount is big, the download version time is oversize with respect to the dog time of feeding of watchdog circuit, therefore needs CPU constantly to feed dog in downloading process.Very complicated on software processes like this, prolonged version download time simultaneously, reduced system start-up speed.At present, the feeding-dog signal time interval of watchdog chip is fixed, and chip is fed the largest interval of dog time and just determined in case selected, and the feeding-dog signal major part is that an I/O pin by CPU provides, thereby the problems referred to above occurred.Select for use and feed relatively large watchdog chip of dog time and can avoid the dog process of feeding when system start-up, but this moment, the real-time of system was bad, can not in time reset when system goes wrong, thus influence various devices such as communication, testing apparatus, Medical Instruments, information household appliances, the device in embedded Control and disposal system cisco unity malfunction.
Summary of the invention
The purpose of this invention is to provide a kind of reset circuit and control method of embedded system, solve an above-mentioned difficult problem, to satisfy the resetting of embedded system, to feed many-sided needs such as dog, real-time.
The object of the present invention is achieved like this: a kind of reset circuit of embedded system, comprise microprocessor and house dog, the input that resets of microprocessor is connected with the output that resets of house dog, and the present invention is connected the middle programming device that is provided with in the input that resets of microprocessor with the output that resets of house dog.
In a kind of program circuit of control method of reset circuit of embedded system, comprise the following steps:
1, system power-on reset,
2, watchdog chip output low level reset signal is exported to microprocessor through programming device;
3, after reset level raise, programming device disconnected watchdog chip output and getting in touch that microprocessor resets and imports;
4, programming device is counted the number of resets of watchdog chip, detects the variation of feeding the dog level simultaneously;
A. microprocessor system starts in time N*T, after output feeding-dog signal, programming device detect the variation of feeding the dog level for twice, connects watchdog chip output and the microprocessor input that resets that resets, and system normally moves;
B. microprocessor system starts failure in time N*T, and microprocessor is not exported feeding-dog signal, and programming device connects watchdog chip output and the microprocessor input that resets that resets, T system reset after the time, repetition said process;
5, after the normal operation of system, microprocessor is if produce a warm reset, and link to each other watchdog chip output and the microprocessor input that resets that resets this moment, the house dog generation output that resets behind the elapsed time T.
Because the present invention has adopted above technical scheme, thereby has following advantage:
1, the present invention utilizes the programming device in existing most of system, and only takies its less pin and macroelement, does not need to add in addition device, and corresponding programming file just can be provided.
2, the present invention has designed when both having preferably and has carried out, and can not need to provide feeding-dog signal at system starting process again, is applicable to the reset circuit of various embedded systems.Hello dog problem and real-time problem when having solved system reset fully.
3, embedded system reset circuit of the present invention has reduced the complexity that starts software, has improved starting efficiency, can be widely used in multiple embedded system.
Description of drawings
Fig. 1 is the principle schematic of existing embedded system circuit;
Fig. 2 is the principle schematic of the reset circuit of a kind of embedded system of the present invention;
Fig. 3 is the control flow chart of reset circuit of a kind of embedded system of Fig. 2;
Fig. 4 is the reset circuit of a kind of embedded system of Fig. 2, and at the appointed time interior microprocessor can move, and the operation back is by the emulation sequential chart of hand-reset
Fig. 5 is the reset circuit of a kind of embedded system of Fig. 2, at the appointed time in microprocessor can move, system is the emulation sequential chart during program fleet at work;
Fig. 6 is the reset circuit of a kind of embedded system of Fig. 2, the emulation sequential chart when pressing hand-reset in system starting process;
Fig. 7 is the reset circuit of a kind of embedded system of Fig. 2, the analogous diagram that at the appointed time interior microprocessor can not move.
Among the figure:
1, house dog 2, microprocessor (CPU) 3, programming device (CPLD, EPLD)
Embodiment
Below in conjunction with accompanying drawing enforcement of the present invention is done as detailed below:
In Fig. 1, in the existing flush type circuit system commonly used, the input that resets of microprocessor is connected with the output that resets of house dog.Under the situation of the normal operation of system, microprocessor (CPU) 2 is connected with the I/O pin of house dog 1 chip and will produces once flat the variation at regular intervals, and house dog 1 affirmation CPU2 is moved normally; Otherwise the circuit of house dog 1 thinks that the program of CPU2 moved undesiredly, and it will produce a reset level resets CPU2.This interval time can not be oversize, otherwise system software can not in time reset after going wrong.Because the time that system passes through the network download version is many with respect to the interval length of feeding the dog time, long enough interval time of therefore also wishing to feed dog in the system downloads version.CPU2 does not provide feeding-dog signal in during this.Feed the dog time relatively more in short-term after system start-up, present circuit is difficult to satisfy this requirement.After powering on as the system in Fig. 1, the RESET pin of house dog 1 (MAX706TESA) produces a reset level, and CPU2 is resetted.In MAX706TESA inside a timer is arranged, if the WDI pin does not change in time T, WDO will produce a reset level and export to WR by resistance, make RESET produce the output that resets, and cause CPU2 to reset.
In Fig. 2, a programming device of polyphone (CPLD) 3 in the middle of the output that resets of reset input and the house dog 1 of CPU2.At the initial time of system power-on reset, the input that resets that the output that resets of house dog 1 is exported to CPU2 by CPLD3; After reset level raises, disconnect the getting in touch of the input that resets of reset output and the CPU2 of house dog 1 by CPLD3.This moment, CPU2 did not provide feeding-dog signal to house dog 1; Through behind the regular hour T, house dog 1 produces the output that resets.Owing to disconnected the getting in touch of the input that resets of reset output and the CPU2 of house dog 1 this moment, so as usual operation of CPU2.Timer with house dog 1 chip internal when the circuit generation of house dog 1 resets output resets, and timer restarts regularly.If feeding-dog signal is not provided, will produce the output that resets once more after time T; Think after twice variation takes place feeding-dog signal that when CPLD3 detects version program starts working, at this moment connect the input that resets of reset output and the CPU2 of house dog 1.If still do not providing feeding-dog signal at the output back CPU2 that resets through N, illustrate that CPU2 work is undesired, still to connect the input that resets of reset output and the CPU2 of house dog 1, process T house dog 1 chip reset CPU2 after the time.
From the above mentioned, the present invention does not need CPU2 that feeding-dog signal be provided to system from downloaded before the intact version at system power-on reset.After system start-up, CPU2 must provide short feeding-dog signal at interval.
For obtaining multiple application, programming device 3 can adopt assorted programmable logic device (PLD) (CPLD), or erasable programmable device (EPLD).
In Fig. 3, the reset circuit of a kind of embedded system of the present invention, the idiographic flow step of its control method is as follows:
1, system power-on reset,
2, watchdog chip output low level reset signal, reset signal is exported to CPU through CPLD;
3, after reset level raise, CPLD disconnected watchdog chip output and gets in touch with the cpu reset input;
4, CPLD counts the watchdog chip number of resets, detects the variation of feeding the dog level simultaneously;
A. if cpu system starts in time N*T, the I/O pin of CPU is exported feeding-dog signal, and CPLD detects the variation of twice hello dog level, and the connection watchdog chip resets to export with cpu reset and imports, and system normally moves;
B. if cpu system (version) starts failure in time N*T, the I/O pin of CPU is not exported feeding-dog signal, and CPLD connection watchdog chip resets and exports and the cpu reset input, and T system reset after the time repeats said process;
5, after the normal operation of system, CPU produces a warm reset for a certain reason, and watchdog chip resetted to export with the cpu reset input and linked to each other this moment, but CPU can not provide feeding-dog signal during system start-up, and house dog produces the output that resets behind the elapsed time T.
In Fig. 4, the reset circuit of embedded system of the present invention, at the appointed time interior CPU can move, and the operation back is by the emulation sequential chart of hand-reset.Whether can be used to checking system hand-reset in operational process by this l-G simulation test works on time.
In Fig. 5, the reset circuit of embedded system of the present invention, at the appointed time interior CPU can move, and the emulation sequential chart when flying runs in system in working routine.Can be used to checking system by this l-G simulation test and in the operational process program, run situation when flying.
In Fig. 6, the reset circuit of embedded system of the present invention, system in start-up course by the emulation sequential chart of hand when resetting.Whether can be used to checking system hand-reset in start-up course by this l-G simulation test works on time.
In Fig. 7, the reset circuit of embedded system of the present invention, the analogous diagram that at the appointed time interior CPU can not move.Whether system resets again when can be used to checking system and can not start at the appointed time by this l-G simulation test.
Claims (4)
1. the reset circuit of an embedded system, comprise microprocessor and house dog, the input that resets of microprocessor is connected with the output that resets of house dog, it is characterized in that, the input that resets of microprocessor is connected the middle programming device that is provided with the output that resets of house dog.
2. the reset circuit of a kind of embedded system according to claim 1 is characterized in that, programming device is a CPLD.
3. the reset circuit of a kind of embedded system according to claim 1 is characterized in that, programming device is the erasable programmable device.
4. the control method of the reset circuit of a kind of embedded system according to claim 1 comprises the following steps:
(1) system power-on reset,
(2) watchdog chip output low level reset signal is exported to microprocessor through programming device;
(3) after reset level raise, programming device disconnected watchdog chip output and getting in touch that microprocessor resets and imports;
(4) programming device is counted the number of resets of watchdog chip, detects the variation of feeding the dog level simultaneously;
A. microprocessor system starts in time N*T, after output feeding-dog signal, programming device detect the variation of feeding the dog level for twice, connects watchdog chip output and the microprocessor input that resets that resets, and system normally moves;
B. microprocessor system starts failure in time N*T, and microprocessor is not exported feeding-dog signal, and programming device connects watchdog chip output and the microprocessor input that resets that resets, T system reset after the time, repetition said process;
(5) after the normal operation of system, microprocessor is if produce a warm reset, and link to each other watchdog chip output and the microprocessor input that resets that resets this moment, the house dog generation output that resets behind the elapsed time T.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031233333A CN100373328C (en) | 2002-12-24 | 2003-04-16 | Reset circuit and control method for embedded system |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| CN02292868 | 2002-12-24 | ||
| CN02292868.5 | 2002-12-24 | ||
| CNB031233333A CN100373328C (en) | 2002-12-24 | 2003-04-16 | Reset circuit and control method for embedded system |
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| CN1510565A true CN1510565A (en) | 2004-07-07 |
| CN100373328C CN100373328C (en) | 2008-03-05 |
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| CNB031233333A Expired - Fee Related CN100373328C (en) | 2002-12-24 | 2003-04-16 | Reset circuit and control method for embedded system |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1329793C (en) * | 2005-11-25 | 2007-08-01 | 华为技术有限公司 | Method for distinguishing system power-on reset and live-line reset |
| CN100354832C (en) * | 2005-01-05 | 2007-12-12 | 杭州华三通信技术有限公司 | Watch-dog Circuit |
| CN100397353C (en) * | 2006-07-26 | 2008-06-25 | 华为技术有限公司 | System and method for raising single-board exception handling ability |
| CN103793251A (en) * | 2014-02-20 | 2014-05-14 | 山东超越数控电子有限公司 | Implementation method for universality of computer start logic |
| US8764636B2 (en) | 2005-06-21 | 2014-07-01 | Olympus Medical Systems Corp. | Electronic endoscopic apparatus |
| CN102004535B (en) * | 2009-09-02 | 2015-06-17 | 康佳集团股份有限公司 | Electronic system and resetting method thereof |
| CN105446446A (en) * | 2015-12-12 | 2016-03-30 | 西安交通大学 | Power supply control device and method of hardware watchdog |
| CN106201755A (en) * | 2016-07-11 | 2016-12-07 | 锐捷网络股份有限公司 | The repositioning method of the network equipment and device |
| CN106933319A (en) * | 2016-11-25 | 2017-07-07 | 科诺伟业风能设备（北京）有限公司 | A kind of current transformer DSP electrification reset control methods |
| CN112783070A (en) * | 2021-01-20 | 2021-05-11 | 深圳市雷能混合集成电路有限公司 | Singlechip power-on processing method and device |
| CN113558622A (en) * | 2021-08-06 | 2021-10-29 | 河南大学 | Wearable bladder urine volume detection system |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101673135B (en) * | 2009-10-14 | 2011-07-27 | 昆明理工大学 | Output safety setting circuit based on ARM embedding system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0851350A3 (en) * | 1996-11-12 | 1999-02-17 | WaferScale Integration Inc. | Programmable independent watchdog circuitry |
| US6260162B1 (en) * | 1998-10-31 | 2001-07-10 | Advanced Micro Devices, Inc. | Test mode programmable reset for a watchdog timer |
| KR20020069689A (en) * | 2001-02-27 | 2002-09-05 | 엘지이노텍 주식회사 | Watchdog timer of program capable of controlling like software |
-
2003
- 2003-04-16 CN CNB031233333A patent/CN100373328C/en not_active Expired - Fee Related
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100354832C (en) * | 2005-01-05 | 2007-12-12 | 杭州华三通信技术有限公司 | Watch-dog Circuit |
| US8764636B2 (en) | 2005-06-21 | 2014-07-01 | Olympus Medical Systems Corp. | Electronic endoscopic apparatus |
| CN1329793C (en) * | 2005-11-25 | 2007-08-01 | 华为技术有限公司 | Method for distinguishing system power-on reset and live-line reset |
| CN100397353C (en) * | 2006-07-26 | 2008-06-25 | 华为技术有限公司 | System and method for raising single-board exception handling ability |
| CN102004535B (en) * | 2009-09-02 | 2015-06-17 | 康佳集团股份有限公司 | Electronic system and resetting method thereof |
| CN103793251A (en) * | 2014-02-20 | 2014-05-14 | 山东超越数控电子有限公司 | Implementation method for universality of computer start logic |
| CN105446446A (en) * | 2015-12-12 | 2016-03-30 | 西安交通大学 | Power supply control device and method of hardware watchdog |
| CN105446446B (en) * | 2015-12-12 | 2019-01-08 | 西安交通大学 | A kind of hardware watchdog power control and method |
| CN106201755A (en) * | 2016-07-11 | 2016-12-07 | 锐捷网络股份有限公司 | The repositioning method of the network equipment and device |
| CN106201755B (en) * | 2016-07-11 | 2019-06-14 | 锐捷网络股份有限公司 | The repositioning method and device of the network equipment |
| CN106933319A (en) * | 2016-11-25 | 2017-07-07 | 科诺伟业风能设备（北京）有限公司 | A kind of current transformer DSP electrification reset control methods |
| CN112783070A (en) * | 2021-01-20 | 2021-05-11 | 深圳市雷能混合集成电路有限公司 | Singlechip power-on processing method and device |
| CN112783070B (en) * | 2021-01-20 | 2024-05-07 | 深圳市雷能混合集成电路有限公司 | Singlechip power-on processing method and device |
| CN113558622A (en) * | 2021-08-06 | 2021-10-29 | 河南大学 | Wearable bladder urine volume detection system |
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|---|---|
| CN100373328C (en) | 2008-03-05 |
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Effective date of registration: 20051216 Address after: Shenzhen Nanshan District hi tech Industrial Park Science and technology south road Zhongxing building law department Applicant after: ZTE Corporation Address before: No. 396, Shanghai, Guilin Road Applicant before: Shanghai Inst. of No.2, Zhongxing Communication Co., Ltd., Shenzhen City |
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