CN1329793C

CN1329793C - Method for distinguishing system power-on reset and live-line reset

Info

Publication number: CN1329793C
Application number: CNB2005101241025A
Authority: CN
Inventors: 李刚
Original assignee: Huawei Technologies Co Ltd
Current assignee: Beijing property right Bats Exchange Inc
Priority date: 2005-11-25
Filing date: 2005-11-25
Publication date: 2007-08-01
Anticipated expiration: 2025-11-25
Also published as: CN1776566A

Abstract

The present invention provides a method for distinguishing system power-on resetting and electrified resetting. A register is arranged in a programmable logic device, a value A is given during power-on resetting of the register by using the function of prearrangement of power-on resetting of the programmable logic device, and a resetting value caused by other peripheral operation (I/O pin or register writing operation) is B. After a CPU is started and before the CPU resets the programmable logic device, the value of the registor is firstly read, and if the value of the register is A, the power-on resetting is executed; if not, the electrified resetting is executed, and then, the CPU resets the programmable logic device for preparation for the next judgment. With regard to the system of which the periphery is provided with the programmable logic device, extra hardware cost does not need to be added, and the power-on resetting and the electrified resetting of the system can be reliably and simply distinguished.

Description

Distinguishing system power-on reset and the charged method that resets

Technical field

The invention belongs to Circuits System resetting technique field, relate in particular to a kind of distinguishing system power-on reset and the charged method that resets.

Background technology

Some equipment need be distinguished system reset triggering factors (electrification reset still is charged resetting) after system restart, existing common method is to use the peripheral SRAM of CPU to judge, write specific data (following is example with 0x55) toward certain storage space of SRAM after the system start-up, after starting, system reset reads the data of identical address again, if be still 0x55, think that then system is charged resetting, if be other any value, then is judged as electrification reset.There are two problems in the method:

1, the CPU periphery does not often have SRAM, considers it is very unworthy from the cost aspect if consider to increase a SRAM from the judgement demand that resets specially in such cases;

2, SRAM is a random access memory, and after powering on, each storage space data is uncertain, has the back object space that the powers on possibility identical with presetting number (0x55 mentioned above), and therefore, judgement is insecure, and the possibility of erroneous judgement is arranged.

Therefore, the situation of reset types can't be reliably judged in existence at present.

Summary of the invention

In order to overcome the existing reliably deficiency of decision circuitry system reset type, provide a kind of programming device register distinguishing system power-on reset and charged method that resets utilized.

This paper provides a kind of distinguishing system power-on reset and the charged method that resets, and comprising:

But enable the register electrification reset preparatory function of programmable logic device (PLD), after the electrification reset, the value of establishing corresponding register is predisposed to A so; To device programming, register is set resets (referring to by the IO pin or write register reset) value for B (B is not equal to A), after system's (referring to CPU or microcontroller) starts, read the value of corresponding register, if be A, then be judged as electrification reset, otherwise be judged as charged resetting.

System read the value of corresponding register before the programmable logic device (PLD) that resets.

Resetting of programmable logic device (PLD) directly or indirectly controlled by system.

The invention has the beneficial effects as follows: for complicated slightly Circuits System, the CPU periphery generally all can have CPLD or FPGA to make Glue Logic, and memory interface generally also is the software development Convenient interface, adopt the present invention (only to take logical resource seldom) not increasing under any system hardware condition of cost, need not upgrading hardware and can reliably, simply distinguish electrification reset and charged resetting, can be widely used in having each electronic product of judgement demand of resetting.

Description of drawings

Fig. 1 is the trigger of 1 (or 0) for the D end;

Fig. 2 is not intended to for input directly drives output;

Fig. 3 is 0 for the register electrification reset, and is irrelevant with trigger D end.

Embodiment

Characteristics difference electrification reset and charged resetting that the present invention utilizes programming device register power-up state can predict/be provided with.At present a lot of programming devices provides electrification reset (PoR) function that register can be provided with, and judges that therefore electrification reset and charged resetting only need do following processing:

But 1, enable the register electrification reset pre-value function of programming device during logical design;

2, in the logical design, make the corresponding effectively later on register of programming device Reset signal reset to certain value different with electrification reset.

CPU before the programming device that do not reset, can judge that according to the value of this register electrification reset still is charged resetting after starting.

A preferred embodiment of the present invention is described in detail in detail below.

It is electrification reset or charged resetting that certain network equipment requires distinguishing system.If electrification reset, the DDR-SDRAM of self check CPU mini system after then resetting, and in journal file recording reset types (electrification reset) and temporal information; If charged resetting, the DDR-SDRAM of self check CPU mini system no longer after then resetting, and in journal file, note down reset types (charged resetting) and temporal information.

Certain CPLD of company a slice of using as adhesive logic is arranged on the veneer CPU mini system, and CPLD hangs on the LocalBus of CPU, provides access interface in the SRAM mode in logic.

In the IDE of the said firm compile option is provided with, have power-up don ' t care option provide to this function enable select.If choose, so, the later buffer status of power-up initializing is directly related with synthesis result, and the state of register trigger D end state when powering on determines that the state of Fig. 1 during powering on is equivalent to Fig. 2.That is to say that the Q end also is 1 if the D end is 1, if the D end is 0, the Q end also is 0.If do not choose power-up don ' tcare, so, no matter how trigger D holds state during powering on, the value of register all was 0 (as shown in Figure 3).This option is that the overall situation is effective for whole design, can bring certain area overhead.The device of all these development environment supports all has this function.

At first, in the logical code design 8bit register is set, (refers to that effective reset signal appears in reset pin, do not comprise electrification reset) be set to 0x55 when resetting, this register is read-only can not be write (preventing written in software operation destruction marking position); Be one section simple code sample that Verilog describes below:

module?powerup(Data，Addr，Wr，Rd，Rst，CS)；

inout[7:0]Data；

input[2:0]Addr；

input?Wr，Rd，Rst，CS；

wire?PldWr，PldRd；

reg[7:0]PoR；

reg[7:0]Reg1，Reg2，Reg3；

reg[7:0]DataIn；

assign?PldWr＝(CS＝1′b1&&Rd＝1′b1)？1:Wr；

assign?PldRd＝(CS＝1?′b1)？1:Rd；

assign?Data＝(PldRd＝1′b1)？8′bzzzzzzzz:DataIn；

always@(posedge?PldWr?or?negedge?Rst)

if(！Rst)

begin

PoR＜=8 ' h55; // reset initialization position 0x55

Reg1＜＝8′h00；

Reg2＜＝8′h00；

Reg3＜＝8′h00；

end

else

Case (Addr) // not is to the write operation of PoR, and promptly PoR is read-only, and CPU can't rewrite;

3′b001:Reg1＜＝Data；

3′b010:Reg2＜＝Data；

3′b011:Reg3＜＝Data；

default:；

endcase

always@(negedge?PldRd)

case(Addr)

3′b000:DataIn＜＝PoR；

3′b001:DataIn＜＝Reg1；

3′b010:DataIn＜＝Reg2；

3′b011:DataIn＜＝Reg3；

default:DataIn＜＝8′h11；

endcase

endmodule

Annotate: if the PoR bit wide is made as 1, then only take a trigger on the resource, need not 8.

Hook falls (not choosing) Verilog the compiler option power-up don ' t care;

Other place of logic design phase changes according to not needing.

On hardware design, can not directly receive the output that resets of house dog and so on the CPLD, because watchdog chip commonly used provides electrification reset, after powering on, can send reset pulse, this moment, CPLD resetted after being actually and receiving the Reset signal, destroyed the register primary data behind the electrification reset, other similar processing can be sent or use to the reset signal of CPLD by the GPIO of CPU.In a word, after powering on, the reset signal of CPLD should directly or indirectly be controlled (as: by writing reseting register control) by CPU.

On software design, CPU judges that the step of reset mode is as follows:

1, CPU starts;

2, read the corresponding PoR register of CPLD;

If 3 PoR are 0x55, then be judged as charged resetting, follow-uply do not do the internal memory self check, and the record log event is charged resetting; If PoR is 0x00, then be judged as electrification reset, follow-uply do the internal memory self check, and the record log event is an electrification reset;

4, the CPLD that resets makes it all registers and enters predetermined state, the start-up system other parts.

Claims

1, a kind of distinguishing system power-on reset and the charged method that resets comprise:

But enable the register electrification reset prevalue function of programmable logic device (PLD), after the electrification reset, register can be made as prevalue automatically;

To the programming of described programmable logic device (PLD), register is set by the IO pin or write the value that register resets, this reset values is different from above-mentioned prevalue;

After the system start-up, read the data of described register,, then be judged as electrification reset if these data are above-mentioned prevalue; If these data are not above-mentioned prevalues, then be judged as charged resetting.

2, distinguishing system power-on reset as claimed in claim 1 and the charged method that resets, it is characterized in that: system read the value of described register before the programmable logic device (PLD) that resets.

3, distinguishing system power-on reset as claimed in claim 1 or 2 and the charged method that resets is characterized in that: resetting of programmable logic device (PLD) directly or indirectly controlled by system.