CN103793251A - Implementation method for universality of computer start logic - Google Patents
Implementation method for universality of computer start logic Download PDFInfo
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- CN103793251A CN103793251A CN201410056288.4A CN201410056288A CN103793251A CN 103793251 A CN103793251 A CN 103793251A CN 201410056288 A CN201410056288 A CN 201410056288A CN 103793251 A CN103793251 A CN 103793251A
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Abstract
The invention discloses an implementation method for the universality of computer start logic. The method relates to a start switch, a CPLD control chip, a power-on chip and a power supply. Signals of the start switch, switching signals of the power-on chip end, power supply enable signals of the power-on chip and enable signals of the power supply end are respectively connected to the CPLD control chip so that all the signals can be controlled by the CPLD control chip in a bridging connection mode. By using different CPLD firmware programs, the compatibility of the start switch can be achieved in a same computer without changing any hardware, and thus the universality of the computer start logic is achieved. The method is easy to operate, good in stability and high in controllability, the modular usage rate of enterprise products can be obviously increased, and production cost can be reduced.
Description
Technical field
The present invention relates to the technical field of computer starting, comprise the equipment such as server, computing machine, computing terminal; Relate in particular to the implementation method of the enable logic versatility of the extraordinary ruggedized computer with specific (special) requirements.
Technical background
Along with the development of modernization information construction, increasing computing machine kind is constantly born, each computing machine has its unique requirement separately, so also not obvious for the performance difference requirement of computing machine own with regard to a certain specific period, its difference is mainly reflected in peripheral components or structure, such as expanding the difference of demand and the difference of complete machine Starting mode for PCI, PCI-E, etc.Conventionally ruggedized computer is because its each side of its unique environment for use requires also different from non-reinforcing machine, it has higher specific customization requirement, as wide warm nature can be better, reliability is higher, and some ruggedized computer needs specific Starting mode to improve reliability in its use procedure, prevent false touch etc.
In ruggedized computer, electrifying startup triggers different enable logics with self-resetting switch and locked switch conventionally.For have same performance require but the computing machine of different enable logics meets this specific (special) requirements with change hardware under normal circumstances.
The present invention designs and adopts CPLD control chip to connect signal, can be according to different starting switch signals, realize identical startup result, identical for performance requirement, the computing machine of starting switch difference (self-resetting switch starts and be locked switch activated) can not changed on the basis of any hardware, realize the versatility of enable logic by the CPLD firmware with different, this design has simple to operate, controllability is strong, be convenient to the features such as maintenance, can realize same hardware core (mainboard because not needing to do any change, base plate and power supply) composition different requirements computing machine, therefore this design also has significant modularization for enterprise, low cost feature.
CPLD is Complex Programmable Logic Device(CPLD) abbreviation, representative be a kind of programmable logic device (PLD), it can be after manufacture completes need to define its logic function by user according to itself.
Summary of the invention
The technical problem to be solved in the present invention is: by using different CPLD firmware programs, in same computer, do not need to change any hardware and can realize the compatibility of starting switch, and then reach the versatility of computer starting logic.
The technical solution adopted in the present invention is:
A kind of implementation method of computer starting logical general, comprise starting switch, CPLD control chip, upper electrical chip, power supply, wherein, the signal of starting switch, the switching signal of the die terminals that powers on, the power enable signal of upper electrical chip and the enable signal of power end are connected respectively to CPLD control chip, use CPLD control chip to carry out bridge joint control to each signal.
Using when self-resetting switch, in CPLD control chip inside, the switching signal of the signal of starting switch and the die terminals that powers on is done direct-connectedly, the power enable signal of upper electrical chip and power enable end are done direct-connected; Under this kind of mode: it is low that switching signal is that low this signal of die terminals that powers on is, switching signal is that height this signal of die terminals that powers on is height; The die terminals that simultaneously powers on power enable signal effectively power end enables to be effectively (opening power), the die terminals that powers on power enable signal is that inactive power sources end enables to be invalid (powered-down), CPLD control chip is completely transparent for starting switch, upper electrical chip and power supply, and the on/off of start and shutdown is by the chip controls that powers on;
In the time using locked switch, there is two states in this kind of starting switch: open and close, in the time using this kind of switch, first CPLD control chip captures switching signal, and carries out different control according to the difference of switching signal; In the time that starting switch is opened, power-on pulse signal is sent in CPLD simulation, gives upper electrical chip by this signal, and keep supplying electrical chip and do other actions that powers on, and the effective enable signal control of the power supply power enable end opening power of returning according to upper electrical chip; In the time that starting switch cuts out, CPLD control chip directly sends power enable shutdown signal, by power-off; When normal shutdown computer-chronograph executes shutdown programm, it is invalid that upper electrical chip is set to power enable signal, and CPLD control chip is also controlled power enable end by power-off after receiving this signal.Above cycle of states realizes.
Beneficial effect of the present invention is:
The present invention, by using different CPLD firmware programs, in same computer, does not need to change any hardware and can realize the compatibility of starting switch, and then reach the versatility of computer starting logic.The method not only simple to operate but also good stability, controllability is strong, can improve significantly the modularization utilization rate of the product of enterprise, reduces production costs.
Accompanying drawing explanation
Fig. 1 is computer starting control block diagram;
Fig. 2 is self-resetting switch CPLD control linkage schematic diagram;
Fig. 3 is locked switch CPLD control program process flow diagram.
Embodiment
With reference to the accompanying drawings, by embodiment, the present invention is further described:
As shown in Figure 1, a kind of implementation method of computer starting logical general, comprise starting switch, CPLD control chip, upper electrical chip, power supply, wherein, the signal of starting switch, the switching signal of the die terminals that powers on, the power enable signal of upper electrical chip and the enable signal of power end are connected respectively to CPLD control chip, use CPLD control chip to carry out bridge joint control to each signal.
As shown in Figure 2, using when self-resetting switch, in CPLD control chip inside, the switching signal of the signal of starting switch and the die terminals that powers on is done direct-connectedly, the power enable signal of upper electrical chip and power enable end are done direct-connected; Under this kind of mode: it is low that switching signal is that low this signal of die terminals that powers on is, switching signal is that height this signal of die terminals that powers on is height; The die terminals that simultaneously powers on power enable signal effectively power end enables to be effectively (opening power), the die terminals that powers on power enable signal is that inactive power sources end enables to be invalid (powered-down), CPLD control chip is completely transparent for starting switch, upper electrical chip and power supply, and the on/off of start and shutdown is by the chip controls that powers on;
In the time using locked switch, there is two states in this kind of starting switch: open and close, in the time using this kind of switch, first CPLD control chip captures switching signal, and carries out different control according to the difference of switching signal; As shown in Figure 3, in the time that starting switch is opened, power-on pulse signal is sent in CPLD simulation, gives upper electrical chip by this signal, and keep supplying electrical chip and do other actions that powers on, and the effective enable signal control of the power supply power enable end opening power of returning according to upper electrical chip; In the time that starting switch cuts out, CPLD control chip directly sends power enable shutdown signal, by power-off; When normal shutdown computer-chronograph executes shutdown programm, it is invalid that upper electrical chip is set to power enable signal, and CPLD control chip is also controlled power enable end by power-off after receiving this signal.Above cycle of states realizes.
Claims (3)
1. the implementation method of a computer starting logical general, comprise starting switch, CPLD control chip, upper electrical chip, power supply, it is characterized in that: the signal of starting switch, the switching signal of the die terminals that powers on, the power enable signal of upper electrical chip and the enable signal of power end are connected respectively to CPLD control chip, use CPLD control chip to carry out bridge joint control to each signal.
2. the implementation method of a kind of computer starting logical general according to claim 1, it is characterized in that: in the time using self-resetting switch, in CPLD control chip inside, the signal of starting switch and the switching signal of die terminals of powering on are done direct-connectedly, the power enable signal of upper electrical chip and power enable end are done direct-connected; Under this kind of mode: it is low that switching signal is that low this signal of die terminals that powers on is, switching signal is that height this signal of die terminals that powers on is height; The die terminals that simultaneously powers on power enable signal effectively power end enables to be effectively, it is invalid that the die terminals that powers on power enable signal is that inactive power sources end enables to be, CPLD control chip is completely transparent for starting switch, upper electrical chip and power supply, and the on/off of start and shutdown is by the chip controls that powers on.
3. the implementation method of a kind of computer starting logical general according to claim 1, it is characterized in that: in the time using locked switch, there is two states in this kind of starting switch: opens and closes, in the time using this kind of switch, first CPLD control chip captures switching signal, and carries out different control according to the difference of switching signal; In the time that starting switch is opened, power-on pulse signal is sent in CPLD simulation, gives upper electrical chip by this signal, and keep supplying electrical chip and do other actions that powers on, and the effective enable signal control of the power supply power enable end opening power of returning according to upper electrical chip; In the time that starting switch cuts out, CPLD control chip directly sends power enable shutdown signal, by power-off; When normal shutdown computer-chronograph executes shutdown programm, it is invalid that upper electrical chip is set to power enable signal, and CPLD control chip is also controlled power enable end by power-off after receiving this signal.
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| CN201410056288.4A CN103793251A (en) | 2014-02-20 | 2014-02-20 | Implementation method for universality of computer start logic |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103995576A (en) * | 2014-06-06 | 2014-08-20 | 山东超越数控电子有限公司 | Computer power supply management method based on CPLD |
| CN104460440A (en) * | 2014-11-18 | 2015-03-25 | 中国兵器工业集团第二一四研究所苏州研发中心 | Programmable logic device internal highly-reliable automatic reset method |
| CN112579186A (en) * | 2020-12-29 | 2021-03-30 | 合肥市卓怡恒通信息安全有限公司 | Terminal based on Loongson platform and starting method thereof |
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| CN101738977A (en) * | 2009-11-24 | 2010-06-16 | 福建星网锐捷网络有限公司 | Method for switching operating mode of main control chip and network equipment thereof |
| CN201773350U (en) * | 2010-03-10 | 2011-03-23 | 深圳华北工控股份有限公司 | Computer master control board power supply management module for PCTV integrated machine |
| CN103592865A (en) * | 2013-11-22 | 2014-02-19 | 绵阳市维博电子有限责任公司 | Startup and shutdown control system, startup and shutdown control method and safe startup and shutdown power supply |
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- 2014-02-20 CN CN201410056288.4A patent/CN103793251A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1510565A (en) * | 2002-12-24 | 2004-07-07 | 深圳市中兴通讯股份有限公司上海第二 | Reset circuit and control method for embedded system |
| CN101738977A (en) * | 2009-11-24 | 2010-06-16 | 福建星网锐捷网络有限公司 | Method for switching operating mode of main control chip and network equipment thereof |
| CN201773350U (en) * | 2010-03-10 | 2011-03-23 | 深圳华北工控股份有限公司 | Computer master control board power supply management module for PCTV integrated machine |
| CN103592865A (en) * | 2013-11-22 | 2014-02-19 | 绵阳市维博电子有限责任公司 | Startup and shutdown control system, startup and shutdown control method and safe startup and shutdown power supply |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103995576A (en) * | 2014-06-06 | 2014-08-20 | 山东超越数控电子有限公司 | Computer power supply management method based on CPLD |
| CN104460440A (en) * | 2014-11-18 | 2015-03-25 | 中国兵器工业集团第二一四研究所苏州研发中心 | Programmable logic device internal highly-reliable automatic reset method |
| CN104460440B (en) * | 2014-11-18 | 2017-02-01 | 中国兵器工业集团第二一四研究所苏州研发中心 | Programmable logic device internal highly-reliable automatic reset method |
| CN112579186A (en) * | 2020-12-29 | 2021-03-30 | 合肥市卓怡恒通信息安全有限公司 | Terminal based on Loongson platform and starting method thereof |
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Application publication date: 20140514 |