CN104467799B - Imput output circuit device - Google Patents
Imput output circuit device Download PDFInfo
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- CN104467799B CN104467799B CN201310415468.2A CN201310415468A CN104467799B CN 104467799 B CN104467799 B CN 104467799B CN 201310415468 A CN201310415468 A CN 201310415468A CN 104467799 B CN104467799 B CN 104467799B
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Abstract
The invention discloses a kind of imput output circuit device, imput output circuit device includes output circuit, biasing circuit and input circuit, and output circuit is connected by biasing circuit with input circuit；Input circuit is used to connect the first input signal and input signal；Output circuit is used for Rreceive output signal and biasing produces signal and electrically connected with input/output port；Biasing circuit includes series resistance division module, electric capacity keeps voltage module and control module；Series resistance division module is used for according to voltage-regulation the first input signal end of input/output port and the operating voltage at the second input signal end；Control module is used for the operating voltage for controlling biasing to produce signal end according to the voltage signal at the second input signal end；Electric capacity keeps voltage module to be used for the operating voltage for keeping biasing to produce signal end.Its effectively avoid local power supply without in the case of electricity input/output port connection the amplitude of oscillation be 5V voltage signals when, the impaired phenomenon of MOS transistor.
Description
Technical field
The present invention relates to integrated circuit, more particularly to a kind of imput output circuit that can bear 5V voltage signals.
Background technology
Along with the fast development of electronics and information industry, the speed of data transfer is growing day by day, between chip and chip, sets
The standby various interface protocols between equipment emerge in an endless stream.The protocol requirement of many of which has the input of 5V signal work ranges
Output circuit (or 5V voltage detecting circuits), and it is generally integrated the active device that circuit uses --- metal oxide is partly led
Body FET (metal-oxide-semiconductor filed effect transistor, abbreviation MOS transistor)
Rated insulation voltage between any two port is 3.3V, is directly applied in the working environment of 5V signals, can cause the damage of device
It is bad.Therefore, how the MOS transistor for the use of rated insulation voltage being 3.3V carrys out the imput output circuit that the modelled signal amplitude of oscillation is 5V, and
And ensure to be not damaged by the problem of just challenging as one in device in the case that local power supply is invalid.
The content of the invention
Based on this, it is necessary to during for local power supply without electricity, input/output port 5V_IO voltage is 5V, MOS in circuit
A kind of the problem of transistor is easily damaged, there is provided imput output circuit device.
To realize the object of the invention, there is provided a kind of imput output circuit device, it is characterised in that including input circuit,
Biasing circuit and output circuit：
The input circuit electrically connects with the biasing circuit, for connecting the first input signal and input signal；
The biasing circuit electrically connects with input/output port and the input circuit, and export the first input signal and partially
Put generation signal；
The output circuit electrically connects with input/output port and the biasing circuit, for Rreceive output signal and described
Biasing produces signal.
In one of the embodiments, the biasing circuit includes series resistance division module, electric capacity keeps voltage module
And control module：
The series resistance division module the first input signal with the input/output port, the input circuit respectively
End, the second input signal end of the control module and the electrical connection of the 3rd input signal end, for according to input/output port
The operating voltage at the first input signal end and the second input signal end described in voltage-regulation；
The control module produces signal end with the second input signal end, biasing and supply voltage electrically connects, and is used for
The operating voltage of signal end, the supply voltage are produced according to the voltage signal at the second input signal end control biasing
For 3.3V；
The electric capacity keeps voltage module to be series at the biasing of the control module and produces signal end and earth terminal, for protecting
Hold the operating voltage that the biasing produces signal end；
The 3rd input signal end electrically connects with earth terminal.
In one of the embodiments, the biasing circuit also includes mode selection module, the mode selection module string
It is coupled between the 3rd input signal end and earth terminal, and receives the biasing and produce signal and output mode selection signal.
In one of the embodiments, the mode selection module includes the 3rd phase inverter and the 5th transistor, and described
The grid of five transistors is connected with the output end of the 3rd phase inverter；
Substrate, source electrode and the earth terminal of 5th transistor connect, the drain electrode and the described 3rd of the 5th transistor
Input signal end electrically connects；
The operating voltage of 3rd phase inverter produces the voltage of signal end for the biasing.
In one of the embodiments, the control module includes the first transistor and second transistor, and described first is brilliant
The grid of body pipe is connected with the source electrode of the second transistor and is coupled to the second input signal end；
The drain electrode of the first transistor, the substrate of the first transistor, the substrate of second transistor and second transistor
Drain electrode connects and produces signal end coupled to the biasing；
The source electrode of the first transistor is connected with the grid of the second transistor and is coupled to the supply voltage.
In one of the embodiments, the electric capacity keeps voltage module to include capacitor, and described capacitor one end is with connecing
Ground terminal connects, and the other end produces signal end coupled to the biasing of the control module.
In one of the embodiments, the output circuit includes third transistor, the 4th transistor and the first phase inverter,
The substrate of the third transistor, the source electrode of third transistor, the substrate of the 4th transistor connect and are coupled to earth terminal；
The grid of the third transistor is connected with the output end of first phase inverter, the drain electrode of the third transistor
It is connected with the source electrode of the 4th transistor；
The drain electrode of 4th transistor is connected with the input/output port；
The grid voltage of 4th transistor produces signal end voltage for the biasing.
In one of the embodiments, the series resistance division module includes first resistor, second resistance and the 3rd electricity
Resistance, the second resistance are series between the first resistor and the 3rd resistor, and the other end of the first resistor is with connecing
Ground terminal connects, and the other end of the 3rd resistor electrically connects with the input/output port；
The connection end of the first resistor and the second resistance is coupled to the second input signal end of the control module；
The connection end of the second resistance and the 3rd resistor is coupled to the first input signal end of the input circuit.
In another embodiment, the series resistance division module includes first resistor, second resistance and 3rd resistor,
The second resistance is series between the first resistor and the 3rd resistor, the other end and earth terminal of the first resistor
Connection, the other end of the 3rd resistor electrically connect with the input/output port；
The connection end of the first resistor and the second resistance is coupled to the first input signal end of the control module；
The connection end of the second resistance and the 3rd resistor is coupled to the second input signal end of the input circuit.
In one of the embodiments, the input circuit includes the second phase inverter, the second inverter input coupling
The first input signal end is bonded to, second inverter output couples with input signal；
The operating voltage of second phase inverter is 3.3V or 1V；
Second phase inverter includes PMOS, the nmos pass transistor that rated insulation voltage is 3.3V.
In another embodiment, the input circuit includes the second phase inverter, the second inverter input coupling
To the first input signal end, second inverter output couples with input signal；
The operating voltage of second phase inverter is 1V；
Second phase inverter includes PMOS, the nmos pass transistor that rated insulation voltage is 1V.
In one of the embodiments, the first transistor and second transistor are enhanced PMOS；
The third transistor, the 4th transistor and the 5th transistor are enhanced NMOS tube；
First phase inverter and the 3rd phase inverter include PMOS, the nmos pass transistor that rated insulation voltage is 3.3V.
Imput output circuit device provided by the invention includes output circuit, biasing circuit and input circuit, output circuit
It is connected by biasing circuit with input circuit；Input circuit is used to connect the first input signal and input signal；Output circuit is used
Signal is produced in Rreceive output signal and biasing and is electrically connected with input/output port；Biasing circuit includes series resistance partial pressure mould
Block, electric capacity keep voltage module and control module；Series resistance division module is used for the voltage-regulation according to input/output port
First input signal end and the operating voltage at the second input signal end；Control module is used for the voltage according to the second input signal end
Signal control biasing produces the operating voltage of signal end；Electric capacity keeps voltage module to be used to keep the biasing to produce signal end
Operating voltage.Its effectively avoid local power supply without in the case of electricity input/output port connection the amplitude of oscillation be 5V voltage signals when,
The impaired phenomenon of MOS transistor.
Brief description of the drawings
Fig. 1 is the embodiment schematic diagram of imput output circuit device one of the present invention；
Fig. 2 is the another embodiment schematic diagram of imput output circuit device of the present invention；
Fig. 3 is imput output circuit device another embodiment schematic diagram of the present invention；
Fig. 4 is another embodiment schematic diagram of imput output circuit device of the present invention；
Fig. 5 is another embodiment schematic diagram of imput output circuit device of the present invention.
Embodiment
In order that the purpose of the present invention, the technical scheme used and advantage are more clearly understood, below in conjunction with accompanying drawing and tool
The imput output circuit device of the present invention is described in further detail body embodiment.
Referring to Fig. 1, a kind of imput output circuit device of the embodiment of the present invention, including input circuit, biasing circuit and defeated
Go out circuit.
The input circuit electrically connects with the biasing circuit, for connecting the first input signal and input signal；
The biasing circuit electrically connects with input/output port and the input circuit, and export the first input signal and partially
Put generation signal.
The output circuit electrically connects with input/output port and the biasing circuit, for Rreceive output signal and described
Biasing produces signal.
The biasing circuit includes series resistance division module, electric capacity keeps voltage module and control module：
The series resistance division module the first input signal with the input/output port, the input circuit respectively
End, the second input signal end of the control module and the electrical connection of the 3rd input signal end, for according to input/output port
The operating voltage at the first input signal end and the second input signal end described in voltage-regulation；
The control module produces signal end with the second input signal end, biasing and supply voltage electrically connects, and is used for
The operating voltage of signal end, the supply voltage are produced according to the voltage signal at the second input signal end control biasing
For 3.3V；
The electric capacity keeps voltage module to be series at the biasing of the control module and produces signal end and earth terminal, for protecting
Hold the operating voltage that the biasing produces signal end；
The 3rd input signal end electrically connects with earth terminal.
It is preferred that as a kind of embodiment, the biasing circuit also includes mode selection module, the model selection
Block coupled in series receives the biasing and produces signal and output mode selection between the 3rd input signal end and earth terminal
Signal.
Referring to Fig. 2, as one embodiment of the present of invention, a kind of imput output circuit device, for avoiding local power supply
During without electricity, the input/output port 5V_IO connections amplitude of oscillation is 5V voltage signals, the impaired phenomenon of MOS transistor, including output electricity
Road, biasing circuit and input circuit, output circuit are connected by biasing circuit with input circuit；The input of input circuit connection first
Signal and input signal；Output circuit is connected with input/output port, and signal is produced for Rreceive output signal and biasing；
Biasing circuit includes series resistance division module, electric capacity keeps voltage module and control module；
Series resistance division module respectively with input/output port 5V_IO, input circuit the first input signal end IO1,
The second input signal end IO2 and the earth terminal electrical connection of control module, for the voltage-regulation according to input/output port 5V_IO
First input signal end IO1 and the second input signal end IO2 operating voltage；
Control module produces signal end and supply voltage V with the second input signal end IO2, biasingCCElectrical connection, for basis
Second input signal end IO2 voltage signal control biasing produces the operating voltage V of signal endbulk；
Electric capacity keeps voltage module to be series at the biasing of control module and produces signal end and earth terminal, for keeping biasing production
The operating voltage V of raw signal endbulk。
Series resistance division module includes first resistor R0, second resistance R1 and 3rd resistor R2, second resistance R1 series connection
Between first resistor R0 and 3rd resistor R2, the first resistor R0 other end is connected with earth terminal, and 3rd resistor R2's is another
End electrically connects with input/output port 5V_IO；Second resistance R1 and 3rd resistor R2 connection end and the first input signal end IO1
Electrical connection；First resistor R0 and second resistance R1 connection end are coupled to the second input signal end IO2.
Electric capacity keeps voltage module to include capacitor C0, and capacitor C0 one end is connected with earth terminal, and the other end is coupled to inclined
Put generation signal end.
Control module includes the first transistor PMOS0 and second transistor PMOS1, the first transistor PMOS0 grid with
Second transistor PMOS1 source electrode connects and is coupled to the second input signal end IO2；The first transistor PMOS0 drain electrode, first
Transistor PMOS0 substrate, second transistor PMOS1 substrate are connected with second transistor PMOS1 drain electrode and are coupled to partially
Put generation signal end；The first transistor PMOS0 source electrode is connected with second transistor PMOS1 grid and is coupled to supply voltage
VCC。
It is preferred that the first transistor PMOS0 and second transistor PMOS1 are enhanced PMOS.
Output circuit includes third transistor NMOS0, the 4th transistor NMOS1 and the first phase inverter, third transistor
NMOS0 substrate, third transistor NMOS0 source electrode, the 4th transistor NMOS1 source electrode connect and are coupled to earth terminal；The
Three transistor NMOS0 grid is connected with the output end of the first phase inverter, third transistor NMOS0 drain electrode and the 4th transistor
NMOS1 source electrode is connected；4th transistor NMOS1 drain electrode is connected with input/output port 5V_IO；4th transistor
NMOS1 grid voltage produces the voltage V of signal end for biasingbulk。
It is preferred that third transistor NMOS0 and the 4th transistor NMOS1 are enhanced NMOS tube；
Input circuit includes the second phase inverter, and the second inverter input is coupled to the first input signal end IO1, and second is anti-
Phase device output end couples with input signal, and the operating voltage of the second phase inverter is 3.3V or 1V；
It is preferred that the second phase inverter includes PMOS, the nmos pass transistor that rated insulation voltage is 3.3V.
When the operating voltage of the second phase inverter in input circuit is 3.3V, the input/output port is connected to 5V power supplys
When, two kinds of situations can be divided into：
(1) as 3.3V power supplys VCCThere is electricity, input/output port can be connected to 5V power supply by a pull-up resistor, now
By the ratio for designing first resistor R0, second resistance R1 and 3rd resistor R2, it is possible to achieve following relation：
Wherein VIO1For magnitudes of voltage of the first input signal end IO1 when signal is high level, V5V_IO(high)For input and output
Magnitudes of voltage of the port 5V_IO when signal is high level.So realized by adjusting (R0+R1) and R2 ratio to input circuit
The first input signal input maximum voltage value adjustment, be not damaged by with the MOS transistor ensured in input circuit, and
And realize the input of logical signal；
By designing first resistor R0, second resistance R1 and 3rd resistor R2 ratio, following relation can also be realized：
Wherein VIO2(high)For magnitudes of voltage of the second input signal end IO2 when signal is high level, V5V_IO(high)For input
Magnitudes of voltage of the output port 5V_IO when signal is high level.So by adjusting R0 and (R1+R2) ratio, can be achieved
VIO2(high)Compare VCCLow the first transistor PMOS0 threshold value or bigger voltage.So when input/output port 5V_IO is deposited
In 5V signal swing, the first transistor PMOS0 grid is low level, because the first transistor PMOS0 is P-channel MOS
Pipe, so now the first transistor PMOS0 is turned on, biasing produces signal end voltage VbulkEqual to VCC, thus in output circuit
Four transistor NMOS1 grid voltage is VCC, and due to VCCFor 3.3V supply voltages, therefore the 4th normal works of transistor NMOS1
Make, will not be damaged, and then ensure that the normal work of metal-oxide-semiconductor in output circuit.
(2) as 3.3V power supplys VCCDuring without electricity, input/output port 5V_IO is connected to 5V electricity by a pull-up resistor
Source, now, the voltage at the first input signal end IO1 and the second input signal end IO2 can also be essentially pulled up in a short time compared with
High level, thus second transistor PMOS1 source levels are higher level, grid and supply voltage VCCIt is connected, VCCWithout electricity, institute
Using second transistor PMOS1 grids as low level, and because second transistor PMOS1 is P-channel metal-oxide-semiconductor, thus the second crystal
Pipe PMOS1 is turned on, so that biasing produces signal end voltage VbulkAlso high level is pulled to, now, biasing produces signal
Terminal voltage Vbulk, the first input signal end IO1 and the second input signal end IO2 voltage return to 3.3V power supplys VCCWhen having electricity
Situation, therefore can ensure imput output circuit input/output port 5V_IO be 5V in the case of CMOS transistor not by
Damage.
Referring to Fig. 3, it is preferred that as another embodiment of the present invention, when input/output port 5V_IO may be operated in pendulum
When width is the situation of 3.3V signals or 5V signals, biasing circuit also includes mode selection module, and mode selection module is series at
Between first resistor is not connected with second resistance in series resistance division module one end and earth terminal.Mode selection module includes
3rd phase inverter and the 5th transistor NMOS2, the 5th transistor NMOS2 grid are connected with the output end of the 3rd phase inverter；The
Five transistor NMOS2 substrate, source electrode and earth terminal connects, the 5th transistor NMOS2 drain electrode and series resistance division module
One end connection that middle first resistor R0 is not connected with second resistance R1；The operating voltage of 3rd phase inverter produces signal end for biasing
Voltage Vbulk。
It is preferred that the 3rd phase inverter includes PMOS, the nmos pass transistor that rated insulation voltage is 3.3V, the 5th transistor NMOS2
For enhanced NMOS tube；
As embodiment, when input/output port 5V_IO is connected to 3.3V power supplys by a pull-up resistor, by outer
Mode select signal in mode selection module is arranged to 3.3V by portion's system, and now the 5th transistor NMOS2 is in cut-off shape
State, thus voltage of the second input signal end IO2 and the first input signal end IO1 voltage with input/output port 5V_IO
It is worth identical, there is no partial pressure effect for series resistance division module.Due to input/output port 5V_IO signal 0V to 3.3V it
Between swing, when input/output port 5V_IO voltage is 0V, the first transistor PMOS0 grids are low level, and now first is brilliant
Body pipe PMOS0 is turned on, and biasing produces signal end voltage VbulkEqual to VCC, electric capacity keep voltage module in electric capacity C0 keep Vbulk
Do not decline, thereby ensure that the normal work of the 4th transistor NMOS1 in output circuit, quiescent dissipation can also not wasted
In the case of realize imput output circuit function.
As embodiment, when input/output port 5V_IO is connected to 5V power supplys by a pull-up resistor, pattern is selected
The mode select signal selected in module is arranged to 0V.Analyze in two kinds of situation below：
(1) in 3.3V power supplys VCCThere is electricity, input/output port is connected to 5V power supply in short-term by a pull-up resistor
In, it is assumed that the transistor NMOS2 of original state the 5th is cut-off state.Second input signal end IO2 and the first input signal end
IO1 voltage is identical with input/output port 5V_IO magnitude of voltage.Second transistor PMOS1 grid potential is VCC, source electrode
Voltage is the second input signal IO2, therefore second transistor PMOS1 is turned on.Biasing produces signal and can risen in a short time
One higher current potential, now the 5th transistor NMOS2 grid potential can also rise to a higher current potential, cause the 5th
Transistor NMOS2 is turned on.Because the 5th transistor NMOS2 is turned on, first resistor R0, second resistance R1 and the 3rd electricity are rationally designed
The second input signal V can be caused by hindering the series resistance division module of R2 ratioIO2(high)Compare VCCA low the first transistor
PMOS0 threshold value or bigger voltage.Because the first transistor PMOS0 is P-channel metal-oxide-semiconductor, so now the first transistor
PMOS0 is turned on, and biasing produces signal end voltage VbulkDrop to VCC, thus in output circuit the 4th transistor NMOS1 grid
Voltage is VCC, and due to VCCFor 3.3V supply voltages, therefore the 4th transistor NMOS1 normal works, it will not be damaged, and then
It ensure that the normal work of metal-oxide-semiconductor in output circuit.
(2) in 3.3V power supplys VCCWithout electricity, input/output port is connected to 5V power supply in short-term by a pull-up resistor
In, it is assumed that the transistor NMOS2 of original state the 5th is cut-off state.Second input signal end IO2 and the first input signal end
IO1 voltage is identical with input/output port 5V_IO magnitude of voltage.Second transistor PMOS1 grid potential is 0, source electrode
Voltage is the second input signal IO2, therefore second transistor PMOS1 is turned on.Biasing produces signal and can risen in a short time
One higher current potential, now the 5th transistor NMOS2 grid potential can also rise to a higher current potential, cause the 5th
Transistor NMOS2 is turned on.Because the 5th transistor NMOS2 is turned on, first resistor R0, second resistance R1 and the 3rd electricity are rationally designed
The second input signal V can be caused by hindering the series resistance division module of R2 ratioIO2(high)Than 3.3V power supplys VCCIt is normal low when having an electricity
One the first transistor PMOS0 threshold value or bigger voltage.Because second transistor PMOS1 is P-channel metal-oxide-semiconductor, so this
When second transistor PMOS1 conducting, biasing produces signal end voltage VbulkDrop to the second input signal current potential VIO2(high), because
And the 4th transistor NMOS1 grid voltage is equal to the second input signal current potential V in output circuitIO2(high), therefore the 4th crystal
Pipe NMOS1 normal works, will not be damaged.
Referring to Fig. 4, as another embodiment of the present invention, the operating voltage Vdd of the second phase inverter in the input circuit
About 1V, the second phase inverter in input circuit are made up of the PMOS and nmos pass transistor that rated insulation voltage is 3.3V.It is described defeated
When entering output port 5V_IO high level voltage scope more than or equal to 1.5V and being less than or equal to 5V, by reasonably designing first
Resistance R0, second resistance R1 and 3rd resistor R2 ratio, make its satisfaction
Due to 1.5V≤V5V_IO(high)≤ 5V and
So
Because the operating voltage Vdd of the second phase inverter is 1V, rated insulation voltage is the conduction threshold of 3.3V nmos pass transistor
About 0.7V, in order to ensure the second phase inverter normal work, pass through design, the input logic high level of the second phase inverter of setting
Turn threshold is about 0.8V, then VIO1(high)>=1V ＞ Vth,high=0.8V, therefore when input/output port 5V_IO high level
When voltage range is more than or equal to 1.5V and is less than or equal to 5V, input of the high level more than the second phase inverter of the first input signal is patrolled
High level upset threshold is collected, the output of the second phase inverter is logical zero, so as to which MOS transistor is not damaged in imput output circuit is ensured
Bad while, being capable of normal work.
Referring to Fig. 5, as another embodiment of the present invention, as the operating voltage V of the second phase inverter in input circuitddFor 1V
When, i.e., it is V that input signal, which needs to give supply voltage,ddSystem processing when, the second phase inverter include can bear about 1V electricity
The CMOS transistor of pressure.VddIt is equal to 1V or so power supply for rated voltage, now VCCIt is equal to 3.3V power supply for rated voltage.
(1) V is worked asCCWhen effective, input/output port 5V_IO is connected to 5V power supplys by pull-up resistor, passes through design first
Resistance R0, second resistance R1 and 3rd resistor R2 ratio, it is possible to achieve following relation：
Wherein, VIO1(high)For magnitudes of voltage of the first input signal end IO1 when signal is high level, V5V_IO(high)To be defeated
Enter magnitudes of voltage of the output port 5V_IO when signal is high level.So acted on just by the partial pressure of series resistance division module
It is V that supply voltage, which can be ensured,ddInput circuit in MOS transistor be not damaged by, and realize the input of logical signal.
By adjusting first resistor R0, second resistance R1 and 3rd resistor R2 ratio, following relation can also be realized：
Wherein, VIO2(high)For magnitudes of voltage of the second input signal end IO2 when signal is high level, V5V-IO(high)To be defeated
Enter magnitudes of voltage of the output port 5V_IO when signal is high level.So can by adjusting (R0+R1) and R2 ratio
VIO2(high)Compare VCCLow the first transistor PMOS0 threshold value or bigger voltage, so when input/output port 5V_IO is deposited
In 5V signal swing, the first transistor PMOS0 conductings, VbulkEqual to VCC, so as to the 4th transistor NMOS1 grid electricity
Pressure is equal to VCC, and then ensure the 4th transistor NMOS1 normal works, and then ensure that the metal-oxide-semiconductor in output circuit is not damaged by.
(2) V is worked asCCWhen invalid, input/output port 5V_IO is connected to 5V power supplys by pull-up resistor, now, defeated when inputting
When exit port 5V_IO is essentially pulled up to 5V, series resistance division module causes biasing to produce signal end voltage Vbulk, first input letter
Number end IO1 and the second input signal end IO2 voltage return to VCCWhen effective, V5V-IO(high)Situation during=5V, so as to protect
Having demonstrate,proved MOS transistor in imput output circuit will not be damaged.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more specific and detailed, but simultaneously
Therefore the limitation to the scope of the claims of the present invention can not be interpreted as.It should be pointed out that for one of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the guarantor of the present invention
Protect scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of imput output circuit device, it is characterised in that including input circuit, biasing circuit and output circuit：
The input circuit electrically connects with the biasing circuit, for connecting the first input signal and input signal；
The biasing circuit electrically connects with input/output port and the input circuit, and exports the first input signal and biasing production
Raw signal；
The output circuit electrically connects with input/output port and the biasing circuit, for Rreceive output signal and the biasing
Produce signal；
The biasing circuit includes series resistance division module, electric capacity keeps voltage module and control module；
The series resistance division module respectively with the input/output port, the input circuit the first input signal end,
Second input signal end of the control module and the electrical connection of the 3rd input signal end, for the voltage according to input/output port
Adjust the operating voltage at the first input signal end and the second input signal end；
The control module produces signal end with the second input signal end, biasing and supply voltage electrically connects, for basis
The voltage signal control biasing at the second input signal end produces the operating voltage of signal end；
The electric capacity keeps voltage module to be series at the biasing of the control module and produces signal end and earth terminal, for keeping
State the operating voltage that biasing produces signal end；
The 3rd input signal end electrically connects with earth terminal；
The biasing circuit also includes mode selection module, the mode selection module be series at the 3rd input signal end and
Between earth terminal, and receive the biasing and produce signal and output mode selection signal.
2. imput output circuit device according to claim 1, it is characterised in that：
The mode selection module includes the 3rd phase inverter and the 5th transistor, the grid and the described 3rd of the 5th transistor
The output end connection of phase inverter；
Substrate, source electrode and the earth terminal of 5th transistor connect, the drain electrode of the 5th transistor and the described 3rd input
Signal end electrically connects；
The operating voltage of 3rd phase inverter produces the voltage of signal end for the biasing.
3. the imput output circuit device according to any one of claim 1 to 2, it is characterised in that：
The control module includes the first transistor and second transistor, the grid of the first transistor and second crystal
The source electrode of pipe connects and is coupled to the second input signal end；
The drain electrode of the first transistor, the drain electrode of the substrate of the first transistor, the substrate of second transistor and second transistor
Connect and be coupled to the biasing and produce signal end；
The source electrode of the first transistor is connected with the grid of the second transistor and is coupled to the supply voltage.
4. imput output circuit device according to claim 3, it is characterised in that：
The electric capacity keeps voltage module to include capacitor, and described capacitor one end is connected with earth terminal, and the other end is coupled to institute
The biasing for stating control module produces signal end.
5. imput output circuit device according to claim 4, it is characterised in that：
The output circuit includes third transistor, the 4th transistor and the first phase inverter, the substrate of the third transistor,
The source electrode of three transistors, the substrate of the 4th transistor connect and are coupled to earth terminal；
The grid of the third transistor is connected with the output end of first phase inverter, the drain electrode of the third transistor and institute
The source electrode for stating the 4th transistor is connected；
The drain electrode of 4th transistor is connected with the input/output port；
The grid voltage of 4th transistor produces signal end voltage for the biasing.
6. imput output circuit device according to claim 5, it is characterised in that：
The series resistance division module includes first resistor, second resistance and 3rd resistor, and the second resistance is series at institute
State between first resistor and the 3rd resistor, the other end of the first resistor is connected with earth terminal, the 3rd resistor
The other end electrically connects with the input/output port；
The connection end of the first resistor and the second resistance is coupled to the second input signal end of the control module；
The connection end of the second resistance and the 3rd resistor is coupled to the first input signal end of the input circuit.
7. imput output circuit device according to claim 5, it is characterised in that：
The series resistance division module includes first resistor, second resistance and 3rd resistor, and the second resistance is series at institute
State between first resistor and the 3rd resistor, the other end of the first resistor is connected with earth terminal, the 3rd resistor
The other end electrically connects with the input/output port；
The connection end of the first resistor and the second resistance is coupled to the first input signal end of the input circuit；
The connection end of the second resistance and the 3rd resistor is coupled to the second input signal end of the control module.
8. imput output circuit device according to claim 6, it is characterised in that：
The input circuit includes the second phase inverter, and second inverter input is coupled to the first input signal end,
Second inverter output couples with input signal；
The operating voltage of second phase inverter is 3.3V or 1V；
Second phase inverter includes PMOS, the nmos pass transistor that rated insulation voltage is 3.3V.
9. imput output circuit device according to claim 7, it is characterised in that：
The input circuit includes the second phase inverter, and second inverter input is coupled to the first input signal end,
Second inverter output couples with input signal；
The operating voltage of second phase inverter is 1V；
Second phase inverter includes PMOS, the nmos pass transistor that rated insulation voltage is 1V.
10. imput output circuit device according to claim 8 or claim 9, it is characterised in that：
The first transistor and second transistor are enhanced PMOS；
The third transistor, the 4th transistor and the 5th transistor are enhanced NMOS tube；
First phase inverter and the 3rd phase inverter include PMOS, the nmos pass transistor that rated insulation voltage is 3.3V.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310415468.2A CN104467799B (en) | 2013-09-12 | 2013-09-12 | Imput output circuit device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310415468.2A CN104467799B (en) | 2013-09-12 | 2013-09-12 | Imput output circuit device |
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| CN104467799A CN104467799A (en) | 2015-03-25 |
| CN104467799B true CN104467799B (en) | 2017-11-24 |
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| CN108322208B (en) * | 2017-01-17 | 2023-03-24 | 上海贝岭股份有限公司 | Signal interface for inputting positive and negative voltage signals and signal interface circuit thereof |
| CN113468089B (en) * | 2021-09-03 | 2021-11-30 | 上海类比半导体技术有限公司 | Output driving circuit and GPIO circuit |
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|---|---|---|---|---|
| CN1780148A (en) * | 2004-11-25 | 2006-05-31 | 冲电气工业株式会社 | Input/output circuit and semiconductor input/output device |
| CN101552605A (en) * | 2009-05-19 | 2009-10-07 | 北京时代民芯科技有限公司 | An interface circuit capable of tolerating high voltage input |
| CN101741373A (en) * | 2008-11-05 | 2010-06-16 | 中兴通讯股份有限公司 | Low voltage differential signal driver adaptive to various IO power supplies |
| US8030964B1 (en) * | 2008-05-15 | 2011-10-04 | Altera Corporation | Techniques for level shifting signals |
| CN103051325A (en) * | 2012-12-10 | 2013-04-17 | 珠海全志科技股份有限公司 | Pull-up resistance circuit for preventing reverse current filling |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1780148A (en) * | 2004-11-25 | 2006-05-31 | 冲电气工业株式会社 | Input/output circuit and semiconductor input/output device |
| US8030964B1 (en) * | 2008-05-15 | 2011-10-04 | Altera Corporation | Techniques for level shifting signals |
| CN101741373A (en) * | 2008-11-05 | 2010-06-16 | 中兴通讯股份有限公司 | Low voltage differential signal driver adaptive to various IO power supplies |
| CN101552605A (en) * | 2009-05-19 | 2009-10-07 | 北京时代民芯科技有限公司 | An interface circuit capable of tolerating high voltage input |
| CN103051325A (en) * | 2012-12-10 | 2013-04-17 | 珠海全志科技股份有限公司 | Pull-up resistance circuit for preventing reverse current filling |
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