CN113468089B - Output driving circuit and GPIO circuit - Google Patents
Output driving circuit and GPIO circuit Download PDFInfo
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- CN113468089B CN113468089B CN202111028874.4A CN202111028874A CN113468089B CN 113468089 B CN113468089 B CN 113468089B CN 202111028874 A CN202111028874 A CN 202111028874A CN 113468089 B CN113468089 B CN 113468089B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
Abstract
The application relates to the technical field of integrated circuits, and discloses an output driving circuit and a GPIO circuit. An output drive circuit comprising: the first control switch, the second control switch, first to third PMOS transistor, first control switch and second control switch connect gradually, and the second control switch includes the fourth PMOS transistor. The grid electrode of the first PMOS transistor, the grid electrode of the second PMOS transistor, the drain electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected, the source electrode of the first PMOS transistor and the substrate are connected, the source electrode of the second PMOS transistor and the substrate are connected, the drain electrode of the first PMOS transistor is connected with an internal voltage source, the drain electrode of the second PMOS transistor is connected with a driving output end, and the parasitic diode of the first PMOS transistor and the parasitic diode of the second PMOS transistor are opposite in polarity. In the embodiment of the application, the actual open-drain function and the full-function GPIO are realized, and meanwhile, the lowest working voltage range in which the GPIO can work is not influenced.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an output driving circuit and a GPIO circuit.
Background
A General-purpose input/output (GPIO) circuit is a functional block often used in a chip, and can implement functions such as digital input, digital output, and analog input through a configuration register, as shown in fig. 1, which is a typical block diagram of a GPIO block. The supply voltage of the GPIO block in fig. 1 is VDD, and when the VDD voltage is low (e.g., 1.8V), if an analog signal (e.g., 5V) with a voltage greater than VDD is required to be input, the analog input signal is clamped to VDD by a parasitic diode (body diode) of a PMOS transistor in the output driver, thereby limiting the maximum voltage amplitude of the analog input signal.
In the general MCU/DSP or GPIO design, the problem that the real Open Drain (True Open Drain) function and the GPIO fully compatible multiplexing function are not solved at present is to be realized. The existing MCU/DSP and integrated circuit with GPIO function do not realize the complete compatibility of True Open Drain and GPIO. For this reason, there are three conventional solutions:
the existing scheme 1: as shown in fig. 2, it is assumed that only the PMOS transistor is turned off when the output driver is configured to be open-drain. The scheme has the defects that the external pull-up voltage is higher than the voltage of the driving chip, and the IIC protocol is not compatible.
Existing scheme 2: as shown in fig. 3, the PMOS transistor is removed from the output driver, and only the NMOS transistor is left, thereby realizing true open-drain. The scheme can not realize the function of GPIO to output high level 1, and limits the universality of MCU/DSP.
Existing scheme 3: as shown in fig. 4, the N-well potential of the PMOS transistor in the digital output driver of the GPIO is switched to the highest power supply voltage of the chip by the well switching circuit, so that the voltage limiting point for the analog maximum input amplitude is increased, but the lowest operating voltage range in which the GPIO can operate is affected.
Disclosure of Invention
The purpose of the embodiments of the present specification is to provide an output driving circuit, which can solve the problem that the maximum amplitude of a multiplexed analog input signal in a GPIO circuit is limited by the voltage of a GPIO power supply, and the problem that an output signal pulled up to an external power supply during open-drain output is also limited by the voltage of the GPIO power supply.
An embodiment of the present application provides an output driving circuit, including: the first control switch is sequentially connected with the second control switch, and the second control switch comprises a fourth PMOS transistor; wherein the content of the first and second substances,
the grid electrode of the first PMOS transistor, the grid electrode of the second PMOS transistor, the drain electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected, the source electrode of the first PMOS transistor is connected with the substrate, the source electrode of the second PMOS transistor is connected with the substrate, and the substrate of the fourth PMOS transistor is connected, the drain electrode of the first PMOS transistor is connected with an internal voltage source, the drain electrode of the second PMOS transistor is connected with a driving output end, and the parasitic diode of the first PMOS transistor and the parasitic diode of the second PMOS transistor are opposite in polarity.
In a preferred embodiment, the output driver circuit further includes: and the source electrode of the first NMOS transistor is connected with the ground end, the drain electrode of the first NMOS transistor is connected with the driving output end, and the grid electrode of the first NMOS transistor is connected with the output end of the first phase inverter.
In a preferred embodiment, the second control switch further includes: a second NMOS transistor, wherein a source of the second NMOS transistor is connected to a source of the fourth PMOS transistor, a drain of the second NMOS transistor is connected to a drain of the fourth PMOS transistor, and an anode of a parasitic diode of the fourth PMOS transistor is connected to the drain and a cathode is connected to the source.
In a preferred embodiment, the first control switch includes: the source electrode of the fifth PMOS transistor and the source electrode of the third NMOS transistor are connected with the drain electrode of the fourth PMOS transistor, the drain electrode of the fifth PMOS transistor and the drain electrode of the third NMOS transistor are connected with the output end of the second inverter, and the substrate of the fifth PMOS transistor is connected with the internal voltage source.
In a preferred embodiment, the first control switch and the second control switch are switched simultaneously, and when the first control switch and the second control switch are switched on, the third PMOS transistor is switched off; when the first control switch and the second control switch are turned off, the third PMOS transistor is turned on.
In a preferred embodiment, the voltage domain of the internal voltage source is 1.8V, and the voltage domain of the driving output terminal is 1.8V, 3.3V or 5V.
An embodiment of the present application provides a GPIO circuit, including:
an input/output pin for connecting an external device;
an input driving circuit connected to the input/output pin and used for inputting an analog function signal or a multiplexing function signal to the external device;
in the output driving circuit, a driving output end of the output driving circuit is connected to the input/output pin and receives a data signal or a multiplexing function signal output by the external device.
In a preferred embodiment, the input driving circuit includes a TTL schottky trigger, a first resistor, a second resistor, a first switch, and a second switch, an input terminal of the TTL schottky trigger is connected to the input/output pin, one end of the first resistor is connected to a voltage source through the first switch, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is connected to a ground terminal through the second switch.
In a preferred embodiment, the method further comprises the following steps: the input data register is connected with the output end of the input driving circuit, and the output data register is connected with the input end of the output driving circuit.
In a preferred embodiment, the method further comprises the following steps: and the anode of one diode is connected with the input/output pin, the cathode of the other diode is connected with a voltage source, and the cathode of the other diode is connected with the ground end and the input/output pin.
Compared with the prior art, the embodiment of the application has at least the following differences and effects:
compared with the prior art, the scheme realizes the real open-drain function and the full-function GPIO, and simultaneously does not influence the minimum working voltage range in which the GPIO can work.
The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which are considered to have been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.
Drawings
Fig. 1 is a schematic diagram of a prior art GPIO circuit design.
Fig. 2 is a schematic diagram of an output drive circuit of conventional technical solution 1.
Fig. 3 is a schematic diagram of an output drive circuit of conventional technical solution 2.
Fig. 4 is a schematic diagram of an output drive circuit of conventional technical solution 3.
FIG. 5 is a schematic diagram of an output driver circuit according to an embodiment of the present application.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
In one embodiment of the present application, an output driving circuit is provided, and fig. 5 shows a schematic diagram of the output driving circuit in one embodiment, where the output driving circuit includes: a first control switch S1, a second control switch S2, first to third PMOS transistors P1, P2, P3. The first control switch S1 is connected to the second control switch S2, and the second control switch S2 includes a fourth PMOS transistor P4 and a second NMOS transistor N2.
The gate of the first PMOS transistor P1, the gate of the second PMOS transistor P2, the drain of the third PMOS transistor P3, and the source of the fourth PMOS transistor P4 are connected. The source and the substrate of the first PMOS transistor P1, the source and the substrate of the second PMOS transistor P2, and the substrate of the fourth PMOS transistor P4 are connected. The drain of the first PMOS transistor P1 is connected to an internal voltage source (i.e., a voltage source internal to GPIO) VIO. The drain of the second PMOS transistor P2 is connected to the driving output terminal DOUT. The driving output terminal DOUT is connected to an input/output pin, i.e. connected to an external device through the input/output pin. The first PMOS transistor P1 includes a parasitic diode D1 pointing from its drain to source, and similarly, the second PMOS transistor P2 includes a parasitic diode D2 pointing from its drain to source. It can be seen that the parasitic diodes D1 and D2 are of opposite polarity.
The output driver circuit further includes a first NMOS transistor N1. The source of the first NMOS transistor N1 is connected to the ground GND, the drain of the first NMOS transistor N1 is connected to the driving output terminal DOUT, and the gate of the first NMOS transistor N1 is connected to the output terminal of the first inverter INV 1.
In the second control switch S2, the source of the second NMOS transistor N2 is connected to the source of the fourth PMOS transistor P4, the drain is connected to the drain of the fourth PMOS transistor P4, and the fourth PMOS transistor P4 includes a parasitic diode D4 pointing from the drain to the source, the anode of the parasitic diode D4 is the drain, and the cathode is the source.
The first control switch S1 includes: a fifth PMOS transistor P5 and a third NMOS transistor N3. The source of the fifth PMOS transistor P5 and the source of the third NMOS transistor N3 are connected to the drain of the fourth PMOS transistor P4, the drain of the fifth PMOS transistor P5 and the drain of the third NMOS transistor N3 are connected to the output terminal of the second inverter INV2, and the substrate of the fifth PMOS transistor P5 is connected to the internal voltage source VIO.
In the present application, the first control switch S1 and the second control switch S2 are switched on and off simultaneously, i.e., turned on and off simultaneously. The third PMOS transistor P3 is turned off when the first and second control switches S1 and S2 are turned on, and the third PMOS transistor P3 is turned on when the first and second control switches S1 and S2 are turned off.
In one embodiment, the voltage domain of the internal voltage source VIO is 1.8V, and the voltage domain of the driving output terminal DOUT is 1.8V, 3.3V or 5V. It should be appreciated that the voltage source driving the output terminal DOUT may be higher than the voltage domain of the internal voltage source.
In this application, two transmission gate control switches S1, S2 are inserted in series in the path of the gate control signal of the conventional PMOS transistor. Both control switches S1, S2 are closed when GPIO is multiplexed into an analog input signal or when GPIO is configured as an Open Drain output. Control switch S1 is of GPIO voltage domain, i.e., VIO voltage domain (e.g., 1.8V), and control switch S2 is of the highest power supply voltage domain internal to the peripheral chip, i.e., DOUT voltage domain (e.g., 3,3V, or 5V). When the control switches S1 and S2 are turned off, the gates pgate of the first PMOS transistor P1 and the second PMOS transistor P2 are in a floating state, and the gate potentials of the first PMOS transistor P1 and the second PMOS transistor P2 are made equal to the N-well potential VNW of the first PMOS transistor P1 and the second PMOS transistor P2 by controlling the third PMOS transistor P3 to be turned on. Due to the opposite polarity of the parasitic diodes of the first PMOS transistor P1 and the second PMOS transistor P2, the voltage amplitude is prevented from being clamped by the GPIO supply voltage when GPIO is multiplexed into an external analog input signal or when GPIO is configured as an Open Drain output.
Another embodiment of the present application further provides a GPIO circuit, as shown in fig. 1 and 5, the GPIO circuit includes: an input/output pin (I/O), an input drive circuit, an output control, an output drive circuit, an input data register, and an output data register. The input/output pins are used to connect external devices (e.g., on-chip peripherals).
The input driving circuit is connected with the input/output pin and used for inputting an analog function signal or a multiplexing function signal to the external device, and comprises a TTL Schottky trigger, a first resistor R1, a second resistor R2, a first switch S and a second switch S ', wherein the input end of the TTL Schottky trigger is connected with the input/output pin, one end of the first resistor R1 is connected with a voltage source VDD through the first switch S, the other end of the first resistor R1 is connected with one end of the second resistor R2, and the other end of the second resistor R2 is connected with a ground terminal VSS through the second switch S'. The node between the resistor R1 and the resistor R2 provides analog input to the on-chip peripherals, and the TTL Schottky flip-flop provides multiplexing function input to the on-chip peripherals. The input data register is connected with the output end of the input driving circuit, such as the output end of the Schottky trigger, and is used for storing data read by the Schottky trigger.
The output driving circuit shown in fig. 5 is used as the output driving circuit, the input of the output driving circuit is connected to the output control, and the driving output end of the output driving circuit is connected to the input/output pin and receives the data signal or the multiplexing function signal output from the external device. The output data register is connected with the input end of the output driving circuit. The GPIO circuit further comprises a bit set/clear register connected to the output data register for storing the written data. The output data register and the output signal of the multiplexing function from the on-chip peripheral are connected with the output control through the multiplexer.
The GPIO circuit also comprises two diodes, wherein the anode of one diode is connected with the input/output pin, the cathode of the diode is connected with a voltage source VDD, the anode of the other diode is connected with a ground terminal VSS, and the cathode of the diode is connected with the input/output pin. The diode is used to prevent the voltage on the input/output pin from being too high.
The scheme realizes the True Open Drain function and the full-function GPIO, and meanwhile, the lowest working voltage range in which the GPIO can work is not influenced.
It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.
The term "coupled to" and its derivatives may be used herein. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but yet still co-operate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled to each other.
This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "a preferred embodiment") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive, unless indicated as mutually exclusive or as would be apparent to one of ordinary skill in the art. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly dictates otherwise.
All documents mentioned in this specification are to be considered as being incorporated in their entirety into the disclosure of the present application so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.
Claims (7)
1. An output driving circuit, comprising: the first control switch is sequentially connected with the second control switch, and the second control switch comprises a fourth PMOS transistor; wherein the content of the first and second substances,
the grid electrode of the first PMOS transistor, the grid electrode of the second PMOS transistor, the drain electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected, the source electrode of the first PMOS transistor and the substrate, the source electrode of the second PMOS transistor and the substrate of the fourth PMOS transistor are connected, the drain electrode of the first PMOS transistor is connected with an internal voltage source, the drain electrode of the second PMOS transistor is connected with a driving output end, and the parasitic diode of the first PMOS transistor and the parasitic diode of the second PMOS transistor are opposite in polarity;
the second control switch further comprises: a second NMOS transistor, wherein a source of the second NMOS transistor is connected to a source of the fourth PMOS transistor, a drain of the second NMOS transistor is connected to a drain of the fourth PMOS transistor, and an anode of a parasitic diode of the fourth PMOS transistor is connected to the drain and a cathode is connected to the source;
the first control switch includes: a fifth PMOS transistor and a third NMOS transistor, wherein a source of the fifth PMOS transistor and a source of the third NMOS transistor are connected to a drain of the fourth PMOS transistor, a drain of the fifth PMOS transistor and a drain of the third NMOS transistor are connected to an output terminal of a second inverter, and a substrate of the fifth PMOS transistor is connected to the internal voltage source;
the first control switch and the second control switch are switched simultaneously, and when the first control switch and the second control switch are switched on, the third PMOS transistor is switched off; when the first control switch and the second control switch are turned off, the third PMOS transistor is turned on.
2. The output driver circuit according to claim 1, further comprising: and the source electrode of the first NMOS transistor is connected with the ground end, the drain electrode of the first NMOS transistor is connected with the driving output end, and the grid electrode of the first NMOS transistor is connected with the output end of the first phase inverter.
3. The output driving circuit of claim 1, wherein the voltage domain of the internal voltage source is 1.8V, and the voltage domain of the driving output terminal is 1.8V, 3.3V, or 5V.
4. A GPIO circuit, comprising:
an input/output pin for connecting an external device;
an input driving circuit connected to the input/output pin and used for inputting an analog function signal or a multiplexing function signal to the external device;
the output driver circuit according to any of claims 1 to 3, wherein a driving output terminal of the output driver circuit is connected to the input/output pin and receives a data signal or a multiplexing function signal output from the external device.
5. The GPIO circuit of claim 4, wherein the input driver circuit comprises a TTL Schottky flip-flop, a first resistor, a second resistor, a first switch and a second switch, wherein an input terminal of the TTL Schottky flip-flop is connected to the input/output pin, one end of the first resistor is connected to a voltage source via the first switch, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is connected to ground via the second switch.
6. The GPIO circuit of claim 4, further comprising: the input data register is connected with the output end of the input driving circuit, and the output data register is connected with the input end of the output driving circuit.
7. The GPIO circuit of claim 4, further comprising: and the anode of one diode is connected with the input/output pin, the cathode of the other diode is connected with a voltage source, and the cathode of the other diode is connected with the ground end and the input/output pin.
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| CN114884487B (en) * | 2022-03-22 | 2024-01-05 | 上海类比半导体技术有限公司 | Circuit for controlling slew rate, I2C bus system and control method thereof |
| CN114900180B (en) * | 2022-05-25 | 2023-09-26 | 苏州华太电子技术股份有限公司 | GPIO circuit, chip and electronic equipment |
| CN114978150A (en) * | 2022-05-25 | 2022-08-30 | 苏州华太电子技术有限公司 | Output driving circuit, GPIO circuit, chip and electronic equipment |
| CN114895738B (en) * | 2022-05-25 | 2023-09-26 | 苏州华太电子技术股份有限公司 | Fail-safe control voltage generating circuit and anti-backflow circuit |
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