1290795 九、發明說明： 【發明所屬之技術領域】 且特別是有關於一種 本發明是有關於一種積體電路 具閘極氧化層保護之輸入/輪出電路 【先前技術】 為了省電，裝置的核心電路如微處理器，通常操作在 一預定的較低之電壓位準，即使此裝 溝^ =使用比裝置的如電路所用的預定更高之輪入/ =(1/0)霞位準。舉例來說，微處理器晶片可能操作在 具有3.3伏特(V)電壓位準的高(H)邏輯位準以及具有〇 V 電壓位準的低(L)邏触準，雖賴置可能祕至5 v電源 執(power rail)以供外部溝通使用。一般而言，在這樣的裝、 置裡，位準偏移器(level shifter)將微處理器晶片所使用的^ V和3.3 V _電壓位準轉換成G v和5 v的輸出電壓位 準^但是，在輸出電晶體之閘極與汲極/源極之間的5 V之 電壓差可財、容祕破制極氧化層(_ Gxide)而使裝置 失效。隨著技術的進步，這些電壓位準將會降低。 圖1繪不為傳統的輸出電路之電路圖，其中輸出電路 使用上述之電壓系統。如圖i所示，傳統的輸出緩衝器100 包括P型金氧半(PM0S)電晶體130和N型金氧半(NM〇s) 電曰曰體140串聯耦接，以驅動輸入/輸出電路。pmqs電晶 體130之源極耦接至5 v的外部電源供應端15〇，而NM〇s 電曰a體140之源極|馬接至〇 v的外部接地電壓“ο。pMQs 電晶體130和NM0S電晶體140之汲極皆耦接至輸出節點 1290795 120以傳送輸出信號。PMOS電晶體130之閘極耦接至第 一輸入節點110以接收第一輸入信號。NMOS電晶體140 之閘極耦接至第二輸入節點115以接收第二輸入信號。當 苐一輸入k號和第二輸入信號皆為0 V(邏輯低)時，pm〇s 電晶體130打開而NM0S電晶體H〇關閉。輸出緩衝器 1〇〇輸出5 V(邏輯高）的信號。在PM〇S電晶體130之閘極 與汲極/源極之間的電壓差為5V。當第一輸入信號和第二1290795 IX. Description of the invention: [Technical field to which the invention pertains] and particularly relates to an input/round circuit for protecting an integrated circuit with a gate oxide layer [Prior Art] In order to save power, the device A core circuit, such as a microprocessor, typically operates at a predetermined lower voltage level, even if the trenching is using a predetermined higher turn-in /=(1/0) Xia level than the device used in the circuit. . For example, a microprocessor die may operate at a high (H) logic level with a 3.3 volt (V) voltage level and a low (L) logic level with a 〇V voltage level, although it may be 5 v Power rail for external communication. In general, in such a device, a level shifter converts the V and 3.3 V _ voltage levels used by the microprocessor chip to the output voltage levels of G v and 5 v. ^ However, the voltage difference of 5 V between the gate of the output transistor and the drain/source can make the device ineffective by breaking the electrode oxide layer (_Gxide). As technology advances, these voltage levels will decrease. Figure 1 depicts a circuit diagram of a conventional output circuit in which the output circuit uses the voltage system described above. As shown in FIG. 1, a conventional output buffer 100 includes a P-type MOS transistor 130 and an N-type NMOS transistor 140 coupled in series to drive an input/output circuit. . The source of the pmqs transistor 130 is coupled to the external power supply terminal 15〇 of the 5v, and the source of the NM〇s electrical body a body 140 is connected to the external ground voltage of the 〇v “ο. pMQs transistor 130 and The drains of the NM0S transistor 140 are coupled to the output node 1290795 120 to transmit an output signal. The gate of the PMOS transistor 130 is coupled to the first input node 110 to receive the first input signal. The gate coupling of the NMOS transistor 140 The second input signal is received by the second input node 115. When both the input k number and the second input signal are 0 V (logic low), the pm〇s transistor 130 is turned on and the NM0S transistor H is turned off. The output buffer 1〇〇 outputs a signal of 5 V (logic high). The voltage difference between the gate and the drain/source of the PM〇S transistor 130 is 5 V. When the first input signal and the second
輸入信號皆為5 V(邏輯高）時，PMOS電晶體130關閉而 NM〇S電晶體140打開。輸出緩衝器100輸出0V(邏輯低) 的k號。在NMOS電晶體140之閘極與汲極/源極之間的 電壓差為5 V。 實際上’施加於閘極氧化層的電場必須小於5 MV/em 以避免閘極氧化層崩潰。假設在目前半導體製程中閘極氧 化層為88·5埃(angstrom)，則5 v的電壓差會導致5 65 ^Vcm的電場施加於閘極氧化層，此電場超過氧化層的崩 /貝電壓，而導致破壞性的閘極氧化層崩潰。 、。:種對付這個問題的方法就是降低作為輸入信號高的 邏^之電壓，接著輸出電晶體之閘極與雜/源極之間的 電麼差會降低。使用這個較低電壓的邏輯高亦可降低輕接 ，PMOS電㈣13()之源極的外部電源供應以及认 =〇S電純⑽之閘_簡緒人信號兩者之間的、i 。從r=PM0S電晶體130完全地關閉。這樣的靜態When the input signals are all 5 V (logic high), the PMOS transistor 130 is turned off and the NM〇S transistor 140 is turned on. The output buffer 100 outputs a k number of 0V (logic low). The voltage difference between the gate and the drain/source of the NMOS transistor 140 is 5 V. In fact, the electric field applied to the gate oxide layer must be less than 5 MV/em to avoid collapse of the gate oxide layer. Assuming that the gate oxide layer is 88·5 angstroms in the current semiconductor process, a voltage difference of 5 v causes an electric field of 5 65 ^Vcm to be applied to the gate oxide layer, which exceeds the collapse/beauty voltage of the oxide layer. And cause the destructive gate oxide to collapse. ,. The way to deal with this problem is to reduce the voltage of the logic that is high as the input signal, and then the difference between the gate and the source/source of the output transistor is reduced. Using this lower voltage logic height can also reduce the light connection, the external power supply of the source of the PMOS (four) 13 () and the i 。 电 电 pure (10) gate _ simple human signal between the i. The transistor 130 is completely turned off from the r=PM0S. Such static
Hi部電源端流到外部接地表示有一固定的漏電流並 且疋不希望存在的特性。 电/爪I 7 1290795 另一種對付這個問題常用的方法就是使用「雙氧化層 (dual oxide)」過程。當I/O f路使収厚的層以操 在更高的電麼時，内部的邏輯使用更薄的氧化層以操作在 更低的電壓。不過，這獅方法將在產品t增加額外的成 本。 【發明内容】 本發明的目的就是在提供一種電路，此電路被設計成 用來保護輸入/輸出(I/O)電路，因此可以操作在相較於内部 電路較高的電壓，並且仍然使用「單—薄氧化層恤扯脇 oxide)」技術使產品保持低成本。 根據本發明一較佳實施例，具閘極氧化層保護之輸入 輸出電路包括第-輸人節點、第二輸人節點、輸出節點、 第f員型的第一輸出電晶體、第二類型的第二輸出電晶 ，、一第二類型的第—夾止(damping)電晶體以及第二類型的 一—夾止電晶體。第一夾止電晶體、第一輸出電晶體、第 =夾止電晶體以及第二輸出電晶體串聯耦接並跨接於第一 3供應端以及第二電源供應端之間。第—輸人節點輕接 :輸出電晶體之閘極。第二輸入節點耦接至第二輸出 止晶，之閘極。輸出節點耦接至第一輸出電晶體與第二夾 電日日體之共同節點(c〇mmonnode)。第一夾止電晶體之閘 亟，接至第-參考電壓。第二夾止電晶體之閘軸接至第 —參考電壓。 1290795 為讓本發明之上述和其他目的、特 易懂，下文特舉較佳實施例，並配合_ j明顯 明如下。 叮附圖式，作詳細說 【實施方式】 之電ί mrnrr供更㈣戦歧極/源極 如邮。i m ^ r電料軸氧化層(_ 電流流動之路的任何電晶體中避免持續的 較佳之化^ 第第-二=，、第-夹止(-二 弟一夾止電晶體260。p型雷曰d 電晶體可提供為輸出電路中的第一或第_ ^曰;^體曰^ N型 =-類型或另—類型能夠類：晶= 電曰曰！-笛rf +輸出電晶體250為第一類型 電晶體270、第一夹止電晶體綱以及 24「t St260為第二類型電晶體。第-夾止電晶體 =、弟:輸出電晶體25〇、第二炎止電晶體以及第二 :第：串聯耦接並跨接於第-電源供應端290以 間广輸·2_至第 ，二電晶體謂之間極。輪出節點 ； a曰體250與第二夹止電晶體之共同節點(_L! 9 J290795 曰體240之間_接至第一參考祕節 並從第一參考電壓節點280接收第一參考電壓 REF1帛—夾正電晶體細之閘極搞接至 :請，並從第二參考電壓節點285接收第二參= 第輸出電晶體250與第一夾止電晶體24〇之共同節 ^即一A點，其龍(Va)保持大約少於第—參考電壓&翻） 二I “止電曰曰體240之臨界電壓(threshold voltage)(VTHi) 老^間的電壓差。那即是說，W-vTH1。第-參 考電難佳地低於第i源供應端29G的電壓，以保持第 夾止電晶體240在打開的狀態。a點的電壓低於第一參 =壓，接著第一參考電壓較佳地低於第一電源供應端的 屏f。因此，施加於第一輸出電晶體25〇之閘極氧化層的 最咼電壓差會降低。 同f地，第二輸出電晶體270與第二夾止電晶體260 同節點’即B黑占，其電壓(Vb)保持大約少於第二參考 電[(VREF2)與第一夾止電晶體26〇之臨界電壓(Vth2)兩者 ，間的電壓差。那就是說，MV, — %。在一較佳實 域中，第二參考電壓低於可以祕至輸出節點230之外 部電路的最大電壓。外部電路的最大電壓通#第一電源 供應端290的電壓相同。於是，B點的電壓較佳地低於第 一夾止電晶體260可以從輸出節點23〇接收的最高電壓。 因此，施加於第二輸出電晶體27〇之閘極氧化層的電壓差 會降低。 1290795 在一較佳實施例中，第一輸出電晶體25〇為PM〇s電 晶體(pi) ’而第一夾止電晶體240、第二夾止電晶體26〇 以及第二輸出電晶體270為NMOS電晶體(分別為N2 ，N3)第電源供應端290的電壓大約為5伏特(ν)，而 第二電源供應端295的電壓大約為〇 ν，即接地電麼。第 :參考電壓大約為4.5 V，而第二參考電壓大約為3 3 ν。 =第-輸入節點21〇和第二輸入節點22〇 電壓分別大約為4.2 V和〇 ν。 ^ G·3 V °因此’ Α點的電壓保 B點的保牲· I而實貝上與邏輯高輸入的電壓相同。 ”、、的電I保持不超過大約3.0 V。 當輸入信號在邏輯高時，篦一於# 人節請輕接至大約4 2\第=即點210和第二輸 b V ° 口為A點的雷懕膏曾卜保 持一邏輯高輸入信號的電壓相 d ，、 源_接至大約4.2V。因此，门第二=出電晶體P1之 因為第二輸出電日# 、第—輸出電晶體P1關閉。 xn 日日體3之源極接地，且第-給出雷曰@ N3之閘_接至大約4.2 v 第一輸出電曰曰體 打開。所U口此弟二輸出電晶體N3 出電晶二虎Λ電屢大約為0 V’施加於第二輸 ^之閘極乳化層的電壓差大約為42V。 虽輪入信號在邏輯低時，第一輪 . 人節點22。_至大㈣v。“ 210和第二輪 與邏輯高輸入信號的電壓相同口 = J壓實質上保持 極輪接至大約4.2 V。因此门第，電晶體P1之源 為第二輸_心接地以 1290795 Μ錢糊蝴4.2 V，施加於 因為笛Γ+_之開極氧化層的電壓差大約為4.2V。 -輸出JC電晶體Νι和第—參考電壓之值，在第 且當輪出:接Λ之閉極氧化層上的受壓(stress)會降低，而 層=崩;接至=，壓時，電晶體ρι之閉極氣： 於閉極氧化’為了避免閑極氧化層崩潰，施加 _妒Γ層電須小於5 Mv/em。麟在目前半導 導閘極氧化層厚度為队5埃，則4.2V的電壓差會 • MV/cm的電場施加於閘極氧化層，此電場通^ 太低以致於無法引起氧化層崩潰。 當，出節點230搞接至5 v時，第二夾止電晶體w ，弟二參考電壓保持B點的電壓低於大約3 v。因此，在 第-輸出電晶體N3之閘極氧化層上的受壓會降低，以避 =在電晶體N3耦接至高外部電_，閘極氧化層產生崩 潰。3 V的電壓差會產生3·39 Mv/cm的電場施加於閘極氧 化層，此電場通常太低而無法導致氧化層崩潰。 在一實施例中，第一輸出電晶體25〇、第二輸出電晶 體270、第一夾止電晶體240以及第二夾止電晶體26〇之 基底(substrate)麵接至它們各自的預定電壓。pm〇s電晶體 之基底的預定電壓為第一電源供應端290的電壓，而 NMOS電晶體之基底的預定電壓為第二電源供應端295的 電壓。The flow of the Hi portion of the power supply to the external ground indicates a fixed leakage current and an undesirable characteristic. Electric / Claw I 7 1290795 Another common method to deal with this problem is to use the "dual oxide" process. When the I/O f path allows the thicker layer to operate at a higher power, the internal logic uses a thinner oxide layer to operate at a lower voltage. However, this lion method will add extra cost to the product t. SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit designed to protect an input/output (I/O) circuit so that it can operate at a higher voltage than the internal circuit and still use " The technology of "single-thin oxide layer" is to keep products at a low cost. According to a preferred embodiment of the present invention, the input and output circuit with gate oxide protection includes a first-input node, a second input node, an output node, a first output transistor of the f-type, and a second type A second output transistor, a second type of first-staging transistor, and a second type of one-clamping transistor. The first clamping transistor, the first output transistor, the thyristor transistor, and the second output transistor are coupled in series and connected between the first 3 supply terminal and the second power supply terminal. The first-input node is lightly connected: the gate of the output transistor. The second input node is coupled to the second output stop, the gate. The output node is coupled to a common node (c〇mmonnode) of the first output transistor and the second charging cell. The first clamp transistor is connected to the first reference voltage. The gate of the second clamping transistor is connected to the first reference voltage. The above and other objects and advantages of the invention will be apparent from the following description.叮 叮 , 作 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 四 四 四 四 四Im ^ r electric energy axis oxide layer ( _ current flow path in any transistor to avoid continuous improvement ^ first - two =, first - pinch - - two brothers one clamping transistor 260. p type The Thunder d transistor can be provided as the first or the first _ ^ 曰 in the output circuit; ^ 曰 ^ N type = - type or another - type can be class: crystal = electric 曰曰! - flute rf + output transistor 250 The first type of transistor 270, the first type of clamping transistor, and 24"t St260 are the second type of transistor. The first-clamping transistor =, the brother: the output transistor 25", the second transistor, and the transistor Second: the first series is coupled and connected across the first power supply terminal 290 to transmit the second to the second, and the second transistor is said to be between the poles; the wheel outlet node; a body 250 and the second pinch battery The common node of the crystal (_L! 9 J290795 between the bodies 240 is connected to the first reference junction and receives the first reference voltage REF1 from the first reference voltage node 280 - the gate of the positive crystal is connected to: And receiving, from the second reference voltage node 285, the common node of the second reference output transistor 250 and the first pinch transistor 24, ie, an A point, the dragon (Va) remains less The first - reference voltage & turn) II I "Threshold voltage of the power-off body 240 (VTHi) The voltage difference between the old ^. That is to say, W-vTH1. The first - reference power is difficult Lower than the voltage of the i-th source supply terminal 29G to keep the first pinch transistor 240 in an open state. The voltage at point a is lower than the first reference voltage, and then the first reference voltage is preferably lower than the first power supply. The screen f of the terminal. Therefore, the final voltage difference applied to the gate oxide layer of the first output transistor 25〇 is lowered. Similarly, the second output transistor 270 and the second pinch transistor 260 are in the same node. B black, the voltage (Vb) remains less than the voltage difference between the second reference power [(VREF2) and the threshold voltage (Vth2) of the first pinch transistor 26". That is, MV, In a preferred real domain, the second reference voltage is lower than the maximum voltage of the external circuit that can be secreted to the output node 230. The maximum voltage of the external circuit is the same as the voltage of the first power supply terminal 290. Thus, B The voltage at the point is preferably lower than the highest voltage that the first pinch transistor 260 can receive from the output node 23A. Therefore, the voltage difference applied to the gate oxide layer of the second output transistor 27A is lowered. 1290795 In a preferred embodiment, the first output transistor 25A is a PM〇s transistor (pi)' A pinch transistor 240, a second pinch transistor 26A, and a second output transistor 270 are NMOS transistors (N2, N3, respectively). The voltage supply terminal 290 has a voltage of about 5 volts (v), and The voltage of the two power supply terminals 295 is approximately 〇ν, that is, the grounding voltage. The reference voltage is approximately 4.5 V and the second reference voltage is approximately 3 3 ν. The voltages of the first-input node 21A and the second input node 22〇 are approximately 4.2 V and 〇 ν, respectively. ^ G·3 V ° Therefore, the voltage at the point of protection is guaranteed at point B. I and the voltage on the solid is the same as the voltage at the logic high input. "," the electric I is kept no more than about 3.0 V. When the input signal is at logic high, please connect to the human section, please connect to approximately 4 2 \ the first = point 210 and the second input b V ° port is A The point of the Thunderbolt has maintained a logic high input signal voltage phase d, and the source_ is connected to approximately 4.2 V. Therefore, the second gate = the output transistor P1 because of the second output electricity day #, the first output power The crystal P1 is turned off. xn The source of the Japanese body 3 is grounded, and the first - gives the Thunder @ N3 gate _ is connected to about 4.2 v The first output electric 打开 body is opened. The U port is the second output transistor N3 The voltage difference between the gate and the emulsifier layer of the second transistor is about 42 V. Although the wheel signal is at logic low, the first round. The human node 22. Large (four) v. "210 and the second round of the same voltage as the logic high input signal = J pressure substantially keeps the pole to about 4.2 V. Therefore, the gate, the source of the transistor P1 is the second input _ core grounded with 1290795 4.2 糊 4.2 4.2 V, applied to the open circuit oxide due to the Γ + _ voltage difference is about 4.2V. - output the value of the JC transistor Νι and the first reference voltage, at the first and when the round: the stress on the closed oxide layer of the joint is reduced, and the layer = collapse; when connected to =, when pressed, The closed cell of the transistor ρι: in the closed-pole oxidation 'in order to avoid the collapse of the idle electrode layer, the application of _ layer of electricity must be less than 5 Mv / em. At the current semi-conductive gate oxide thickness of 5 angstroms, the voltage difference of 4.2V will apply an electric field of MV/cm to the gate oxide layer, which is too low to cause the oxide layer to collapse. When the output node 230 is connected to 5 v, the second clamping transistor w and the second reference voltage maintain the voltage at point B below about 3 v. Therefore, the voltage on the gate oxide layer of the first output transistor N3 is lowered to avoid the breakdown of the gate oxide layer when the transistor N3 is coupled to the high external power. A voltage difference of 3 V produces an electric field of 3.39 Mv/cm applied to the gate oxide layer, which is usually too low to cause the oxide layer to collapse. In one embodiment, the substrates of the first output transistor 25A, the second output transistor 270, the first pinch transistor 240, and the second pinch transistor 26 are surface-connected to their respective predetermined voltages. . The predetermined voltage of the substrate of the pm〇s transistor is the voltage of the first power supply terminal 290, and the predetermined voltage of the substrate of the NMOS transistor is the voltage of the second power supply terminal 295.
在另一實施例中，第一夾止電晶體240之基底耦接至 第一夾止電晶體240與第一輪出電晶體250之共同節點(A 1290795 • j)，而不是電晶體之基絲接至其财電壓。因此， —夾止電晶體的臨界電壓小於上述實施例中第 止，晶體24G的臨界電[結果將使A點的電壓增加，而 使得輸出信號容易被辨認出是邏輯高。 曰 一圖3A繪示為具閘極氧化層保護之輸入/輸出電路的另 =佳實施例之電關。如圖3所示，制極氧化層保護 之輸入輸出電路300包括位準偏移器31〇和内部電路 φ 34〇。内部電路340輸出信號至位準偏移器31〇，接著位準 偏移器310輸出信號至第一輸入節點21〇和第二輸入節點 220。位準偏移器31〇耦接至第三和第四電源供應端3如 和330。内部電路34〇耦接至第五和第六電源供應端 和 360 〇 ，一實施例中，由第一電源供應端所提供至輸出電路 的電壓(VDD1)較佳地大於由第三電源供應端所提供至位準 偏移器310的電壓(VdD2)，接著由第三電源供應端所提供 至位準偏移器310的電壓(Vdd2)較佳地大於由第五電源供 φ 應端所提供至内部電路340的電壓(Vcc)。第二電源供應端 (vssl)、第四電源供應端(Vss2)以及第六電源供應端(Vss2) 接地。配置第一參考電壓(VrEF1)以使A點的電壓(VA)實質 上與由第三電源供應端所提供的電壓(VDD2)相同 。例如， 第一參考電壓大約為4·5 V。由第三電源供應所提供的電壓 以及Α點的電壓(Va)兩者皆保持大約4·2 ν。因此，當輸 入信號在邏輯高時，第一輸出電晶體250能夠完全關閉。 第一參考電壓(VREF1)較佳地高於由第三電源供應端所提供 13 1290795 的電壓(vD]〇2)，並較佳地低於由第一電源供應端所提供的 電壓(vDD1)。第二參考電壓(Vref2)較佳地低於第一參考電 壓(Vrefi) ’用以限制會降低第二輸出電晶體270使用壽命 的熱載子(hot carrierS)。因為由第五電源供應端所提供的電 壓(Vcc)低於第一參考電壓(Vrefi)，第五電源供應端35()能 夠提供第二參考電壓(VREF2)。 ，如圖3B所示之另一實施例中，第三電源供應端的 電壓藉由將位準偏移器31〇之電源供應線325耦接至a點 來取得，其中A點為第一夾止電晶體240與第一輸出電晶 體250之共同節點。也就是說，供應給位準偏移器的電壓 上與A點的電壓(VA)相同。因此，當輸入信號在邏輯 同日寸，第一輸出電晶體25〇能夠完全關閉。In another embodiment, the base of the first clamping transistor 240 is coupled to the common node of the first pinch transistor 240 and the first wheel-out transistor 250 (A 1290795 • j) instead of the base of the transistor. The wire is connected to its financial voltage. Therefore, the threshold voltage of the clamping transistor is smaller than that in the above embodiment, and the critical electric current of the crystal 24G [results in increasing the voltage at point A, so that the output signal is easily recognized as being logic high. FIG. 3A illustrates the electrical switching of another preferred embodiment of the input/output circuit with gate oxide protection. As shown in Fig. 3, the gate oxide protected input and output circuit 300 includes a level shifter 31A and an internal circuit φ 34A. The internal circuit 340 outputs a signal to the level shifter 31A, and then the level shifter 310 outputs a signal to the first input node 21A and the second input node 220. The level shifter 31 is coupled to the third and fourth power supply terminals 3 such as and 330. The internal circuit 34 is coupled to the fifth and sixth power supply terminals and 360 〇. In one embodiment, the voltage (VDD1) provided by the first power supply terminal to the output circuit is preferably greater than the third power supply terminal. The voltage supplied to the level shifter 310 (VdD2), and then the voltage supplied by the third power supply terminal to the level shifter 310 (Vdd2) is preferably greater than that provided by the fifth power supply for the φ terminal The voltage to the internal circuit 340 (Vcc). The second power supply terminal (vss1), the fourth power supply terminal (Vss2), and the sixth power supply terminal (Vss2) are grounded. The first reference voltage (VrEF1) is configured such that the voltage (VA) at point A is substantially the same as the voltage (VDD2) supplied from the third power supply terminal. For example, the first reference voltage is approximately 4·5 V. Both the voltage supplied by the third power supply and the voltage (Va) of the defect are maintained at approximately 4·2 ν. Therefore, when the input signal is at logic high, the first output transistor 250 can be completely turned off. The first reference voltage (VREF1) is preferably higher than the voltage (vD] 〇 2) provided by the third power supply terminal 13 1290795, and preferably lower than the voltage supplied by the first power supply terminal (vDD1) . The second reference voltage (Vref2) is preferably lower than the first reference voltage (Vrefi)' to limit the hot carrier S that would reduce the useful life of the second output transistor 270. Since the voltage (Vcc) supplied from the fifth power supply terminal is lower than the first reference voltage (Vrefi), the fifth power supply terminal 35() can supply the second reference voltage (VREF2). In another embodiment, as shown in FIG. 3B, the voltage of the third power supply terminal is obtained by coupling the power supply line 325 of the level shifter 31 to the point a, where the point A is the first pinch. The transistor 240 is in common with the first output transistor 250. That is, the voltage supplied to the level shifter is the same as the voltage (VA) at point A. Therefore, when the input signal is at the same logic level, the first output transistor 25A can be completely turned off.
•當施加外部電源供應Μ。…一以後，在電路致動 (active)時’相關的輸人輸出電路之電源供應電壓將經過電 ，供電程序，然後保持敎。以圖3A之實施例為例，第 二電源供應端的電壓（VDm)從第一電源供應端的電壓 (Vddi)所產生。第一電源供應端的電壓(VDD1)與第三電源供 f電壓(、2)用來產生第-參考電壓(Vrefi)。當施加 電源供應時，第一電源供應端的電壓(VDD1)例如從〇 v 然後保持穩定。同時，第一電源供應端的電 1 DD1)使第三電源供應端的電壓(vDm)上升，例如從 二4·2、：’然，保持穩定。同樣地，第-電源供應端的電壓 DD1) /、第三電源供應端的電壓(VDD2)使第一參考電壓 REF1上升’例如從〇 v到4·5 V，然後保持穩定。當第一 1290795 電壓(Vrefi)到達一預定值時，輸入輸出電路從電源供 回C桑作。當電路致動時，第-參考卿一 產生第二電源供應端的電壓(vDD2)。 由莖二f 3B之實施例為例’中間電壓(intermediate voltage) ::電源供應端的電壓(Vddi)所產生。第一電源供應端 和DDI)以財間電麼用來產生第一參考電產(vREF1) 弟一參考電壓(VREF2)。• When an external power supply is applied Μ. ...afterwards, when the circuit is active, the power supply voltage of the associated input output circuit will pass through the power supply process and then remain 敎. Taking the embodiment of Fig. 3A as an example, the voltage (VDm) of the second power supply terminal is generated from the voltage (Vddi) of the first power supply terminal. The voltage of the first power supply terminal (VDD1) and the voltage of the third power supply (, 2) are used to generate a first reference voltage (Vrefi). When a power supply is applied, the voltage (VDD1) of the first power supply terminal is then stabilized, for example, from 〇v. At the same time, the electric power 1 DD1) of the first power supply terminal raises the voltage (vDm) of the third power supply terminal, for example, from the 2nd, 2nd, and 2nd, and remains stable. Similarly, the voltage of the first power supply terminal DD1) / and the voltage of the third power supply terminal (VDD2) cause the first reference voltage REF1 to rise 'for example, from 〇 v to 4·5 V, and then remain stable. When the first 1290795 voltage (Vrefi) reaches a predetermined value, the input and output circuits are supplied back from the power supply. When the circuit is actuated, the first reference generates a voltage (vDD2) at the second power supply terminal. The embodiment of the stem two f 3B is exemplified by an intermediate voltage: voltage at the power supply terminal (Vddi). The first power supply and the DDI are used to generate the first reference voltage (vREF1) and the reference voltage (VREF2).
為了在電源供電階段和致動階段的期間，產生第三電 應端的電壓(Vdd2)給圖3A中的位準偏移器320,輸入 ^電路之另一較佳實施例如圖4A以及圖5A所示，其中 雨入輸出電路包括電源供電電路和偵測電路47〇。對於如 圖3B所不之輸出電路而言，因為位準偏移器則的電源 ，應線325直接耦接至a點，所以為了位準偏移器31〇的 ，源供應而產生獨立的電壓是不必要的。不過，為了產生 第一參考電壓(vREF1)和第二參考電壓(Vref2)給圖3B中的 輪出電路，輸入輸出電路之另-較佳實施例如圖4B以及 圖5B所示，此輸入輸出電路包括電源供電電路、偵測電 路470以及調節器480。 、 如圖4A所示，電源供電電路包含電阻器41〇、開關電 曰曰體420、電源供電階段電晶體430、致動階段電晶體44〇、 第一保濩電路450以及第二電源供應節點。電阻器 41〇、開關電晶體420以及第一保護電路45〇串聯耦接並跨 接於第一電源供應端290和第二電源供應端295之間。開 15 1290795 r 關電晶體42G之閘極輕接至制電路47〇，以接收開關作 號。 。 • 1源供電階段電晶體430之第-端祕至第一電源供 應端29G。電源供電階段電晶體㈣之第二端減至第三 電源供應節點460。電源供電階段電晶體430之閘極輕接 至電阻器410與開關電晶體42〇之共同節點。致動階段電 晶體440之第-端減至第一電源供應端携。致動階段 電曰曰體440之第二端_馬接至第三電源供應節點偏和電源 籲 供電階段電晶體430之第二端。致動階段電晶體44〇之閑 極耦接至第一參考電壓節點28〇。 在電源供電期間，第三電源供應端的電壓(Vdd2)從電 源供電階段電晶體43G所產生。第三電源供應端的電壓 (vD〇2)，以及第一電源供應端的電壓(Vddi)與電源供電階段 電晶體430的臨界電壓之間的電壓差，兩者大約相同。第 二電源供應端的電壓(vDD2)更對第一參考電壓(Vref ι)的產 生有所貢獻。根據偵測出第一參考電壓(Vrefi)增加至一預 φ 疋值之後，偵測電路470送出開關信號以打開開關電晶體 • 電阻器•電源供電咖 420之共同節點’即c點，其電壓(ve)明顯地下降至關閉 電源供電階段電晶體430。在第一參考電壓(Vrefi)已經到 達一預定值之後，然後第三電源供應端的電壓(Vdd2)由致 動階段電晶體440產生。 為了保護電源供電階段電晶體430之閘極氧化層以避 免崩潰，C點的電壓較佳地稍微高於第二電源供應端的電 16 1290795 壓(VSS1)。第一保護電路450具有第一保護電晶體452和第 二保護電晶體454，而第一保護電路450能增加C點的電 壓(Vc)以避免閘極氧化層崩潰。另外，當開關電晶體420 打開時，電流可以經由電阻器410、開關電晶體420以及 保護電路450而從第一電源供應端(VDD1)流到第二電源供 應端(VSS1)。電阻器410較佳地有大的電阻以限制電流流動 和功率耗損。 在一實施例中，開關電晶體420、電源供電階段電晶 體430、致動階段電晶體440以及第一保護電晶體452皆 為NMOS電晶體。第二保護電晶體454為PMOS電晶體。 電源供電階段電晶體430與致動階段電晶體440之汲極皆 耦接至第一電源供應端290 (VDD1)。電源供電階段電晶體 430與致動階段電晶體440之源極皆耦接至第三電源供應 節點460 (VDD2)。致動階段電晶體440之閘極耦接至第一 參考信號節點280 (VREF1)。電源供電階段電晶體430之源 極與基底耦接在一起。電源供電階段電晶體43〇之閘極耦 接至電阻器410和開關電晶體420之汲極。開關電晶體420 之基底耦接至第二電源供應端(vssi)。第一保護電晶體452 之汲極與閘極皆麵接至開關電晶體42〇之源極。第一保護 電晶體452之基底耦接至第二電源供應端(Vssi)。第一保護 電晶體452之源極耦接至第二保護電晶體454之源極與基 底。第二保護電晶體454之閘極與汲極耦接至第二電源供 應端(Vssi)。 17 1290795 r ® 5A繪示為圖3A中位準偏移器320所需之電源供電 ；- 1路的另—較佳實施例之電路圖，此電源供電電路更包括 第二保護電路510，用以保護電源供電階段電晶體43〇的 閘極氧化層以避免崩潰。第二保護電路51〇具有第三保護 電晶體520和第四保護電晶體5 3 〇串聯祕以增加c點的 電壓(Vc)。第二保護電晶體520之第一端輕接至第 一電源 供應端。第三保護電晶體52〇之第二端耦接至第四保護電 曰曰曰體530之第-端。第三保護電晶體52〇與第四保護電晶 • 體530之閘極皆搞接至第一參考電壓(VREF1)。第四保護電 晶體530之第二端耗接至電阻器41〇與開關電晶體之 共同節點。 為了產生第-參考電壓(Vrefi)和第二參考電壓麗) 給圖3B巾的輸出電路，輸入輸出電路的另一較佳實施例 如圖4B和圖SB所示，其中輸入輸出電路包括電源供電電 路、偵測電路470和調節器480。電源供電階段電晶體43〇 和致動階段電晶體440之第二端皆搞接至調節器、_之輸 • 人端。調節器480輸出第一參考電壓(V删)和第二參考電 壓(VREF2)。在圖4B中的電源供電電路和偵測電路47〇可 以和圖4A中的相同，而在圖5B中的電源供電電路和偵測 電路470可以和圖5A中的相同。 、 雖然本發明已以較佳實施例揭露如上，然其並非用以 限疋本發明，任何熟習此技藝者，在不脫離本發明之 和範圍内，當可作些許之更動與潤飾，因此本發明之保 範圍當視後附之申請專利範圍所界定者為準。 ^In order to generate a voltage (Vdd2) of the third electrical terminal during the power supply phase and the actuation phase to the level shifter 320 of FIG. 3A, another preferred embodiment of the input circuit is as shown in FIG. 4A and FIG. 5A. The rain input output circuit includes a power supply circuit and a detection circuit 47〇. For the output circuit as shown in FIG. 3B, since the power supply of the level shifter is directly coupled to the point a, the source 325 generates a separate voltage for the level shifter 31〇. It is unnecessary. However, in order to generate the first reference voltage (vREF1) and the second reference voltage (Vref2) to the wheel-out circuit of FIG. 3B, another preferred embodiment of the input-output circuit is shown in FIG. 4B and FIG. 5B, the input-output circuit The power supply circuit, the detection circuit 470, and the regulator 480 are included. As shown in FIG. 4A, the power supply circuit includes a resistor 41, a switching body 420, a power supply phase transistor 430, an actuation phase transistor 44, a first protection circuit 450, and a second power supply node. . The resistor 41A, the switching transistor 420, and the first protection circuit 45A are coupled in series and across the first power supply terminal 290 and the second power supply terminal 295. On 15 1290795 r The gate of the 42G transistor is lightly connected to the circuit 47〇 to receive the switch. . • The first end of the transistor 430 in the source supply phase is secreted to the first power supply terminal 29G. The second end of the power supply phase transistor (4) is reduced to the third power supply node 460. The gate of the transistor 430 in the power supply phase is lightly connected to the common node of the resistor 410 and the switching transistor 42. The first end of the actuation phase transistor 440 is reduced to the first power supply terminal. Actuation phase The second end of the electric body 440 is connected to the third power supply node and the second end of the power supply phase 430. The idle electrode of the actuating phase transistor 44 is coupled to the first reference voltage node 28A. During power supply, the voltage (Vdd2) of the third power supply terminal is generated from the power supply stage transistor 43G. The voltage (vD 〇 2) of the third power supply terminal, and the voltage difference between the voltage of the first power supply terminal (Vddi) and the threshold voltage of the power supply phase transistor 430 are approximately the same. The voltage at the second power supply (vDD2) contributes more to the generation of the first reference voltage (Vref ι). After detecting that the first reference voltage (Vrefi) is increased to a pre-φ value, the detecting circuit 470 sends a switching signal to open the switching transistor. • The common node of the power supply 420 is the point c, the voltage thereof. (ve) apparently underground down to turn off the power supply stage transistor 430. After the first reference voltage (Vrefi) has reached a predetermined value, then the voltage (Vdd2) of the third power supply terminal is generated by the actuation phase transistor 440. In order to protect the gate oxide of the transistor 430 during power supply phase to avoid collapse, the voltage at point C is preferably slightly higher than the voltage at the second supply terminal (VSS1). The first protection circuit 450 has a first protection transistor 452 and a second protection transistor 454, and the first protection circuit 450 can increase the voltage (Vc) at point C to avoid breakdown of the gate oxide layer. In addition, when the switching transistor 420 is turned on, current can flow from the first power supply terminal (VDD1) to the second power supply terminal (VSS1) via the resistor 410, the switching transistor 420, and the protection circuit 450. Resistor 410 preferably has a large electrical resistance to limit current flow and power loss. In one embodiment, the switching transistor 420, the power supply phase transistor 430, the actuation phase transistor 440, and the first protection transistor 452 are all NMOS transistors. The second protection transistor 454 is a PMOS transistor. Both the power supply phase transistor 430 and the anode of the actuation phase transistor 440 are coupled to the first power supply terminal 290 (VDD1). The source of the power supply phase transistor 430 and the actuation phase transistor 440 are both coupled to the third power supply node 460 (VDD2). The gate of the actuation phase transistor 440 is coupled to a first reference signal node 280 (VREF1). In the power supply phase, the source of the transistor 430 is coupled to the substrate. The gate of the transistor 43A of the power supply phase is coupled to the drain of the resistor 410 and the switching transistor 420. The base of the switching transistor 420 is coupled to a second power supply terminal (vssi). The drain and the gate of the first protection transistor 452 are both connected to the source of the switching transistor 42. The base of the first protection transistor 452 is coupled to the second power supply terminal (Vssi). The source of the first protection transistor 452 is coupled to the source and the base of the second protection transistor 454. The gate and the drain of the second protection transistor 454 are coupled to the second power supply terminal (Vssi). 17 1290795 r ® 5A is shown as a power supply required for the level shifter 320 of FIG. 3A; a circuit diagram of another preferred embodiment of the 1-way circuit, the power supply circuit further includes a second protection circuit 510 for The gate oxide layer of the transistor 43 is protected from the power supply phase to avoid collapse. The second protection circuit 51A has a third protection transistor 520 and a fourth protection transistor 5 3 〇 in series to increase the voltage (Vc) at point c. The first end of the second protection transistor 520 is lightly connected to the first power supply terminal. The second end of the third protection transistor 52 is coupled to the first end of the fourth protection electrode body 530. The third protection transistor 52A and the fourth protection transistor 530 are connected to the first reference voltage (VREF1). The second end of the fourth protection transistor 530 is drained to a common node of the resistor 41A and the switching transistor. In order to generate the first reference voltage (Vrefi) and the second reference voltage MN to the output circuit of FIG. 3B, another preferred embodiment of the input and output circuit is shown in FIG. 4B and FIG. SB, wherein the input and output circuit includes a power supply circuit. , detection circuit 470 and regulator 480. The power supply stage transistor 43A and the second end of the actuation stage transistor 440 are connected to the regulator, the input terminal, and the human terminal. The regulator 480 outputs a first reference voltage (V deleted) and a second reference voltage (VREF2). The power supply circuit and detection circuit 47A in Fig. 4B can be the same as in Fig. 4A, and the power supply circuit and detection circuit 470 in Fig. 5B can be the same as in Fig. 5A. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the scope of the present invention, and those skilled in the art can make some modifications and refinements without departing from the scope of the invention. The scope of the invention is subject to the definition of the scope of the patent application. ^
1290795 【圖式簡單說明】 圖1繪示為傳統的輸出電路之電路圖。 具陳氧化層倾之以/糾電路的一 季父佳實施例之電路圖。 圖3Α繪示為圖2所示的具閘極氧化層保護之輸入/輸 出電路的另-較佳實關之電關，其巾更包括位準偏移 器和内部電路。 圖3Β繪示為圖3Α所示的具閘極氧化層保護之輸入/ 輸出電路的另一較佳實施例之電路圖，其中位準偏移器之 電壓供應耦接至Α點。 " 圖4Α繪示為電源供電電路以及偵測電路的一較佳實 施例之電路圖，其中電源供電電路以及偵測電路用以產生 圖3Α中位準偏移器之電壓供應。 圖4Β繪示為電源供電電路、偵測電路以及調節器的 一較佳實施例之電路圖，其中電源供電電路、偵測電路以 及調節器用以產生圖3Β中第一參考電壓以及第二參考電 壓。 圖5Α繪示為圖4Α所示的電源供電電路的另一較佳實 施例之電路圖，此電源供電電路包括第二保護電路。 圖5Β繪示為圖4Β所示的電源供電電路的另一較佳實 施例之電路圖，此電源供電電路包括第二保護電路。 【主要元件符號說明】 100、200、300 ··輸入/輸出電路 110、115、210、220、280、285 :輸入節點 19 1290795 . 120、230 ··輸出節點 130、140、250、270 :輸出電晶體 150、160、290、295、320、330、350、360、Vcc VdD、V〇Dl、V〇D2、Vssi、VsS2 :電源供應端（的電壓） 240、260 :夾止電晶體 310 :位準偏移器 325 :電源供應線 340 :内部電路 • 410 ··電阻器 420 :開關電晶體 430 :電源供電階段電晶體 440 :致動階段電晶體 450、510 :保護電路 452、454、520、530 :保護電晶體 460 :第三電源供應節點 470 :偵測電路 • 480 :調節器 A、B、C :共同節點1290795 [Simple description of the drawing] FIG. 1 is a circuit diagram of a conventional output circuit. A circuit diagram of a parent-friendly embodiment with a white oxide/deformation circuit. FIG. 3 is a diagram showing another preferred embodiment of the input/output circuit with gate oxide protection shown in FIG. 2, the wiper further including a level shifter and an internal circuit. 3A is a circuit diagram of another preferred embodiment of the input/output circuit with gate oxide protection shown in FIG. 3A, wherein the voltage supply of the level shifter is coupled to the defect. < Figure 4A is a circuit diagram showing a preferred embodiment of a power supply circuit and a detection circuit, wherein the power supply circuit and the detection circuit are used to generate a voltage supply of the level shifter of Figure 3. 4 is a circuit diagram of a power supply circuit, a detection circuit, and a regulator, wherein the power supply circuit, the detection circuit, and the regulator are used to generate the first reference voltage and the second reference voltage in FIG. 5 is a circuit diagram of another preferred embodiment of the power supply circuit shown in FIG. 4A. The power supply circuit includes a second protection circuit. 5 is a circuit diagram of another preferred embodiment of the power supply circuit shown in FIG. 4A. The power supply circuit includes a second protection circuit. [Description of main component symbols] 100, 200, 300 · Input/output circuits 110, 115, 210, 220, 280, 285: Input node 19 1290795 . 120, 230 · Output nodes 130, 140, 250, 270: Output The transistors 150, 160, 290, 295, 320, 330, 350, 360, Vcc VdD, V〇Dl, V〇D2, Vssi, VsS2: voltage of the power supply terminal 240, 260: the clamping transistor 310: Level offset 325: power supply line 340: internal circuit • 410 • Resistor 420: Switching transistor 430: Power supply stage transistor 440: Actuation stage transistor 450, 510: Protection circuit 452, 454, 520 , 530: protection transistor 460: third power supply node 470: detection circuit • 480: regulators A, B, C: common node
Nl、N2、N3 : NMOS 電晶體 PI : PMOS電晶體 VA、VB、Vc :共同節點的電壓Nl, N2, N3: NMOS transistor PI: PMOS transistor VA, VB, Vc: voltage of the common node
VreFI > VreF2 :參考電壓VreFI > VreF2 : Reference voltage