JP2000323671A - Signal holding circuit, semiconductor device, gate array and ic card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a signal holding circuit and the like which can hold the results of computation or the like even if power is shut off and consumes less power. SOLUTION: A logic processing circuit 56 is provided with a combination logic block CB and a latch block LT. The latch block LT is provided with a line 104 for transmitting results OUT of computation from the combination logic block CB. A part of the line 104 is a loop signal path (feed back loop) provided with a line 106 and a line 108. An inverter circuit INV2 composed of ferroelectric transistors is interposed into the line 108. As a result, the results OUT of computation appearing on the line 104 can be held in a volatile manner and data just before the power shutoff can be restored on the line 104 as the power is restored. Also, a power control part 55 shutting off the power supplied to the latch block LT is provided for power savings.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal holding circuit and the like, and more particularly to a signal holding circuit and the like using a ferroelectric material.

[0002]

2. Description of the Related Art IC cards are used as identification tags used in credit cards and distribution processes.
There are IC cards equipped with a logic LSI and those equipped with a microcomputer. A circuit as shown in FIG. 26 is known as a sequence logic processing circuit used in such a logic LSI or a microcomputer. Have been.

The logic processing circuit 2 shown in FIG.
It comprises a combinational logic block CB composed of a circuit, an OR circuit and the like, and a latch block LT for latching the output of the combinational logic block CB.

The combinational logic block CB has input data I
A predetermined logical operation or the like is performed on N, and an operation result OUT is output. The latch block LT outputs the clock pulse Cp
The operation result OUT at the time of rising (or at the time of rising) is latched. The latched operation result OUT is output to the output Q.

As described above, when the logic processing circuit 2 is used,
The calculation result is latched at the timing of the rising (or falling) of the clock pulse Cp, and the latched calculation result can be output until the next clock pulse Cp comes. Therefore, a stable output can be obtained by removing noise from the operation result.

Therefore, by using a large number of such logic processing circuits 2 in combination, highly reliable sequence logic processing can be performed.

[0007]

However, the conventional logic processing circuit 2 as described above has the following problems. In a conventional logic processing circuit, a voltage must always be applied to the circuit in order to hold data being processed.

Therefore, in the case where the power supply is cut off during the sequence logic processing, even if the power supply is restored, the operation result before the power cut-off does not remain, and the sequence logic processing is performed in the state immediately before the power cut-off. To return to, it was necessary to restart from the beginning of the sequence logic processing. This is wasteful and lacks processing reliability.

In a non-contact IC card or the like,
Since power is supplied via radio waves, power supply becomes unstable. In particular, when a large amount of data processing is required in real time, the processing becomes difficult when the supply of power is stopped.

Further, in order to suppress the power consumption of the circuit,
A power-saving latch block LT as shown in FIG. 27 has been proposed. The focus is on the point that power consumption can be reduced by using a transistor with a high threshold voltage.

The low-threshold circuit section 4 is a circuit including inverter circuits INV0 and INV1 formed by using low-threshold transistors which consume a large amount of power but operate at a high speed. The high-threshold circuit section 6 is a circuit including inverter circuits INV2 and INV3 configured using high-threshold transistors whose operation speed is low but whose power consumption is small.

The power control unit 8 supplies power to the low threshold circuit unit 4 during operation, and stops supplying power to the low threshold circuit unit 4 during standby. In this way, the operation result OUT is output via the inverter circuits INV0 and INV1 having a high operation speed during operation, and the operation result OUT is held by the inverter circuits INV2 and INV3 having low power consumption during standby. So
It is convenient.

However, even in the power-saving latch block LT shown in FIG. 27, power consumption is reduced during standby, but power consumption is not changed.

The present invention solves such a problem of the conventional logic processing circuit, and can maintain a calculation result or the like even when the power supply is cut off. The purpose is to provide.

[0015]

Means for Solving the Problems, Functions and Effects of the Invention
The signal holding circuit according to claim 1, further comprising: a signal path for transmitting a signal; and a polarization state coupled to the signal path, the polarization state corresponding to the signal appearing in the signal path at the time of operation being maintained after the operation is stopped. A ferroelectric storage unit for restoring a signal to a signal path when the operation is restored based on the state.

Therefore, the signal appearing in the signal path is held in the ferroelectric storage unit in a polarization state corresponding to the signal. Therefore, even if the power is cut off, the data is held in the ferroelectric storage unit.

As a result, when the power supply is restored, the state of the signal holding circuit can be surely and promptly returned to the state before the power supply was cut off by using the held data. Becomes That is, even if the power is cut off, the calculation result and the like can be held.

In the signal holding circuit according to the second aspect, an annular signal path having a main signal path and a feedback signal path is provided in a part of the signal path, and a strong signal path is provided in at least one of the main signal path and the feedback signal path. It is characterized in that a dielectric storage unit is connected.

Therefore, by providing the feedback signal path, the normal operation and the operation when the power is restored can be further stabilized.

According to a third aspect of the present invention, in the signal holding circuit, a ferroelectric transistor is used as the ferroelectric storage unit.

Therefore, nondestructive reading can be easily realized, and a long-life signal holding circuit can be easily realized.

According to a fourth aspect of the present invention, in the signal holding circuit, the ferroelectric transistor includes: A) a source region and a drain region of a first conductivity type formed in a semiconductor substrate; and B) a source region and a drain region. The second
A channel forming region of a conductivity type; C) an insulating layer disposed on the channel forming region; D) a first conductor layer disposed on the insulating layer; E) on the first conductor layer. And F) a second conductor layer formed on the ferroelectric layer.

Therefore, by using a transistor having the above structure as a ferroelectric transistor, the ordinary M
A signal holding circuit can be easily obtained simply by adding a step of stacking a ferroelectric layer and a second conductor layer to the OSFET manufacturing process.

In the signal holding circuit according to the fifth aspect, an inverter circuit is inserted into each of the main signal path and the feedback signal path, and at least one of the inverter circuits is used as a ferroelectric storage unit using a ferroelectric transistor. It is characterized by having.

Therefore, by making the transistor constituting the inverter circuit a ferroelectric transistor,
A signal appearing in the signal path can be held in the ferroelectric transistor.

According to a sixth aspect of the present invention, in the signal holding circuit, on the input side of the ring-shaped signal path, an input side gate for performing a switching operation based on a predetermined gate control signal is provided in the signal path.

Therefore, even when the operation result from the combinational logic circuit includes noise, a stable output can be obtained by removing the noise.

In the signal holding circuit of the present invention, an inverter circuit is inserted into the main signal path, and the input side of the inverter circuit and a predetermined reference potential are connected via a switching circuit having a control input terminal. The output side of the inverter circuit and the control input terminal are coupled by a feedback signal path, and at least one of the inverter circuit and the switching circuit is a ferroelectric storage unit using a ferroelectric transistor. It is characterized by.

Therefore, when the signal path is a bus line, the signal on the bus line is stored in the ferroelectric storage unit in a polarization state corresponding to the signal. In other words, signals and the like on the bus line can be retained even when the power is cut off.

The signal holding circuit according to claim 8 is characterized in that the ferroelectric memory is provided only in the feedback signal path.

Therefore, by not providing the ferroelectric storage section in the main signal path, the signal transmission speed at the time of non-latching can be increased.

In the signal holding circuit according to the ninth aspect, a feedback gate for interrupting a feedback signal path when transmitting a signal via the main signal path and connecting the feedback signal path when feeding back the signal via the feedback signal path. It is characterized by having provided.

Therefore, by cutting off the feedback signal path, it is possible to reduce the power consumption during non-latching.

According to a tenth aspect of the present invention, in the signal holding circuit, a ferroelectric capacitor is used as the ferroelectric storage unit.

Therefore, a more reliable signal holding circuit can be realized by using a ferroelectric capacitor capable of easily obtaining a stable operation.

In the signal holding circuit according to the eleventh aspect, an input side gate that performs a disconnection operation based on a predetermined gate control signal, and an output that performs a reverse disconnection operation of the input side gate based on the gate control signal Side gate is inserted in series in the signal path, one end of the ferroelectric capacitor is coupled to the signal path between the input side gate and the output side gate, and the other end of the ferroelectric capacitor is connected to the gate. It is characterized in that a voltage synchronized with the control signal is applied.

Therefore, for example, by connecting the signal path and the bus line via the output side gate, a signal holding circuit connectable to the bus line can be easily realized.

According to a twelfth aspect of the present invention, there is provided the signal holding circuit, wherein a storage section gate for disconnecting the signal path from the ferroelectric storage section is provided.

Therefore, the signal path and the ferroelectric memory can be cut off by the memory gate if necessary. For this reason, it is possible to prevent the polarization state of the ferroelectric storage unit from being carelessly changed due to the signal path.

According to a thirteenth aspect of the present invention, in the signal holding circuit, the storage unit gate disconnects the signal path from the ferroelectric storage unit in response to a change in the power supply voltage.

Therefore, it is possible to prevent the polarization state of the ferroelectric memory unit from being changed carelessly due to a change in the power supply voltage such as a decrease in the power supply voltage.

According to a fourteenth aspect of the present invention, in the signal holding circuit, there is provided a power supply control unit for switching off or adjusting the power supplied to the signal holding circuit.

Therefore, the power supplied to the signal holding circuit constituting the inactive block is cut off by the power supply control unit or is extremely reduced, so that power consumption can be suppressed. In this case, for example, even if the power supplied to the signal holding circuit is cut off, the polarization state of the ferroelectric memory unit is maintained, and when the power supply is resumed with the restart of operation, a signal corresponding to the polarization state is output. It is convenient because it can be given to the road.

According to a fifteenth aspect of the present invention, the signal holding circuit is connected to a combinational circuit via a signal path.

Therefore, by using a logic processing circuit having a combinational circuit and a nonvolatile signal holding circuit, highly reliable sequence logic processing can be performed.

According to a sixteenth aspect of the present invention, in the signal holding circuit, the combinational circuit is a power saving type circuit.

Therefore, by using a power-saving combination circuit, for example, a combination circuit capable of adjusting power or a combination circuit having a small number of elements, power saving can be further promoted.

A semiconductor device according to a seventeenth aspect is characterized by using a signal holding circuit and a combinational circuit connected to the holding circuit.

Therefore, it is possible to realize a semiconductor device capable of holding a calculation result and the like even when the power is cut off, and a power-saving semiconductor device.

The semiconductor device according to claim 18 is characterized by further comprising a ferroelectric memory circuit.

Therefore, in a semiconductor device requiring a memory, the memory can also be nonvolatile.
Therefore, a semiconductor device with higher power saving effect can be realized.

The semiconductor device according to the nineteenth aspect is characterized in that the semiconductor device is a microcomputer.

Therefore, it is possible to realize a microcomputer capable of holding the operation result and the like even when the power is cut off, and a power-saving microcomputer.

According to a twentieth aspect of the present invention, the semiconductor device is configured using a gate array.

Therefore, it is possible to easily realize a semiconductor device or a power-saving semiconductor device which can hold the operation result and the like even when the power is cut off. Further, by changing the connection of the gate array, it is possible to easily change to hardware having another function.

A gate array according to a twenty-first aspect is characterized by comprising a transistor and an element formed of a ferroelectric.

Therefore, by freely combining a transistor and an element made of a ferroelectric material, a semiconductor device capable of retaining an operation result or the like even when power is cut off, or a power-saving type semiconductor device Can be easily realized.

An IC card according to a twenty-second aspect is characterized by using any one of the above semiconductor devices.

Therefore, the power supply is particularly unstable,
In a non-contact type IC card with low power supply,
Even if the power supply is cut off, the calculation result etc. can be held,
In addition, power consumption can be advantageously reduced.

In the claims, "ferroelectric storage unit"
The term "part" refers to a part for storing information using the hysteresis characteristics of a ferroelectric substance, and is a concept including a ferroelectric transistor, a ferroelectric capacitor itself, and a circuit in which these are combined. In the embodiment, the inverter circuit INV2 shown in FIG.
Corresponds to this.

The term “ferroelectric transistor” refers to a transistor using a ferroelectric, and is a concept including a transistor having a so-called MFMIS structure and a transistor having an MFS structure (described later). In the embodiment, the transistors NT and PT shown in FIG. 4 correspond to this.

[0062]

FIG. 1 is a circuit diagram showing a logic processing circuit 50 used in a semiconductor device according to one embodiment of the present invention. The logic processing circuit 50 includes a combinational logic block CB that is a combinational circuit, and a latch block LT that is a signal holding circuit.

The combinational logic block CB is composed of a NAND circuit, an OR circuit, etc.
(Eg, four inputs of A, B, C, and D) are subjected to a predetermined logical operation or the like, and an operation result OUT is output.

The latch block LT has a line 104 constituting a signal path for transmitting the operation result OUT.
A part of the line 104 is a line 10 constituting the main signal path.
6 and a line 108 constituting a feedback signal path. By lines 106 and 108,
It constitutes a ring signal path.

On the input side of the ring signal path, line 1
A transmission gate GT1, which is an input-side gate that performs a switching operation based on a clock pulse Cp, which is a gate control signal, is inserted in 04. The transmission gate GT1 is configured to be turned off when the clock pulse Cp is “H” and to be turned on when the clock pulse Cp is “L”.

A transmission gate GT2, which is a feedback gate, is inserted into the line 108. The transmission gate GT2 is turned on when the clock pulse Cp is “H”, and is turned off when the clock pulse Cp is “L”, contrary to the transmission gate GT1.
F.

As described above, the transmission gate G
By inserting T2 to cut off the line 108, power consumption during non-latching can be reduced.

The line 106 includes an inverter circuit INV
1 is inserted. The inverter circuit INV1 has a CM
An OS inverter circuit having a configuration in which a P-channel MOSFET and an N-channel MOSFET are connected in series.

As described above, the line 1 constituting the main signal path
By not providing a ferroelectric transistor in 06, the signal transmission speed during non-latching can be increased.

An inverter circuit INV2, which is a ferroelectric storage unit, is inserted into the line 108. The inverter circuit INV2 has the same configuration as the inverter circuit INV1.
Although it is a MOS inverter circuit, as shown in FIG. 4, a transistor PT which is a P-channel MOSFET which is a component and a transistor N which is an N-channel MOSFET
The difference from the inverter circuit INV1 is that T is a ferroelectric transistor.

Transistor NT and Transistor PT
Are ferroelectric transistors having a so-called MFMIS structure (from the top, a metal layer, a ferroelectric layer, a metal layer, an insulating layer,
(A transistor having a structure in which silicon layers are stacked in this order).

FIG. 3A shows the structure of the transistor NT. A source region 22 and a drain region 24 made of an n-type (first conductivity type) semiconductor are formed on a p-type silicon substrate 20, which is a semiconductor substrate. An insulating layer 28 made of silicon oxide (SiO ₂ ) is provided on the channel formation region 26 made of a p-type (second conductivity type) semiconductor. On the insulating layer 28, a lower conductive layer (first conductive layer) 30 in which Poly-Si, IrO ₂ , and Ir are laminated in this order is provided.

A ferroelectric layer 32 made of PZT or the like is provided thereon. The ferroelectric layer 32 maintains a polarization state corresponding to the cutoff state of the transistor NT, as described later.

An upper conductor layer (second conductor layer) 34 in which IrO ₂ and Ir are laminated in this order is further provided thereon.

The insulating layer 28 may be made of silicon nitride (SiN) or the like in addition to the above. The lower conductor layer 30 and the upper conductor layer 34 are, in addition to the above,
Oxide conductors such as RuOx and ITO, and metals such as Pt, Pb, Au, Ag, Al, and Ni can be used.

FIG. 3B shows the transistor NT in FIG. 3A by symbols. The control gate electrode CG is connected to the upper conductor layer 34. No electrodes are connected to the lower conductor layer 30 and the lower conductor layer 30 is in a floating state. The source electrode 22 is connected to the source region 22, and the drain electrode D is connected to the drain region 24.

The control gate electrode CG (the input side of the inverter circuit INV2) is connected to the output side of the inverter circuit INV1 shown in FIG. 1, and the drain electrode D (the output side of the inverter circuit INV2) is connected to the transmission gate GT2. , Source electrode S is grounded.

The transistor NT and the transistor PT are one except that one is an “N-channel type” MOSFET and the other is a “P-channel type” MOSFET.
It has a similar configuration. That is, the transistor PT also has M
This is a ferroelectric transistor having an FMIS structure.

Operation result O from combinational logic block CB
The UT is input via the transmission gate GT1, is inverted by the inverter circuit INV1, is re-inverted (that is, is restored) by the inverter circuit INV2, and is input again to the inverter circuit INV1. That is, the data holding is stabilized using the feedback circuit having the inverter circuit INV2. Note that the output of the inverter circuit INV1 becomes the output Q of the latch block LT.

The operation of the latch block LT shown in FIG.
7 is similar to the operation of the conventional latch block LT shown in FIG. 7, but is different from the conventional latch block LT in that the data is retained even when the power is cut off, as described later.
In this embodiment, the operation result OUT is latched at the rising timing of the clock pulse Cp.

Using the timing chart shown in FIG.
The operation of the latch block LT will be described. When the clock pulse CP changes from "L" to "H" (see FIG. 2, (a)), the transmission gate GT1 is turned off (disconnected state) and the transmission gate GT2 is turned off.
Is turned ON (connected state). Therefore, the data corresponding to the operation result OUT at the rise of the clock pulse Cp (the output Q has a value obtained by inverting the operation result OUT) is latched by the latch block LT and output as the output Q. While the clock pulse Cp is "H", the data corresponding to the latched operation result OUT is output.

Next, when the clock pulse Cp changes from "H" to "L" (see FIG. 2, (b)), the transmission gate GT1 is turned on (in a continuous state), and
The transmission gate GT2 is turned off (disconnected state). Therefore, the output Q includes the current operation result OUT.
(The output Q has a value obtained by inverting the operation result OUT) is output as it is.

Next, when the clock pulse Cp changes from "L" to "H" (see FIG. 2, (c)), the transmission gate GT1 is again turned off (disconnected state), and the transmission gate GT2 is turned on (disconnected state). State). Therefore, the data corresponding to the operation result OUT at the rising of the clock pulse Cp (the output Q is
The calculation result OUT is a value obtained by inverting the calculation result OUT) is latched by the latch block LT and output as the output Q.

As described above, in the latch block LT, the operation result OUT is latched at the timing of the rise of the clock pulse Cp, and the clock pulse Cp becomes “H”.
During this period, the data corresponding to the latched operation result OUT can be output. Therefore, if the output Q during which the clock pulse Cp is "H" is used, even if the operation result OUT from the combinational logic block CB includes noise, the noise is removed. ,
A stable output can be obtained.

As described above, the logic processing circuit 5 shown in FIG.
Unlike the latch block LT forming the conventional logic processing circuit 2 shown in FIG. 26, the latch block LT forming 0 holds data even when power is cut off. The operation of holding and reproducing data will be described.

As described above, at the rising of the clock pulse Cp, that is, the data corresponding to the operation result OUT immediately before the clock pulse Cp changes from “L” to “H”, is latched in the latch block LT. For convenience of description, it is assumed that the corresponding data is “H” (the operation result OUT itself is “L”).

FIG. 4 shows the state of the inverter circuit INV2 when the clock pulse Cp rises. FIG.
As shown in FIG. 7, the "L" potential is applied to the source electrode S of the transistor NT of the inverter circuit INV2.
The “H” potential is applied to the source electrode S of the transistor PT.

The control gate electrodes CG of the transistors NT and PT are both at the “H” potential. When the control gate electrode CG goes to the “H” potential, the transistor NT turns “ON” and the transistor PT
The threshold value _{Vth of} each of the transistors NT and PT is set so that is turned "OFF". Therefore,
In this case, the drain electrodes D of the transistors NT and PT
Are both at "L" potential.

In such a state, the transistor N
The T and PT ferroelectric layers 32 have a predetermined polarization state, as described later. That is, the data “H” is
The predetermined polarization state generated in the ferroelectric layer 32 of the transistors NT and PT is written in the latch block LT.

Thereafter, when the clock pulse Cp rises and becomes "H", the transmission gate GT1
Is turned off, but the self-latch function of the inverter circuits INV1 and INV2 causes the ON state of the transistor NT and the O
The FF state is maintained. That is, data "H" is latched in latch block LT.

The state of the transistors NT and PT during the period from the writing of data "H" to the latch state will be described. First, the state of the transistor NT will be described.

As shown in FIGS. 3A and 3B, the transistor N
T is a ferroelectric capacitor C _ferro formed between the upper conductor layer 34 and the lower conductor layer 30, and a capacitor formed between the lower conductor layer 30 and the channel region 26. a certain MOS capacitor C _MOS, can be considered to be connected in series. A capacitor obtained by combining the ferroelectric capacitor C _ferro and the MOS capacitor C _MOS is called a GATE capacitor C _GATE .

FIG. 5 shows the ferroelectric capacitors C _ferro and MO of the transistor NT when data “H” is written.
An example of the voltage-charge characteristics of the S capacitance _CMOS is shown.

As described above, since the transistor NT is ON (see FIG. 4), the channel region 26 (FIG. 3)
A) is almost at the ground potential. Also,
"H" is applied to the control gate electrode CG of the transistor NT.
(V _DD ) "potential.
The E capacitance C _GATE has + V with respect to the channel region 26.
The voltage of _DD is applied.

For this reason, as shown in FIG.
Quantity C_ferroIs P4. Similarly, MOS capacitance
C_MOSState becomes S4. In addition, indicated by S4 point
The state charge has the same value as the state charge indicated by point P4.
is there. At this time, the MOS capacitor C _MOSVoltage,
That is, the lower conductive layer 30 (floating gate)
The generated voltage is V_TwoIt has become.

Next, the state of the transistor PT will be described. FIG. 6 shows the ferroelectric capacitance C _ferro and the MOS of the transistor PT when data “H” is written.
5 shows the voltage-charge characteristics of the capacitance _CMOS . In FIG. 6, in order to facilitate comparison with the transistor NT,
The polarity of the voltage axis (horizontal axis) is reversed from that in FIG. Thus, for example, a voltage -V ₄ shown in FIG. 6 is actually a positive potential.

As described above, the transistor P shown in FIG.
Since T is OFF, the potential of the channel region of the transistor PT is almost half of the power supply potential V _DD . Further, a potential “H (V _DD )” is applied to the control gate electrode CG of the transistor PT. Therefore, a voltage of ・ · _VDD is applied to the GATE capacitor C _GATE with reference to the channel region 26.

[0098] Therefore, as shown in FIG. 6, strong state of the dielectric capacitor C _ferro becomes P4, MOS capacitor C _MOS state becomes S4. The electric charge in the state indicated by the point S4 is
This is the same value as the charge in the state indicated by point P4. At this time, the voltage generated in the MOS capacitor _CMOS , that is, the voltage generated in the lower conductor layer 30 (floating gate) is
It has become a -V _4.

Next, an operation in the case where the power supply (not shown) of the latch block LT is cut off, and then the power supply is turned on again will be described. First, the state of the transistor NT will be described.

When the power supply is cut off while the latch block LT stores data “H”, the ferroelectric capacitors C _ferro and M ferroelectric capacitors C _ferro and M of the transistor NT change over time.
Voltage-charge appearing on OS capacitance C _MOS, respectively, FIG. 5
The state indicated by points P4 and S4 changes from the state indicated by points P5 and S5. Ferroelectric capacitor C _ferro
And the MOS capacitor C _MOS are connected in series.
The charges at the points 5 and S5 become equal. Also, the sum of the voltages at points P5 and S5 should be 0V.
Therefore, the voltage at point P5 and the voltage at point S5 have a relationship in which the absolute values are equal and the polarities are opposite.

[0102] Here, when power cycle the latch block LT, along with power-on, the state of the voltage-charge appearing at the MOS capacitor C _MOS is suddenly changed S5 to point to S4 points. Here, the electric charge in the state indicated by the point S4 has the same value as the electric charge in the state indicated by the point P4.

[0102] voltage generated at this time the MOS capacitor C _MOS, i.e., the voltage generated in the floating gate has a V _2. That is, the transistor NT
This is the same ON state as before the power was turned off.

As shown in FIG. 5, the ferroelectric capacitor C _ferro
Will return from P5 to P4. Similarly, M
OS capacitance C _MOS state, the process returns from S5 is S4.

Next, the state of the transistor PT will be described. When the latch block LT blocks the power remains stored with data "H", the voltage-charge appearing on the ferroelectric capacitor C _ferro and the MOS capacitor C _MOS transistor PT, respectively, P4 points and S4 point 6 The state indicated by the point is changed to the state indicated by the points P5 and S5.

[0105] Here, when power cycle the latch block LT, along with power-on, the state of the voltage-charge appearing at the MOS capacitor C _MOS is suddenly changed S5 to point to S4 points. Here, the electric charge in the state indicated by the point S4 has the same value as the electric charge in the state indicated by the point P4.

[0106] voltage generated at this time the MOS capacitor C _MOS, i.e., the voltage generated in the floating gate,
It has become a -V _4. That is, the transistor PT
This is the same OFF state as before the power was turned off.

As shown in FIG. 6, the ferroelectric capacitor C _ferro
Will return from P5 to P4. Similarly, M
OS capacitance C _MOS state, the process returns from S5 is S4.

That is, when the power of the latch block LT is turned off and then turned on again,
T is the state before the power is turned off, that is, data "
It can be seen that the state returns to the state where "H" is latched.

The case where data “H” is latched in latch block LT has been described as an example.
The operation when data "L" is latched in T is almost the same. That is, regardless of the contents of the latch data, the latch block LT stores the data even when the power is turned off, and can reproduce the data when the power is restored.

As described above, this latch block LT includes the inverter circuit INV2 constituted by ferroelectric transistors. Therefore, the operation result OUT from the combinational logic block CB is converted into the inverter circuit INV in the form of a polarization state corresponding to the operation result OUT.
2 holds. Therefore, even if the power is cut off, the data is held by the inverter circuit INV2.

As a result, when the power is restored, the combinational logic block CB is
To the value before the power was turned off,
It is possible to reliably and quickly return. That is, a nonvolatile latch circuit can be realized.

Since the time required for the polarization inversion of the ferroelectric substance is short, the inverter circuit IN
The time required for V2 to reach the polarization state corresponding to the operation result OUT is short. Therefore, high-speed response is possible.

Further, in the case of a ferroelectric material, a high voltage is not required for writing and erasing data. Therefore,
There is no need to provide a booster circuit in the chip or separately prepare a high-voltage power supply in addition to the normal power supply. Therefore, an increase in chip size and an increase in manufacturing cost can be suppressed.

In this embodiment, an inverter circuit INV2 having a pair of transistors as ferroelectric transistors NT and PT is used as a ferroelectric memory. Therefore, the ferroelectric transistors NT and PT hold the polarization state corresponding to the operation result OUT. For this reason, when the power is restored after the power is cut off,
Using the held signal, the latch block LT
Can be more reliably returned to the state before the power was cut off.

However, only one of the transistors NT and PT constituting the inverter circuit INV2 can be a ferroelectric transistor. In this case, the processing speed is further increased.

Further, in the above-described embodiment, of the inverter circuits INV1 and INV2 included in the latch block LT, only the inverter circuit INV2 inserted in the feedback signal path uses the ferroelectric transistor. However, conversely, it is also possible to use a ferroelectric transistor only for the inverter circuit INV1 inserted in the main signal path.

In addition, like a logic processing circuit 52 used in a semiconductor device according to another embodiment of the present invention shown in FIG. 7, an inverter circuit IN included in a latch block LT is provided.
It is also possible to employ a configuration in which a ferroelectric transistor is used for both V1 and the inverter circuit INV2.

In each of the above embodiments, a ferroelectric transistor having a so-called MFMIS structure has been described as an example of a ferroelectric transistor, but the ferroelectric transistor is not limited to this. As the ferroelectric transistor, for example, a transistor NT as shown in FIG. 13A can be used.

A transistor NT shown in FIG. 13A is an n-channel MOSFET. A source region 22 and a drain region 24 made of an n-type semiconductor are formed on a p-type silicon substrate 20, which is a semiconductor substrate. A ferroelectric layer 32 made of a ferroelectric material such as PZT is provided on the channel region 26 made of a p-type semiconductor. The conductor layer 40 is provided on the ferroelectric layer 32.

A transistor of this type is referred to as MF
It is referred to as an S-structure transistor (a transistor having a structure in which a metal layer, a ferroelectric layer, and a silicon layer are stacked in this order from the top). Note that a transistor having an MFIS structure in which an insulating material is interposed between a ferroelectric layer and a silicon layer (semiconductor substrate) can also be used.

FIG. 13B shows the transistor NT in FIG. 13A represented by a symbol. The gate electrode G is connected to the conductor layer 40. The source electrode 22 is connected to the source region 22, and the drain electrode D is connected to the drain region 24.

This transistor NT is a normal MOSF
This is a transistor in which the insulating layer of ET is made of a ferroelectric material such as PZT instead of silicon oxide. Therefore, a nonvolatile latch circuit can be easily obtained by only partially changing the material of a storage transistor used in a conventional SRAM or the like. The p-channel MOSFET
As the transistor PT, a transistor having a structure similar to that of the transistor NT illustrated in FIG. 13A can be used.

Further, the ferroelectric memory is not limited to the ferroelectric transistor. For example, a ferroelectric capacitor can be used. In this case, for example, instead of the ferroelectric transistor NT shown in FIG.
What is necessary is just to use a ferroelectric capacitor connected in series to the gate electrode of a normal MOSFET.

With such a configuration, a nonvolatile latch circuit can be easily obtained by using a normal MOSFET used for a conventional latch circuit as it is and adding a new ferroelectric capacitor.

Further, in each of the above embodiments, the transmission gate is used as the gate, but the gate is not limited to this. For example, a transistor or a clocked CMOS inverter can be used as the gate.

In each of the above embodiments, for convenience of explanation, a logic processing circuit using one latch block as a signal holding circuit has been described. However, a circuit actually used in a semiconductor device or the like is a signal processing circuit. As a holding circuit,
In many cases, a flip-flop circuit in which two latch blocks are connected in series is used.

FIG. 23 is a circuit diagram showing a logic processing circuit 112 used in a semiconductor device according to still another embodiment of the present invention. In the logic processing circuit 112, a flip-flop circuit FF in which two latch blocks are connected in series is used as a signal holding circuit.

FIG. 24 is a timing chart showing the operation of flip-flop circuit FF shown in FIG. The flip-flop circuit FF is configured by connecting a latch block LT1 (master latch circuit) and a latch block LT2 (slave latch circuit) in series. In addition,
PA in FIG. 24 represents the output signal of the latch block LT1, that is, the signal at the point PA in FIG.

When the clock pulse Cp changes from “H” to “L” (see FIG. 24A), the latch block LT1
Becomes latched, and the latch block LT2 becomes unlatched. Therefore, the clock pulse Cp
(The signal at the point PA is the inverted value of the data Dn) corresponding to the data at the time of falling (the operation result OUT of the combinational logic block CB) Dn (current data) is latched in the latch block LT1. As well as
The output D outputs the data Dn.

Next, when the clock pulse Cp changes from “L” to “H” (see FIG. 24B), the latch block LT1 enters the unlatched state and the latch block LT2 enters the latched state. Therefore, data D
n is latched by the latch block LT2, and the data Dn is also output to the output Q.

Next, when the clock pulse Cp changes from "H" to "L" (see FIG. 24, (c)), the latch block LT1 enters the latch state again, and the latch block LT2 enters the unlatched state again. Therefore, the data corresponding to the data Dn + 1 (next data) at the falling of the clock pulse Cp (the signal at the point PA is the data D
n is the inverted value) is the latch block LT1
And the output Q is applied to the data Dn +
1 is output.

As described above, when the flip-flop circuit FF is used, data is latched at the falling timing of the clock pulse Cp, and the latched data is output for a time corresponding to one cycle of the clock pulse Cp. Can be. Therefore, even if the data (the operation result OUT from the combinational logic block CB) includes noise, the noise can be removed and a more stable output can be obtained.

Therefore, by using a combination of such a flip-flop circuit FF and a combinational logic block CB constituted by logic gates and the like, a more reliable sequence processing can be performed.

The flip-flop circuit FF shown in FIG.
, One transistor (N-channel MO) of the inverter circuit INV2 forming the latch block LT1
SFET) is a ferroelectric transistor, but any transistor of any inverter circuit of any latch block constituting the flip-flop circuit FF may be a ferroelectric transistor. Further, two or more of the plurality of transistors may be ferroelectric transistors.

The above-described variations can be similarly applied to various other embodiments described below.

FIG. 8 shows a logic processing circuit 54 used in a semiconductor device according to still another embodiment of the present invention.
FIG. The logic processing circuit 54 in FIG. 8 is the same as the logic processing circuit 50 in FIG. 1 except that a power supply control unit 55 that cuts or adjusts the power supplied to the latch block LT is provided.

The power supply control unit 55 includes a P-channel MOSFE
It includes T and N channel MOSFETs, and controls supply of power to the latch block LT based on a power control signal SC.

As described above, by providing power supply control unit 55, for example, inactive latch block LT
Is cut off by the power supply control unit 55,
Power consumption can be reduced. In this case, even if the power supplied to the latch block LT is cut off, the polarization state of the ferroelectric transistor included in the inverter circuit INV2 is maintained, and when the power supply is restarted with the restart of the operation, the polarization state is adjusted. A signal can be provided on line 104.

FIG. 9 shows a logic processing circuit 56 used in a semiconductor device according to still another embodiment of the present invention.
FIG. The logic processing circuit 56 of FIG.
08 and the inverter circuit I inserted in the line 108
8 is the same as the logic processing circuit 54 in FIG. 8 except that a transmission gate GT3, which is a storage unit gate for disconnecting from the NV2, is provided, and the transmission gate GT3 is operated in response to a change in the power supply voltage. is there.

When the low voltage detecting section 84 detects a decrease in the power supply voltage, the transmission gate GT3 is turned off.
F is set. With this configuration, the inverter circuit INV2 is inadvertently caused by a decrease in the power supply voltage.
Can be prevented from changing the polarization state of the ferroelectric transistor constituting the semiconductor device.

In this embodiment, the low voltage detector 8
4, when only the transmission gate GT3 is turned off when a decrease in the power supply voltage is detected, other transmission gates, for example, the transmission gate GT2, may also be turned off at the same time.

In this embodiment, the transmission gate GT3 is connected to the normal clock pulse Cp.
And is turned on / off at the same timing as the transmission gate GT2. Therefore, the transmission gate GT3 is not only a storage gate but also a feedback gate.

FIG. 10 shows a logic processing circuit 5 used in a semiconductor device according to still another embodiment of the present invention.
8 is a circuit diagram. The logic processing circuit 58 of FIG.
Is not provided with the transmission gate GT1 and the transmission gate GT2, and is further provided with two combinational logic blocks.

Combination logic block CB1 and combination logic block CB2 receive input data IN (for example, A,
B, C, and D) are subjected to a predetermined logical operation or the like, and an operation result OUT1 and an operation result OUT2
Is output.

Operation result OU of combinational logic block CB1
T1 is connected to the inverter circuit INV1 via the line 104.
And the output of the inverter circuit INV1 becomes the output Q of the latch block LT. The operation result OUT2 of the combinational logic block CB2 is input to the input side of the inverter circuit INV2 via the line 105.

The operation result OUT1 and the operation result OUT
The relationship with 2 is not particularly limited. For example, the combinational logic block CB1 and the combinational logic block CB2 can be set so that the operation result OUT1 and the operation result OUT2 have a complementary relationship.

As described above, this logic processing circuit 58
Unlike the logic processing circuit 52 shown in FIG. 7, the transmission gate GT1 and the transmission gate GT
However, the combinational logic block CB1 and the combinational logic block CB2 have the same function as the transmission gate. The other configuration is the same as that of the logic processing circuit 52 shown in FIG.

In the case of the logic processing circuit 58, as in the above embodiments, at least one of the four transistors constituting the inverter circuits INV1 and INV2 should be a ferroelectric transistor. . The operating speed can be increased as the number of ferroelectric transistors used in the inverter circuits INV1 and INV2 is reduced.

FIG. 11 shows a logic processing circuit 6 used in a semiconductor device according to still another embodiment of the present invention.
0 shows a circuit diagram. The latch block LT configuring the logic processing circuit 60 in FIG. 11 is for latching data on the bus line.

An annular signal path including a line 106 serving as a main signal path and a line 108 serving as a feedback signal path is formed in a part of the bus line BUS1 serving as a signal path.

An inverter circuit INV1 is inserted into the line 106, and the input side of the inverter circuit and a power supply potential Vdd as a predetermined reference potential are connected to a transistor PT as a switching circuit having a control gate electrode CG as a control input terminal. Through the connection.

Further, the output side of the inverter circuit INV1 and the control gate electrode CG are connected by a line 108 constituting a feedback signal path. In this embodiment, the inverter circuit INV1
Is a CMOS inverter circuit using a normal MOSFET, and the transistor PT is a ferroelectric transistor. Therefore, the transistor PT corresponds to a ferroelectric part.

The bus line BUS1 is precharged to “H” (power supply potential Vdd) by a precharge signal PC generated at a predetermined timing, and thereafter, the “H” state is maintained by the transistor PT.

The logic processing circuit 60 includes a number of combinational logic blocks CB1, CB2,..., And the operation result OUT from each of the combinational logic blocks CB1, CB2,.
1, OUT2,...
L "(ground potential Vss). In this manner, the operation result OUT from each of the combinational logic blocks CB1, CB2,.
, OUT2,... Can be output to the bus line BUS1.

As described above, in the logic processing circuit 60, the transistor PT is a ferroelectric transistor. Therefore, the state of the bus line BUS1, that is, the signal on the bus line BUS1 is stored in the transistor PT in a polarization state corresponding to the signal. Therefore, even if the power is cut off, the bus line BUS
1 can be held, and when the power is restored, the signal is reproduced on the bus line.

In this embodiment, the inverter circuit INV1 included in the latch block LT is connected to a normal MOS transistor.
Although the signal transmission speed is increased by using an FET, the logic processing circuit 62 used in a semiconductor device according to still another embodiment of the present invention shown in FIG.
As described above, the inverter circuit INV1 can be configured using ferroelectric transistors.

The other configuration of the logic processing circuit 62 shown in FIG. 12 is the same as that of the logic processing circuit 60 shown in FIG. In the logic processing circuit 62 shown in FIG. 12, the transistor PT may be a normal P-channel MOSFET instead of a ferroelectric transistor.

FIG. 14 shows a logic processing circuit 6 used in a semiconductor device according to still another embodiment of the present invention.
4 is a circuit diagram. The logic processing circuit 64 includes a combinational logic block C
B and a latch block LT as a signal holding circuit.

The combinational logic block CB is composed of a NAND circuit, an OR circuit, etc.
A predetermined logical operation or the like is performed on (for example, four inputs of A, B, C, and D), and an operation result OUT (and its inverted output) is output.

The latch block LT has a line 104 forming a signal path for transmitting the operation result OUT.
A transistor TR1 which is an input side gate that performs a switching operation based on a clock pulse Cp that is a predetermined gate control signal, and a transistor that is an output side gate that performs a switching operation reverse to the transistor TR1 based on the clock pulse Cp. TR2 is inserted in line 104 in series.

One end of a ferroelectric capacitor C1, which is a ferroelectric memory, is connected to a transistor TR1 and a transistor TR1.
2 and a clock pulse C at the other end of the ferroelectric capacitor C1.
The voltage synchronized with p is applied by the plate line PL.

The line 10 is connected via the transistor TR2.
4 and the bus line BUS1.
Therefore, the operation result OUT is determined by the transistors TR1,
The signal is transmitted to the bus line BUS1 via the transistor TR2.

The ferroelectric capacitor C1 is formed such that a ferroelectric layer made of PZT or the like is sandwiched between two electrodes. The ferroelectric capacitor C1, as described later, holds a polarization state corresponding to the operation result OUT.

The signal path for transmitting the inverted output of the operation result OUT has the same configuration as the signal path for transmitting the operation result OUT. Therefore, the line 105 forming the signal path for transmitting the inverted output of the operation result OUT is coupled to the bus line BUS2 via the transistor TR4.

A precharge circuit PCC and a sense amplifier SA are connected to the pair of bus lines BUS1 and BUS2. Note that a pair of bus lines BUS1, B
A load capacitance C is connected between US2 and the ground potential.
3, C4 is assumed to exist.

With this configuration, the latch block L that can be connected to the pair of bus lines BUS1 and BUS2
T can be easily realized. Further, even when the power is cut off, the operation result OUT (and its inverted output) can be held.

The operation of the latch block LT forming the logic processing circuit 64 will be described with reference to the timing chart shown in FIG. For convenience of explanation, the latch block L
The following description focuses on the signal path for transmitting the operation result OUT among T.

When the clock pulse Cp is "H" (see FIG. 1)
5, (a)), the transistor TR1 is turned on,
The transistor TR2 is off.

In this state, a predetermined voltage synchronized with the clock pulse Cp is applied to the plate line PL (FIG. 1).
5, (b)). Thereby, the ferroelectric capacitor C
The polarization state of 1 is calculated based on the calculation result OUT (in the example of FIG. 15, “
H "(see FIGS. 15 and (c)) (see FIGS. 15 and (d)). On the other hand, the precharge circuit PCC is turned on in synchronization with the clock pulse Cp (see FIGS. 15 and 15).
(E)). As a result, the load capacitance C3 is precharged to the ground potential.

Next, when the clock pulse Cp becomes "L" (see FIG. 15, (f)), the transistor TR1 is turned off.
It becomes FF, and the transistor TR2 turns on.

In this state, a predetermined voltage synchronized with the clock pulse Cp is applied to the plate line PL again (see FIG. 15, (g)). Thereby, the voltage corresponding to the polarization state of the ferroelectric capacitor C1 is changed to the bus line BU.
It appears in S1 (see FIG. 15, (h)).

Thereafter, in synchronization with the clock pulse Cp,
The sense amplifier SA is turned on (see FIG. 15, (i)). The sense amplifier SA operates at a voltage corresponding to the polarization state of the ferroelectric capacitor C1 (see FIG. 15, (h)).
And a voltage (not shown) corresponding to the polarization state of the ferroelectric capacitor C2, and raises the potential of the bus line BUS1 to a predetermined logic level (in this case, "H") (FIG. 15, (See (j)) (or pull down to "L"). With the potential of the bus line BUS1 at a predetermined logic level, the output Q is detected in synchronization with the clock pulse Cp (see FIG. 15, (k)).

In this way, the operation result OUT is latched and output at a predetermined timing. The inverted output of the operation result OUT is processed in the same manner as the operation result OUT.

As described above, this latch block LT
Retains data even when the power is turned off. Therefore, when the power is restored, the held data can be read out to the latch block LT by the same operation as the above-described operation at the time of reading.

The data write operation and the data read operation will be described focusing on the polarization state of the ferroelectric capacitor C1. For convenience of description, a signal path of the latch block LT that transmits the operation result OUT will be described.

FIG. 16 is a circuit diagram showing a portion of the latch block LT corresponding to the signal path for transmitting the operation result OUT in the vicinity of the ferroelectric capacitor C1 and the load capacitance C3. FIG. 17 shows a voltage (potential of the line 104 when the plate line PL shown in FIG. 16 is set as a reference potential) and a polarization state (in FIG. 17, "charge" equivalent to the "polarization state") with respect to the ferroelectric capacitor C1. (History curve) (voltage-charge characteristic) showing the relationship between the two.

In FIG. 17, the state in which remanent polarization Z1 occurs is referred to as polarization state P1, and the state in which remanent polarization Z2 occurs is referred to as polarization state P2.

As described above, at the time of writing (when the clock pulse Cp is “H” (see FIG. 15A)), the transistor TR1 is turned on and the transistor TR2 is turned off.
It is F. At the time of writing, a predetermined voltage synchronized with the clock pulse Cp is applied to the plate line PL (see FIG. 15B), but in the example of FIG. 15, when the voltage applied to the plate line falls. Then, data is written to the ferroelectric capacitor C1. FIG.
6 shows the state of the signal near the ferroelectric capacitor C1 and the load capacitance C3 at this time.

At this time, as shown in FIG. 16, the "H" potential is given to one end (line 104) of the ferroelectric capacitor C1 by the operation result OUT (data "H" in this example). The "L" potential is applied to the other end (plate line PL) of the ferroelectric capacitor C1.

Thus, the ferroelectric capacitor C1 is charged together with the load capacitance C3. At this time, the ferroelectric capacitor C1 exhibits the polarization state P3 shown in FIG.

Next, at the time of reading (clock pulse Cp
Is "L" (see FIG. 15, (f)), the transistor TR1 is turned off, and the transistor TR2 is turned off.
Turns ON. As a result, the polarization state of the ferroelectric capacitor C1 starts to shift from P3 to P1.

At the time of reading, the clock pulse Cp
Is applied to the plate line PL (see FIG. 15 (g)), a voltage corresponding to the polarization state of the ferroelectric capacitor C1 is applied to the line 104 and the bus line BUS1 connected to the line 104. (See FIG. 15, (h)) V1 occurs.

The polarization state of ferroelectric capacitor C1 at this time is represented by point P6 in FIG. This voltage V1
And a line 105 coupled to one end of the other ferroelectric capacitor C2 and a bus line B connected thereto.
As described above, the potential of the bus line BUS1 is raised to a predetermined logic level (in this case, “H”) based on the difference from the voltage of US2 (see FIG. 15, (j)). In this state, the output Q is read as described above.

FIG. 18 shows a logic processing circuit 6 used in a semiconductor device according to still another embodiment of the present invention.
6 is a circuit diagram. The logic processing circuit 66 of FIG. 18 operates the transistors TR1, TR2, TR3, and TR4 in response to the fluctuation of the power supply voltage,
4 is similar to the logic processing circuit 54.

When the low voltage detecting section 84 detects a drop in the power supply voltage, the transistors TR1, TR2, TR3
TR4 is set to be all OFF. In this way, it is possible to prevent the polarization states of the ferroelectric capacitors C1 and C2 from being changed carelessly due to a decrease in the power supply voltage. That is, in this embodiment, the transistors TR1, TR2, TR3,
TR4 is also a storage unit gate.

Next, FIG. 19A is a circuit diagram showing an example of a combinational logic block CB constituting various logic processing circuits used in the semiconductor device according to each embodiment of the present invention. FIG. 19B illustrates the combinational logic block CB using logic gates.

The circuit shown in FIG. 19A is one of the power-saving logic blocks CB, and includes a power control unit 110. The power control unit 110 includes an N-channel MOSFET, and controls supply of power to the combinational logic block CB based on the power control signal SC.

By providing power supply control unit 110 as described above, for example, power supply to inactive combinational logic block CB is cut off by power supply control unit 110, so that power consumption can be suppressed.

FIG. 20 is a circuit diagram showing another example of the combinational logic block CB constituting various logic processing circuits used in the semiconductor device according to each embodiment of the present invention.

The circuit shown in FIG. 20 is one of the power-saving logic blocks CB, and is a circuit configured using a circuit configuration method called path logic. With this circuit configuration method, the number of elements can be significantly reduced.

FIG. 21A is a truth table corresponding to the circuit shown in FIG. FIG. 21B illustrates the truth table using logic gates. FIG. 22 corresponds to FIG.
This is an example of a case where a circuit corresponding to the truth table shown in FIG.

It can be seen that the number of elements of the circuit (10 elements) shown in FIG. 20 is considerably smaller than that of the circuit (22 elements) formed by using the conventional CMOS configuration method shown in FIG. This is because in the conventional CMOS configuration method,
While only the two terminals (drain and gate) of the FET are used as the logic processing path, in the circuit configuration method called path logic, F is used as the logic processing path.
This is because the three terminals (source, drain and gate) of ET are fully utilized.

As described above, the power consumption can be reduced by reducing the number of elements constituting the logic block CB.

Next, FIG. 25 is a block diagram showing an example of an IC card using the semiconductor device according to each embodiment of the present invention. The IC card is used as a credit card, an identification tag used in a distribution process, or the like.
IC cards include contact type IC cards and non-contact type IC cards.
Card, but here, a non-contact type IC card 7
0 will be described as an example.

The IC card 70 includes an antenna section 72, an analog processing section 74, a digital processing section 76, and a memory section 78. The IC card 70 is configured to supply electric power and send and receive data using radio waves via an ID number reader 102 connected to the host computer 100.

The analog section 74 includes a rectifying section 80, a power supply section 82, a low voltage detecting section 84, a detecting section 86, and a waveform shaping section 8.
8 and a modulation unit 90. Digital section 76
Includes an encoder 92, a protocol controller 94, a decoder 96, and a memory interface 98.

The memory section 78 is configured using a ferroelectric memory circuit using a ferroelectric transistor or a ferroelectric capacitor. Therefore, a power source is not required for data retention, the writing speed is high, and a high voltage is not required. Therefore, the present invention is suitable for use in such a non-contact IC card 70.

The radio wave input to the antenna unit 72 is rectified by the rectification unit 80 and then sent to the power supply unit 82,
The power of the card 70 is used. The low voltage detector 84 detects a drop in the power supply voltage. As described above, for example, transmission gate GT3 (see FIG. 9) is cut off based on the output of low-voltage detector 84.

The radio wave input to the antenna unit 72 is detected by the detection unit 86, and then is detected by the waveform shaping unit 8.
At 8, the waveform is trimmed.

The output of the waveform shaping section 88 is decoded by the encoder 92 based on an instruction from the protocol controller 94, and is stored in the memory section 78 via the memory interface 98, if necessary, based on the decoded information. Write and read for the written data.

[0201] The decoder 96 decodes data read from the memory unit 78 and sends the data to the modulation unit 90 based on an instruction from the protocol controller 94. Modulation unit 90
After modulating this data,
Output as radio waves.

[0202] The host computer 100 reads the data on the radio wave via the ID number reader 102.
In this manner, data is exchanged between the host computer 100 and the IC card 70.

The semiconductor device according to each of the above embodiments is used, for example, to configure the digital section 76 of the IC card 70. When the digital unit 76 is configured by a microprocessor, the semiconductor device according to each of the above embodiments can be used as a sequence logic processing circuit of the microprocessor.

Further, the digital section 76 has a logic LS
In the case of using I, the semiconductor device according to each of the above embodiments can be used as a sequence logic processing circuit of a logic LSI.

As the logic LSI, a dedicated LSI can be used, but it can also be configured using a general-purpose gate array. In this case, as a general-purpose gate array, a gate array including a transistor such as an FET and a ferroelectric element such as a ferroelectric transistor or a ferroelectric capacitor may be used.

In this embodiment, a non-contact type IC card has been described as an example of an IC card using a semiconductor device. However, an IC card using a semiconductor device to which the present invention is applied is not limited to this. It is not limited. For example, the present invention can be applied to a contact type IC card, a contact type / non-contact type IC card, and the like.

Further, the semiconductor device according to the present invention comprises an IC
It is not limited to those applied to cards. F
PGA (Field Programmable Gate Array), D
The present invention is generally applied to semiconductor devices such as various gate arrays such as PGA (dynamic programmable gate array), computer hardware such as dedicated LSIs and microprocessors, and the like.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a logic processing circuit 50 used in a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of a latch block LT of a logic processing circuit 50;

FIG. 3A is a cross-sectional view illustrating a structure of a transistor NT. FIG. 3B is a drawing in which the transistor NT is represented by a symbol.

FIG. 4 is a diagram showing a state of an inverter circuit INV2 at the time of rising of a clock pulse Cp.

5 is a diagram showing an example of a ferroelectric capacitor C _ferro and the MOS capacitor C _MOS voltage-charge characteristic of the transistor NT when writing data "H".

6 is a view showing a ferroelectric capacitor C _ferro and the MOS capacitor C _MOS voltage-charge characteristic of the transistor PT in the case of writing data "H".

FIG. 7 is a circuit diagram showing a logic processing circuit 52 used in a semiconductor device according to another embodiment of the present invention.

FIG. 8 is a circuit diagram showing a logic processing circuit used in a semiconductor device according to still another embodiment of the present invention.

FIG. 9 is a circuit diagram showing a logic processing circuit 56 used in a semiconductor device according to still another embodiment of the present invention.

FIG. 10 is a circuit diagram showing a logic processing circuit 58 used in a semiconductor device according to still another embodiment of the present invention.

FIG. 11 is a circuit diagram showing a logic processing circuit 60 used in a semiconductor device according to still another embodiment of the present invention.

FIG. 12 is a circuit diagram showing a logic processing circuit 62 used in a semiconductor device according to still another embodiment of the present invention.

FIG. 13A is a drawing showing another example of the structure of the transistor NT. FIG. 13B is a drawing in which the transistor NT of FIG. 13A is represented by a symbol.

FIG. 14 is a circuit diagram showing a logic processing circuit 64 used in a semiconductor device according to still another embodiment of the present invention.

FIG. 15 is a timing chart illustrating an operation of a latch block LT included in the logic processing circuit 64.

FIG. 16 shows a ferroelectric capacitor C1 and a load capacitance C3.
It is a circuit diagram of a vicinity.

FIG. 17 is a hysteresis curve showing a relationship between a voltage and a polarization state of the ferroelectric capacitor C1.

FIG. 18 is a circuit diagram showing a logic processing circuit 66 used in a semiconductor device according to still another embodiment of the present invention.

FIG. 19A is a circuit diagram illustrating an example of a combinational logic block CB that forms various logic processing circuits used in the semiconductor device according to each embodiment of the present invention; FIG. 19B is a drawing in which the combinational logic block CB is expressed using logic gates.

FIG. 20 is a circuit diagram showing another example of the combinational logic block CB constituting various logic processing circuits used in the semiconductor device according to each embodiment of the present invention;

FIG. 21A is a truth table corresponding to the path logic circuit shown in FIG. 20; FIG. 21B shows the truth table,
It is a drawing expressed using a CMOS logic gate.

FIG. 22 shows a circuit corresponding to the truth table shown in FIG. 21A,
It is a figure showing an example at the time of constituted using the conventional CMOS composition method.

FIG. 23 is a circuit diagram showing a logic processing circuit 112 used in a semiconductor device according to still another embodiment of the present invention.

24 is a timing chart illustrating an operation of the flip-flop circuit FF illustrated in FIG.

FIG. 25 is a block diagram illustrating an example of an IC card using the semiconductor device according to each embodiment of the present invention.

FIG. 26 is a block diagram showing a conventional logic processing circuit 2.

FIG. 27 is a drawing illustrating an example of a specific circuit of a conventional logic processing circuit 2 including a power-saving latch block LT.

[Explanation of symbols]

 55 Power supply control unit 56 Logic processing circuit 104 Line 106 Line 108 Line CB Combination logic block INV2 Inverter Circuit LT Latch block

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 H01L 29/78 371 H03K 17/24 19/003

Claims (22)

[Claims] 1. A signal holding circuit for holding a signal for a predetermined period, comprising: a signal path for transmitting the signal; and a polarization state corresponding to the signal appearing on the signal path during operation, which is coupled to the signal path. And a ferroelectric storage unit for restoring a signal to a signal path at the time of operation return based on the held polarization state. 2. The signal holding circuit according to claim 1, wherein an annular signal path having a main signal path and a feedback signal path is provided in a part of the signal path, and at least one of the main signal path and the feedback signal path is provided. The ferroelectric storage unit is combined. 3. The signal holding circuit according to claim 2, wherein a ferroelectric transistor is used as said ferroelectric storage unit. 4. The signal holding circuit according to claim 3, wherein the ferroelectric transistor comprises: A) a first conductivity type source region and a drain region formed on a semiconductor substrate; and B) a region between the source region and the drain region. The second placed in
A channel forming region of a conductivity type; C) an insulating layer disposed on the channel forming region; D) a first conductor layer disposed on the insulating layer; E) on the first conductor layer. And F) a second conductor layer formed on the ferroelectric layer. 5. The signal holding circuit according to claim 3, wherein an inverter circuit is inserted into each of the main signal path and the feedback signal path, and at least one of the inverter circuits is connected to the ferroelectric circuit. A ferroelectric storage unit using a body transistor. 6. The signal holding circuit according to claim 2, wherein an input side of said signal path, on an input side of said annular signal path, performs a disconnection operation on said signal path based on a predetermined gate control signal. A gate is provided. 7. The signal holding circuit according to claim 3, wherein an inverter circuit is inserted into the main signal path, and an input side of the inverter circuit and a predetermined reference potential are connected to a control input terminal. And an output side of the inverter circuit and the control input terminal,
Coupling with the feedback signal path, and at least one of the inverter circuit and the switching circuit is a ferroelectric storage unit using the ferroelectric transistor. 8. The signal holding circuit according to claim 2, wherein said ferroelectric storage section is provided only in a feedback signal path. 9. A signal holding circuit according to claim 2, wherein a signal is transmitted via a main signal path, a feedback signal path is interrupted, and a signal is fed back via the feedback signal path. A feedback gate for connecting a feedback signal path is provided. 10. The signal holding circuit according to claim 1, wherein a ferroelectric capacitor is used as said ferroelectric storage unit. 11. The signal holding circuit according to claim 10, wherein an input side gate that performs a switching operation based on a predetermined gate control signal, and a reverse switching operation opposite to the input side gate is performed based on the gate control signal. An output-side gate is inserted in series with the signal path, and one end of the ferroelectric capacitor is coupled to the signal path between an input-side gate and an output-side gate. An end configured to apply a voltage synchronized with the gate control signal. 12. The signal holding circuit according to claim 1, further comprising: a memory gate for disconnecting the signal path from the ferroelectric memory. 13. The signal holding circuit according to claim 12, wherein the storage section gate disconnects the signal path from the ferroelectric storage section in response to a change in power supply voltage. . 14. A signal holding circuit according to claim 1, further comprising a power supply control unit for cutting off or adjusting the power supplied to said signal holding circuit. 15. The signal holding circuit according to claim 1, wherein said signal holding circuit is connected to a combinational circuit via said signal path. 16. The signal holding circuit according to claim 15, wherein said combination circuit is a power saving circuit. 17. A semiconductor device using the signal holding circuit according to claim 15 and said combination circuit connected to said holding circuit. 18. The semiconductor device according to claim 17, further comprising a ferroelectric memory circuit. 19. The semiconductor device according to claim 17, wherein said semiconductor device is a microcomputer. 20. The semiconductor device according to claim 17, wherein said semiconductor device is configured using a gate array. 21. A gate array for use in the semiconductor device according to claim 20, comprising: a transistor; and an element made of a ferroelectric substance. 22. An IC card using the semiconductor device according to claim 17.