CN113938126B - Voltage latching type level conversion circuit - Google Patents
Voltage latching type level conversion circuit Download PDFInfo
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- CN113938126B CN113938126B CN202111241106.7A CN202111241106A CN113938126B CN 113938126 B CN113938126 B CN 113938126B CN 202111241106 A CN202111241106 A CN 202111241106A CN 113938126 B CN113938126 B CN 113938126B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a voltage latch type level conversion circuit, which belongs to the field of integrated circuits and comprises an inverter taking a power supply 1 as a voltage source, a level conversion unit taking a power supply 2 as the voltage source and an output buffer taking the power supply 2 as the voltage source; the inverter provides a set of inverted signals to the level shifting unit; the level conversion unit receives an input reverse signal and realizes conversion of different voltage domains through a voltage latching mode, and the output buffer realizes shaping of an output signal and improves driving capability of a lower stage. The invention is suitable for 1.8V-5V bidirectional level conversion under 1Gbps, and can control the voltage latch function of the level conversion circuit through the enabling signal, and the transmission delay is lower than 200p seconds; compared with the conventional level conversion and latch series connection, the invention has the advantages of smaller transmission delay, smaller dynamic power consumption, wider voltage domain range, higher transmission rate and less total MOS transistors.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a voltage latch type level shifter circuit.
Background
Bus interface circuits are highly versatile, whether on-chip or board-card circuits, and the functionality of such circuits is indispensable in order to match the operating conditions of the system under various conditions. The level conversion circuit is an IO interface circuit which is very popular in application, and is generally used in a system powered by multiple power supplies. In order to meet the power supply conditions of each functional module, the level conversion circuit can realize the conversion function of different voltage sources under the condition of extremely small drain electrode so as to match the power supply requirements of different modules.
The traditional level conversion circuit is mainly divided into 2 types, one type is the level conversion circuit shown in fig. 1, the level conversion circuit has a simple structure, full-amplitude voltage is output, and the level conversion function is completed on the premise of small electric leakage by controlling the switching sequence of NMOS transistors N12 and N13 and PMOS transistors P12 and P13. However, the limit frequency of the circuit can only reach about 400Mbps, because the design of the structure determines that the edge of the voltage inversion cannot be raised or lowered instantaneously, and the transmission delay of the circuit structure is higher than the sum of the delays of the 3-stage inverters. At present, the full-width level conversion chip mostly adopts the level conversion circuit under the condition of no special requirement and no speed limit.
The second type is a level conversion circuit of a current mirror load, and fig. 2 shows a level conversion circuit of a wilson current mirror, which is characterized in that a differential comparator is implemented through the current mirror load to further implement a level conversion function, and has the disadvantages that output cannot reach full width, input power supply voltage is limited by the working states of the NMOS transistors N22 and N23, and when the frequency is higher, in order to ensure that the differential circuit works in a large signal mode, the input power supply cannot be too small.
Disclosure of Invention
The invention aims to provide a voltage latching type level conversion circuit which is used for solving the problems in the background technology.
In order to solve the technical problems, the invention provides a voltage latch type level conversion circuit, which comprises an inverter, a level conversion unit and an output buffer;
the inverter provides a set of inverted signals to the level shifting unit;
the level conversion unit receives an input reverse signal and realizes conversion of different voltage domains in a voltage latching mode;
the output buffer shapes the output signal and improves the driving capability of the lower stage.
Optionally, the inverter includes a PMOS transistor P41 and an NMOS transistor N41; wherein,,
the grid end of the PMOS tube P41 is connected with an input pressure welding spot IN, the source end is connected with a power supply voltage VDDIN, and the substrate is connected with the power supply voltage VDDIN;
the gate end of the NMOS tube N41 is connected with an input pressure welding spot IN, and the source end and the substrate are both connected with GND;
the drain end of the PMOS tube P41 is connected with the drain end of the NMOS tube N41 to form the output end of the inverter.
Optionally, the level conversion unit includes PMOS transistors P42, P43, P44, P45, P46, P47, P48, and NMOS transistors N42, N43, N44, N45, N48; wherein,,
the gate end of the PMOS tube P42 is connected with the output end of the inverter, and is simultaneously connected with the gate end of the PMOS tube P46 and the gate end of the NMOS tube N42; the source end and the substrate of the PMOS tube P42 are both connected with the power supply voltage VDDOUT, and the drain end is simultaneously connected with the source ends of the PMOS tubes P44 and P45 and the drain ends of the PMOS tubes P43 and P48;
the gate end of the PMOS tube P43 is connected with an input pressure welding spot IN and the gate ends of the PMOS tubes P45 and P47 and the NMOS tube N43; the source end and the substrate of the PMOS tube P43 are both connected with the power supply voltage VDDOUT, and the drain end is simultaneously connected with the source ends of the PMOS tubes P44 and P45 and the drain ends of the PMOS tubes P42 and P48;
the gate end of the PMOS tube P44 is connected with the input end of the output buffer and is simultaneously connected with the gate end of the NMOS tube N44, the drain ends of the N43 and N45 and the drain end of the P47; the source end of the PMOS tube P44 is connected with the drain ends of the P42, the P43 and the P48 and the source end of the P45, the drain end of the PMOS tube P44 is connected with the source end of the P46, and the substrate is connected with the VDDOUT;
the gate end of the PMOS tube P45 is connected with the gate end of the NMOS tube N45, the drain end of the N42, the drain end of the N44 and the drain end of the P46, the source end of the PMOS tube P45 is connected with the drain end of the P42, the drain end of the P43, the drain end of the P48 and the source end of the P44, the drain end of the PMOS tube P45 is connected with the source end of the P47, and the substrate is connected with the VDDOUT;
the gate end of the PMOS tube P46 is connected with the output end of the inverter and is simultaneously connected with the gate ends of the P42 and the N42, the source end of the PMOS tube P46 and the substrate are both connected with the drain end of the P44, and the drain end of the PMOS tube P46 is connected with the drain end of the N42, the drain end of the N44, the gate end of the P45 and the gate end of the N45;
the gate end of the PMOS tube P47 is connected with the input press welding point IN and is connected with the gate end of the P43 and the gate end of the N43, and the drain end of the PMOS tube P47 and the substrate are both connected with the drain end of the P45; the drain end of the PMOS tube P47 is connected with the input end of the output buffer and is connected with the drain end of the N43, the drain end of the N45, the gate end of the P44 and the gate end of the N44;
the gate end of the NMOS tube N42 is connected with the output end of the input inverter and is connected with the gate end of the P42 and the gate end of the P46, the source end and the substrate are both connected with GND, and the drain end of the NMOS tube N42 is connected with the drain end of the N44, the drain end of the P46, the gate end of the P45 and the gate end of the N45;
the gate end of the NMOS tube N43 is connected with an input press welding spot IN and is simultaneously connected with the gate end of the P43 and the gate end of the P47, the source end of the NMOS tube N43 is connected with the substrate and the GND, the drain end of the NMOS tube N43 is connected with the input end of the output buffer and is simultaneously connected with the drain end of the N45, the drain end of the P47, the gate end of the P44 and the gate end of the N44;
the gate end of the NMOS tube N44 is connected with the input end of the output buffer and is simultaneously connected with the drain end of the N43, the drain end of the N45, the drain end of the P47 and the gate end of the P4, the source end and the substrate are both connected with GND, and the drain end of the NMOS tube N44 is connected with the drain end of the N42, the drain end of the P46, the gate end of the P45 and the gate end of the N45;
the gate end of the NMOS tube N45 is connected with the drain end of the N42, the drain end of the N44, the drain end of the P46 and the gate end of the P45, and the source end and the substrate are connected with GND; the drain end of the NMOS tube N45 is connected with the input end of the output buffer, and is connected with the drain end of the N43, the drain end of the P47, the gate end of the P44 and the gate end of the N44;
the gate end of the NMOS tube N48 is connected with a pressing welding point EN and is connected with the gate end of the P48, the source end and the substrate are both connected with GND, and the drain end of the NMOS tube N48 is connected with the source end of the N42 and the source end of the N43; the gate end of the PMOS tube P48 is connected with the pressure welding point EN and is connected with the gate end of the N48, the source end and the substrate are both connected with VDDOUT, and the drain end of the PMOS tube P48 is connected with the drain end of the P42, the drain end of the P43, the source end of the P44 and the source end of the P45.
Optionally, the output buffer includes a PMOS transistor P49 and an NMOS transistor N49; wherein,,
the gate end of the PMOS tube P49 is simultaneously connected with the drain end of the P47, the drain end of the N43, the drain end of the N45, the gate end of the P44 and the gate end of the N44; the source end of the PMOS tube P49 is connected with the substrate by the power supply voltage VDDOUT, the drain end is connected with the output pressure welding point OUT, and the source end is connected with the drain end of the N49;
the gate end of the NMOS tube N49 is simultaneously connected with the drain end of the P47, the drain end of the N43, the drain end of the N45, the gate end of the P44 and the gate end of the N44; the source end of the NMOS tube N49 is connected with the substrate GND, the drain end of the NMOS tube N49 is connected with the output pressure welding point OUT, and the drain end of the NMOS tube N49 is connected with the drain end of the PMOS tube P49.
The invention provides a voltage latch type level conversion circuit, which comprises an inverter taking a power supply 1 as a voltage source, a level conversion unit taking a power supply 2 as the voltage source and an output buffer taking the power supply 2 as the voltage source; the inverter provides a set of inverted signals to the level shifting unit; the level shift unit outputs the buffer. The invention is suitable for 1.8V-5V bidirectional level conversion under 1Gbps, and can control the voltage latch function of the level conversion circuit through the enabling signal, and the transmission delay is lower than 200p seconds; compared with the conventional level conversion and latch series connection, the invention has the advantages of smaller transmission delay, smaller dynamic power consumption, wider voltage domain range, higher transmission rate and less total MOS transistors.
Drawings
FIG. 1 is a schematic diagram of a conventional full-width level shift circuit;
FIG. 2 is a schematic diagram of a level shift circuit based on a current mirror;
FIG. 3 is a schematic block diagram of a voltage latch type level shifter circuit provided by the present invention;
FIG. 4 is a schematic diagram of a voltage latch type level shifter circuit according to the present invention;
FIG. 5 is a schematic diagram of the voltage latch type level shifter circuit of the present invention operating at 1Gbps for input/output and transmission delay.
Detailed Description
The voltage latch type level shifter circuit according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a voltage latch type level conversion circuit, the principle of which is shown in figure 3, comprising an inverter taking a power supply 1 as a voltage source, a level conversion unit taking a power supply 2 as the voltage source and an output buffer taking the power supply 2 as the voltage source; the inverter provides a set of inverted signals to the level shifting unit; the level conversion unit receives an input reverse signal and realizes conversion of different voltage domains through a voltage latching mode, and the output buffer realizes shaping of an output signal and improves driving capability of a lower stage.
Referring to fig. 4, the inverter includes a PMOS transistor P41 and an NMOS transistor N41; the gate of the PMOS tube P41 is connected with an input pressure welding spot IN, the source is connected with a power supply voltage VDDIN, and the substrate is connected with the power supply voltage VDDIN; the gate end of the NMOS tube N41 is connected with an input pressure welding spot IN, and the source end and the substrate are both connected with GND; the drain end of the PMOS tube P41 is connected with the drain end of the NMOS tube N41 to form the output end of the inverter.
The level conversion unit comprises PMOS (P-channel metal oxide semiconductor) transistors P42, P43, P44, P45, P46, P47 and P48, and NMOS (N-channel metal oxide semiconductor) transistors N42, N43, N44, N45 and N48; the NMOS transistors N42, N43, N44 and N45 are also middle threshold transistors, and have smaller starting voltage and larger current driving capability; under the working state, the switching states of the NMOS transistors N2 and N3 are opposite in direction and same in time delay. The gate end of the PMOS tube P42 is connected with the output end of the inverter, and is simultaneously connected with the gate end of the PMOS tube P46 and the gate end of the NMOS tube N42; the source end and the substrate of the PMOS tube P42 are both connected with the power supply voltage VDDOUT, and the drain end is simultaneously connected with the source ends of the PMOS tubes P44 and P45 and the drain ends of the PMOS tubes P43 and P48; the gate end of the PMOS tube P43 is connected with an input pressure welding spot IN and the gate ends of the PMOS tubes P45 and P47 and the NMOS tube N43; the source end and the substrate of the PMOS tube P43 are both connected with the power supply voltage VDDOUT, and the drain end is simultaneously connected with the source ends of the PMOS tubes P44 and P45 and the drain ends of the PMOS tubes P42 and P48; the gate end of the PMOS tube P44 is connected with the input end of the output buffer and is simultaneously connected with the gate end of the NMOS tube N44, the drain ends of the N43 and N45 and the drain end of the P47; the source end of the PMOS tube P44 is connected with the drain ends of the P42, the P43 and the P48 and the source end of the P45, the drain end of the PMOS tube P44 is connected with the source end of the P46, and the substrate is connected with the VDDOUT; the gate end of the PMOS tube P45 is connected with the gate end of the NMOS tube N45, the drain end of the N42, the drain end of the N44 and the drain end of the P46, the source end of the PMOS tube P45 is connected with the drain end of the P42, the drain end of the P43, the drain end of the P48 and the source end of the P44, the drain end of the PMOS tube P45 is connected with the source end of the P47, and the substrate is connected with the VDDOUT; the gate end of the PMOS tube P46 is connected with the output end of the inverter and is simultaneously connected with the gate ends of the P42 and the N42, the source end of the PMOS tube P46 and the substrate are both connected with the drain end of the P44, and the drain end of the PMOS tube P46 is connected with the drain end of the N42, the drain end of the N44, the gate end of the P45 and the gate end of the N45; the gate end of the PMOS tube P47 is connected with the input press welding point IN and is connected with the gate end of the P43 and the gate end of the N43, and the drain end of the PMOS tube P47 and the substrate are both connected with the drain end of the P45; the drain end of the PMOS tube P47 is connected with the input end of the output buffer and is connected with the drain end of the N43, the drain end of the N45, the gate end of the P44 and the gate end of the N44; the gate end of the NMOS tube N42 is connected with the output end of the input inverter and is connected with the gate end of the P42 and the gate end of the P46, the source end and the substrate are both connected with GND, and the drain end of the NMOS tube N42 is connected with the drain end of the N44, the drain end of the P46, the gate end of the P45 and the gate end of the N45; the gate end of the NMOS tube N43 is connected with an input press welding spot IN and is simultaneously connected with the gate end of the P43 and the gate end of the P47, the source end of the NMOS tube N43 is connected with the substrate and the GND, the drain end of the NMOS tube N43 is connected with the input end of the output buffer and is simultaneously connected with the drain end of the N45, the drain end of the P47, the gate end of the P44 and the gate end of the N44; the gate end of the NMOS tube N44 is connected with the input end of the output buffer and is simultaneously connected with the drain end of the N43, the drain end of the N45, the drain end of the P47 and the gate end of the P4, the source end and the substrate are both connected with GND, and the drain end of the NMOS tube N44 is connected with the drain end of the N42, the drain end of the P46, the gate end of the P45 and the gate end of the N45; the gate end of the NMOS tube N45 is connected with the drain end of the N42, the drain end of the N44, the drain end of the P46 and the gate end of the P45, and the source end and the substrate are connected with GND; the drain end of the NMOS tube N45 is connected with the input end of the output buffer, and is connected with the drain end of the N43, the drain end of the P47, the gate end of the P44 and the gate end of the N44; the gate end of the NMOS tube N48 is connected with a pressing welding point EN and is connected with the gate end of the P48, the source end and the substrate are both connected with GND, and the drain end of the NMOS tube N48 is connected with the source end of the N42 and the source end of the N43; the gate end of the PMOS tube P48 is connected with the pressure welding point EN and is connected with the gate end of the N48, the source end and the substrate are both connected with VDDOUT, and the drain end of the PMOS tube P48 is connected with the drain end of the P42, the drain end of the P43, the source end of the P44 and the source end of the P45. The output buffer comprises a PMOS tube P49 and an NMOS tube N49; the gate end of the PMOS tube P49 is simultaneously connected with the drain end of the P47, the drain end of the N43, the drain end of the N45, the gate end of the P44 and the gate end of the N44; the source end of the PMOS tube P49 is connected with the substrate by the power supply voltage VDDOUT, the drain end is connected with the output pressure welding point OUT, and the source end is connected with the drain end of the N49; the gate end of the NMOS tube N49 is simultaneously connected with the drain end of the P47, the drain end of the N43, the drain end of the N45, the gate end of the P44 and the gate end of the N44; the source end of the NMOS tube N49 is connected with the substrate GND, the drain end of the NMOS tube N49 is connected with the output pressure welding point OUT, and the drain end of the NMOS tube N49 is connected with the drain end of the PMOS tube P49.
The level conversion unit has the functions of realizing the conversion from the power supply 1 to the power supply 2, normally operating when being enabled to be turned on, and outputting the last state when being enabled to be turned off; the input-output truth table is as follows:
| EN | IN | OUT | status of |
| 0 | 0 | Is indefinite | Maintaining the last state |
| 0 | 1 | Is indefinite | Maintaining the last state |
| 1 | 0 | 0 | Level shift output 0 |
| 1 | 1 | 1 | Level shift output VDDOUT |
Level conversion function: when the input is high voltage, the input signal outputs a low voltage to the PMOS transistors P42 and P46 and the NMOS transistor N42 through the inverter of the first stage, so that the P42 and P46 are turned on, the N42 is turned off, and the N43 is turned on at the same time, the gate terminal voltage of the PMOS transistor P49 in the output buffer is low, and finally the output is high, namely the output VDDOUT. Meanwhile, since the P42 and P46 are turned on, and the gate terminal of P44 is also turned on due to the fact that the last state was pulled down by N43, the gate terminal voltage of N45 is high, N45 is turned on, and the gate terminal of P44 is further pulled down, and the states of P43, N44, P45 and P47 are all determined to be turned off in this state. Similarly, when the input is low voltage, P42, N43, P44, P46 are turned off, N42, P43, P45, P47 are turned on, the gate voltage of P49 in the output buffer is high, and the final output is low, i.e. output GND.
Synchronous switch theory of operation: when the input voltage is turned from high to low, the middle threshold tube N42 is turned on and N43 is turned off, the P42 and the P46 are turned off instantaneously and simultaneously, the P43 and the P47 are turned on simultaneously, and the on-off states of the P44, the N44, the P45 and the N45 are slower than those of the P42, the P46, the P43 and the P47, so that the existence of the synchronous switch P46 avoids the transient competition risk of the P44 and the N42 and accelerates the pull-down speed of the edge. Similarly, the presence of the synchronous switch P47 avoids a brief contention hazard between P45 and N43 when the voltage is reversed from low to high. The structure greatly reduces the duration of the edge, improves the upper limit of the working frequency of the circuit, and reduces the transmission delay. The substrates of the synchronous switches P46 and P47 are connected with the source end, so that the substrate bias effect is reduced, and the current driving capability is improved.
The enable signal controls the latch function: when the enabling signal is high, the enabling switch tube P48 is turned off, the N48 is turned on, and the level conversion works normally; when enabled low, the level shift unit has a latch function. If the enable signal is turned off when the input pad IN is high, the circuit initial state is that P42, N43, P44, N45, P46 is turned on, the input of the output buffer is low, the output is high, when the input pad IN changes from high to low, N42, P43, P47 is turned on, P42, N43, P46 is turned off, the gate voltage of P44, P45 is not discharged due to the cut-off of N48, the channel is IN an unstable state, the drain terminal of P46 keeps high potential under the condition of no leakage, the voltage loss caused by the leakage can be compensated by the voltage generated at the drain terminal of P46 by coupling the gate terminal signal of P46, N42 from small to large suddenly, so as to ensure that the gate source voltage VGS of the middle threshold tube N45 can be larger than the turn-on voltage VTH thereof, and thus the threshold tube N44, N45 is also expected to have a lower voltage VTH (zero overdrive voltage vgh) IN order to keep the drain terminal of vcp 45 to keep the output of the low voltage v 47, and keep the drain terminal of v 47 from being turned on when the drain terminal of the voltage v 45 is still kept low under the condition. Similarly, when the input pad IN is low, the enable signal is turned off, the circuit is initially turned on by N42, P43, N44, P45, P47, and turned off by P42, N43, P44, N45, P46, the input of the output buffer is high, the output OUT port is low, when the input pad IN changes from low to high, P42, N43, P46 is turned on, N42, P43, P47 is turned off, the gate voltage of P44, P45 is not discharged due to the turn-off of N48, the channel is IN an unstable state, the drain of P47 is kept at a high potential under no leakage condition, and IN fact, P45 is still turned on due to the influence of the previous state, and P48 is IN a normally-open state due to the effect of the pad EN, so that even if P47 has leakage, since both source and drain terminals are at a high potential, the input of the output buffer can be determined to be high, the output OUT port is still low, and the output state before the level conversion unit is kept to be turned off.
The invention can realize the fixed output state under the suspended input, and the circuit at the back can not generate unstable state through the turn-off enable under the condition of the disconnection of the input or the power failure of the input power supply voltage; average power supply leakage does not exceed 2mA under the limiting frequency, static average leakage does not exceed 10nA, and dynamic power consumption is lower than 10mW under the limiting frequency; the power supply voltage can span 1.8V, 3.3V and 5V voltage domains, and meanwhile, 2 modes of high-pass low and low-pass high are supported; the input and the output can be regarded as full-swing power supply voltage; the limit frequency of the level shift unit is limited by the turn-on voltages of the medium threshold transistors N42, N43, N44, N45. The greater the full period duty cycle the more aggressive the output duty cycle the time of the edge. The circuit can normally work at 1Gbps, the input/output and transmission delay conditions at 1Gbps are shown in fig. 5, 1.8V is an input waveform, 5V is an output waveform, the input waveform is excited by excitation, the inflection point is relatively sharp, and the transmission delay condition marked by 68.9P seconds in the figure can be also mentioned.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (2)
1. A voltage latch type level conversion circuit is characterized by comprising an inverter, a level conversion unit and an output buffer;
the inverter provides a set of inverted signals to the level shifting unit;
the level conversion unit receives an input reverse signal and realizes conversion of different voltage domains in a voltage latching mode;
the output buffer realizes shaping for output signals and improves driving capability of lower stages;
the inverter comprises a PMOS tube P41 and an NMOS tube N41; wherein,,
the grid end of the PMOS tube P41 is connected with an input pressure welding spot IN, the source end is connected with a power supply voltage VDDIN, and the substrate is connected with the power supply voltage VDDIN;
the gate end of the NMOS tube N41 is connected with an input pressure welding spot IN, and the source end and the substrate are both connected with GND;
the drain end of the PMOS tube P41 is connected with the drain end of the NMOS tube N41 to form the output end of the inverter;
the level conversion unit comprises PMOS (P-channel metal oxide semiconductor) transistors P42, P43, P44, P45, P46, P47 and P48, and NMOS (N-channel metal oxide semiconductor) transistors N42, N43, N44, N45 and N48; wherein,,
the gate end of the PMOS tube P42 is connected with the output end of the inverter, and is simultaneously connected with the gate end of the PMOS tube P46 and the gate end of the NMOS tube N42; the source end and the substrate of the PMOS tube P42 are both connected with the power supply voltage VDDOUT, and the drain end is simultaneously connected with the source ends of the PMOS tubes P44 and P45 and the drain ends of the PMOS tubes P43 and P48;
the gate end of the PMOS tube P43 is connected with the input pressure welding spot IN and is simultaneously connected with the gate end of the PMOS tube P47 and the gate end of the NMOS tube N43; the source end and the substrate of the PMOS tube P43 are both connected with the power supply voltage VDDOUT, and the drain end is simultaneously connected with the source ends of the PMOS tubes P44 and P45 and the drain ends of the PMOS tubes P42 and P48;
the gate end of the PMOS tube P44 is connected with the input end of the output buffer and is simultaneously connected with the gate end of the NMOS tube N44, the drain ends of the N43 and N45 and the drain end of the P47; the source end of the PMOS tube P44 is connected with the drain ends of the P42, the P43 and the P48 and the source end of the P45, the drain end of the PMOS tube P44 is connected with the source end of the P46, and the substrate is connected with the VDDOUT;
the gate end of the PMOS tube P45 is connected with the gate end of the NMOS tube N45, the drain end of the N42, the drain end of the N44 and the drain end of the P46, the source end of the PMOS tube P45 is connected with the drain end of the P42, the drain end of the P43, the drain end of the P48 and the source end of the P44, the drain end of the PMOS tube P45 is connected with the source end of the P47, and the substrate is connected with the VDDOUT;
the gate end of the PMOS tube P46 is connected with the output end of the inverter and is simultaneously connected with the gate ends of the P42 and the N42, the source end of the PMOS tube P46 and the substrate are both connected with the drain end of the P44, and the drain end of the PMOS tube P46 is connected with the drain end of the N42, the drain end of the N44, the gate end of the P45 and the gate end of the N45;
the gate end of the PMOS tube P47 is connected with the input press welding point IN and is connected with the gate end of the P43 and the gate end of the N43, and the drain end of the PMOS tube P47 and the substrate are both connected with the drain end of the P45; the drain end of the PMOS tube P47 is connected with the input end of the output buffer and is connected with the drain end of the N43, the drain end of the N45, the gate end of the P44 and the gate end of the N44;
the gate end of the NMOS tube N42 is connected with the output end of the input inverter and is connected with the gate end of the P42 and the gate end of the P46, the source end and the substrate are both connected with GND, and the drain end of the NMOS tube N42 is connected with the drain end of the N44, the drain end of the P46, the gate end of the P45 and the gate end of the N45;
the gate end of the NMOS tube N43 is connected with an input press welding spot IN and is simultaneously connected with the gate end of the P43 and the gate end of the P47, the source end of the NMOS tube N43 is connected with the substrate and the GND, the drain end of the NMOS tube N43 is connected with the input end of the output buffer and is simultaneously connected with the drain end of the N45, the drain end of the P47, the gate end of the P44 and the gate end of the N44;
the gate end of the NMOS tube N44 is connected with the input end of the output buffer and is simultaneously connected with the drain end of the N43, the drain end of the N45, the drain end of the P47 and the gate end of the P4, the source end and the substrate are both connected with GND, and the drain end of the NMOS tube N44 is connected with the drain end of the N42, the drain end of the P46, the gate end of the P45 and the gate end of the N45;
the gate end of the NMOS tube N45 is connected with the drain end of the N42, the drain end of the N44, the drain end of the P46 and the gate end of the P45, and the source end and the substrate are connected with GND; the drain end of the NMOS tube N45 is connected with the input end of the output buffer, and is connected with the drain end of the N43, the drain end of the P47, the gate end of the P44 and the gate end of the N44;
the gate end of the NMOS tube N48 is connected with a pressing welding point EN and is connected with the gate end of the P48, the source end and the substrate are both connected with GND, and the drain end of the NMOS tube N48 is connected with the source end of the N42 and the source end of the N43; the gate end of the PMOS tube P48 is connected with the pressure welding point EN and is connected with the gate end of the N48, the source end and the substrate are both connected with VDDOUT, and the drain end of the PMOS tube P48 is connected with the drain end of the P42, the drain end of the P43, the source end of the P44 and the source end of the P45.
2. The voltage latch type level shifter circuit of claim 1, wherein the output buffer comprises a PMOS transistor P49 and an NMOS transistor N49; wherein,,
the gate end of the PMOS tube P49 is simultaneously connected with the drain end of the P47, the drain end of the N43, the drain end of the N45, the gate end of the P44 and the gate end of the N44; the source end of the PMOS tube P49 is connected with the substrate by the power supply voltage VDDOUT, the drain end is connected with the output pressure welding point OUT, and the source end is connected with the drain end of the N49;
the gate end of the NMOS tube N49 is simultaneously connected with the drain end of the P47, the drain end of the N43, the drain end of the N45, the gate end of the P44 and the gate end of the N44; the source end of the NMOS tube N49 is connected with the substrate GND, the drain end of the NMOS tube N49 is connected with the output pressure welding point OUT, and the drain end of the NMOS tube N49 is connected with the drain end of the PMOS tube P49.
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| CN113938126B true CN113938126B (en) | 2023-08-01 |
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|---|---|---|---|---|
| JP2003298408A (en) * | 2002-04-02 | 2003-10-17 | New Japan Radio Co Ltd | Level converting circuit |
| CN106899288A (en) * | 2017-02-21 | 2017-06-27 | 珠海市杰理科技股份有限公司 | Level shifting circuit |
| CN110620577A (en) * | 2019-10-12 | 2019-12-27 | 上海华力微电子有限公司 | FDSOI structure-based level conversion unit circuit and layout design method |
| CN110798201A (en) * | 2019-11-29 | 2020-02-14 | 重庆邮电大学 | High-speed withstand voltage level conversion circuit |
| CN214101345U (en) * | 2020-12-17 | 2021-08-31 | 中国电子科技集团公司第五十八研究所 | Level conversion structure supporting wide level range high-speed data |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3657235B2 (en) * | 2002-03-25 | 2005-06-08 | Ｎｅｃマイクロシステム株式会社 | Level shifter circuit and semiconductor device provided with the level shifter circuit |
| KR100853649B1 (en) * | 2007-04-02 | 2008-08-25 | 삼성전자주식회사 | Clock-gated latch with a level-converting funtion |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003298408A (en) * | 2002-04-02 | 2003-10-17 | New Japan Radio Co Ltd | Level converting circuit |
| CN106899288A (en) * | 2017-02-21 | 2017-06-27 | 珠海市杰理科技股份有限公司 | Level shifting circuit |
| CN110620577A (en) * | 2019-10-12 | 2019-12-27 | 上海华力微电子有限公司 | FDSOI structure-based level conversion unit circuit and layout design method |
| CN110798201A (en) * | 2019-11-29 | 2020-02-14 | 重庆邮电大学 | High-speed withstand voltage level conversion circuit |
| CN214101345U (en) * | 2020-12-17 | 2021-08-31 | 中国电子科技集团公司第五十八研究所 | Level conversion structure supporting wide level range high-speed data |
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