CN101924356B - Improved ESD protective device, corresponding integrated circuit - Google Patents
Improved ESD protective device, corresponding integrated circuit Download PDFInfo
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- CN101924356B CN101924356B CN201010173260.0A CN201010173260A CN101924356B CN 101924356 B CN101924356 B CN 101924356B CN 201010173260 A CN201010173260 A CN 201010173260A CN 101924356 B CN101924356 B CN 101924356B
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Abstract
The invention provides an improved ESD protective device for inhibiting current flowing through the ESD protective device in normal electrification. The improved ESD protective device comprises an RC detection circuit, a drive circuit and a current release device. The improved ESD protective device is characterized in that: one side of a capacitive device of the RC detection circuit is connected with an impedance circuit. The invention also provides a corresponding control method and an integrated circuit. An MOS tube connected in series with a capacitor is added into the RC detection circuit so as to inhibit the current flowing through the ESD release device in electrification and electrify a chip normally.
Description
Technical field
The present invention relates to ESD protector, the ESD protector between VDD-to-VSS especially, particularly, relates to and flows through the release ESD protector of electric current of device of ESD when effectively having suppressed to power on.
Background technology
For the damage that prevents that static discharge from causing, integrated circuit need to add ESD protection circuit and carry out electrostatic defending.For integrated circuit, static discharge is described with three kinds of physical models conventionally, respectively manikin (HBM, human bodymodel), machine mould (MM, machinemodel) and charging device model (CDM, charge device model), represent separately the dissimilar static discharge in real world.The ESD protection circuit of IO and the ESD protection circuit between POWER (power clamp) have formed the ESD protection of whole IC jointly.
Circuit involved in the present invention is the ESD protection circuit (power clamp) between above-mentioned VDD-to-VSS.ESD protection circuit between VDD-to-VSS has various ways, as gateground MOS (GGMOS), gate coupled MOS (GCMOS) and active driven MOS etc.Fig. 1 shows the ESD protection circuit between the active driving power of a kind of conventional RC and ground in prior art.This protective circuit comprises resistance 201, electric capacity 22, active driving circuit 3 and ESD current drain device 4; wherein; described resistance 201 and electric capacity 22 form RC testing circuit 20; described active driving circuit 3 consists of line and one or more levels inverter; described ESD current drain device 4 is one to be connected across between power vd D and GND NMOS pipe, and described active driving circuit 3 drives the ESD electric current of described ESD current drain device 4 to release between VDD and GND under the control of described RC testing circuit 20.For certain ESD protective capacities is provided, the size of described ESD current drain device 4 is larger.When the ESD that to have with respect to GND on VDD be positive polarity occurs, described RC testing circuit 20 detects this esd event and makes 4 conductings of described ESD current drain device by described active driving circuit 3, thereby electrostatic leakage is fallen.Like this, when ESD occurs, by controlling 4 conductings of described ESD current drain device, thereby provide the low impedance path of a VDD to GND, can make IC avoid the damage of ESD.When IC normally works, described ESD current drain device 4 is in closed condition.
In above-mentioned three kinds of ESD models (HMB, MM and CDM), the discharge time of HBM ESD is the longest, can reach hundreds of nanosecond.For enough ESD protective capacities are provided, the ON time of the described ESD current drain device 4 shown in Fig. 1 is wanted long enough, and therefore the value of described resistance 201 and described electric capacity 22 is larger.But ESD current drain device 4 conductings described in order to prevent from powering on, the time constant of described resistance 201 and described electric capacity 22 again can not be excessive.
In integrated circuit technology, the described resistance 201 in described Fig. 1 can use polysilicon (poly) resistance to realize.The advantage of polysilicon resistance is that resistance is relatively accurate.But, the ON time long enough of ESD current drain device 4 described in owing to will guarantee esd discharge time, the value of described resistance 201 is larger, and the square resistance of polysilicon resistance less (being less than 10ohm/sheet square) in some processing procedures, so the chip area that this polysilicon resistance takies is larger.In order to save area, described in this, resistance 201 can be realized with metal-oxide-semiconductor.For example, the circuit of realizing described resistance 201 with PMOS pipe as shown in Figure 2.The breadth length ratio of adjusting metal-oxide-semiconductor is easy to obtain the resistance needing, and Area Ratio polysilicon resistance is little a lot.
Compare with polysilicon resistance, the MOS resistance consisting of metal-oxide-semiconductor has been saved area, has but introduced new problem, should the described ESD current drain device 4 in off-state while powering on has electric current and flows through.Circuit simulation is found, in VDD is power-up to a period of time that is slightly larger than metal-oxide-semiconductor threshold voltage (Vt), is had electric current I peak and flow through, as shown in Figure 3 in described ESD current drain device 4.In described Fig. 3, curve 61 illustrates the variation characteristic of vdd voltage in normal power up, curve 62 illustrates the variation characteristic of the electric current of the described ESD current drain device 4 of flowing through in normal power up, wherein, in VDD is power-up to a period of time that is slightly larger than metal-oxide-semiconductor threshold voltage vt, in described ESD current drain device 4, having electric current I peak flows through, the reason that this electric current produces is when vdd voltage value is near metal-oxide-semiconductor threshold voltage vt, the resistance of described metal-oxide-semiconductor resistance 201 ' realization is excessive, described RC testing circuit 20 ' make 4 conductings of described ESD current drain device by described active driving circuit 3.Wherein, the size of above-mentioned electric current I peak is directly proportional to the size of described ESD current drain device 4, when the anti-ESD Capability Requirement of IC is higher, the size of described ESD current drain device 4 can be very large, above-mentioned electric current I peak can reach tens milliamperes and even up to a hundred milliamperes, from the angle of system applies, consider, above-mentioned electric current I peak does not wish to occur.
Summary of the invention
For defect of the prior art, the object of this invention is to provide a kind of improved ESD protector.
According to an aspect of the present invention, a kind of improved ESD protector is provided, it flows through the electric current of ESD protective device when suppressing normally to power on, comprise RC testing circuit, drive circuit and current drain device, the resistive device of RC testing circuit is MOS transistor, in capacitive device one side of RC testing circuit, is connected with an impedance circuit.Described impedance circuit at least comprises first MOS transistor; This first MOS transistor is connected across between the resistive device and capacitive device of RC testing circuit, and described drive circuit one side is coupled between described resistive device and described the first MOS transistor.
Preferably, described the first MOS transistor is PMOS pipe, and wherein, the drain electrode of described PMOS pipe connects the capacitive device of RC testing circuit, and source electrode connects the resistive device of RC testing circuit, and grid connects ground.
Preferably, described the first MOS transistor is NMOS pipe, and wherein, the drain electrode of described NMOS pipe connects the capacitive device of RC testing circuit, and source electrode connects the resistive device of RC testing circuit, and grid connects VDD.
Preferably, described the first MOS transistor comprises a plurality of PMOS pipes, wherein, is connected across between the resistive device and capacitive device of RC testing circuit the grounded-grid of described PMOS pipe after described a plurality of PMOS pipe string connection.
Preferably, described the first MOS transistor comprises a plurality of NMOS pipes, wherein, after described a plurality of NMOS pipe string connection, is connected across between the resistive device and capacitive device of RC testing circuit, and the grid of described NMOS pipe meets VDD.
Preferably, the breadth length ratio of described PMOS pipe is much larger than the breadth length ratio of the metal-oxide-semiconductor of the resistive device of formation RC testing circuit.
Preferably, the breadth length ratio of described NMOS pipe is much larger than the breadth length ratio of the metal-oxide-semiconductor of the resistive device of formation RC testing circuit.
According to another aspect of the present invention, a kind of control method that flows through the electric current of ESD protective device in improved ESD protector when suppressing normally to power on is also provided, it is characterized in that, comprise step: the impedance that improves capacitive device one side in RC testing circuit.
According to a further aspect of the invention, a kind of integrated circuit is provided, comprise power pins, internal circuit and ESD protection circuit, the resistive device of RC testing circuit is MOS transistor, also comprises for improving an impedance circuit of capacitive device one side impedance in the RC testing circuit of ESD protection circuit; Described impedance circuit comprises the first MOS transistor; This first MOS transistor is connected across between the resistive device and capacitive device of RC testing circuit, and one drive circuit one side is coupled between described resistive device and described the first MOS transistor.
Preferably, described the first MOS transistor comprises any in one or more following transistors: PMOS pipe or NMOS pipe.
The present invention by adding a metal-oxide-semiconductor with capacitances in series in RC testing circuit, thereby compare with common ESD protection circuit, circuit provided by the present invention flows through the ESD electric current of device of releasing in the time of can suppressing to power on, and the shared area of the metal-oxide-semiconductor adding is very little.
Accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that other features, objects and advantages of the present invention will become:
Fig. 1 shows according to prior art, the schematic diagram of the protection circuit between the active driving of a kind of conventional RC ESD VDD-to-VSS;
Fig. 2 shows according to prior art, the schematic diagram of the protection circuit between the active driving of another kind of conventional RC ESD VDD-to-VSS;
Fig. 3 shows according to circuit shown in Fig. 2, the variation characteristic schematic diagram of the electric current of the described ESD current drain device of flowing through in normal power up;
Fig. 4 shows according to the first embodiment of the present invention, the structural representation of ESD protector;
Fig. 5 shows according to one of the first embodiment of the present invention and changes example, the structural representation of ESD protector;
Fig. 6 shows according to a second embodiment of the present invention, the structural representation of ESD protector; And
Fig. 7 illustrates according to a second embodiment of the present invention one and changes example, the structural representation of ESD protector.
Embodiment
Fig. 4 shows according to the first embodiment of the present invention, the structural representation of ESD protector.Particularly, in the present embodiment, described ESD protector comprises RC testing circuit 2, active driving circuit 3 and ESD current drain device 4, and wherein, described RC testing circuit 2 comprises PMOS pipe 21, electric capacity 22 and PMOS pipe 23.The source electrode of described PMOS pipe 21 connects VDD, and its drain electrode connects the source electrode of described PMOS pipe 23, and its grid connects GND.The source electrode of described PMOS pipe 23 connects the drain electrode of described PMOS pipe 21, and its drain electrode connects described electric capacity 22, and its grid connects GND.The two ends of described electric capacity 22 are connected with drain electrode and the GND of described PMOS pipe 23 respectively.
Those skilled in the art understand, the improvements of the present embodiment are, in described RC testing circuit 2, added described PMOS pipe 23, described PMOS pipe 23 is connected with described electric capacity 22 in capacitive device one side, therefore the impedance that has increased capacitive device one side, make described ESD current drain device 4 when powering on, be difficult for conducting, thereby suppressed to flow through electric current I peak wherein.
With the 5V device in 1.0um processing procedure, carried out emulation.Circuit simulation discovery, under some process corner (corner), described ESD protection circuit provided by the invention can be eliminated the electric current that powers in described ESD current drain device 4 completely; Under other process corner (corner), the electric current that powers in described ESD current drain device 4 can be reduced to 1/2nd to 1/3rd of circuit shown in Fig. 2.
Preferably, the breadth length ratio of described PMOS pipe 23 is much larger than the breadth length ratio of described PMOS pipe 21.When vdd voltage value is larger, the impedance that described PMOS pipe 23 is introduced can be ignored, and the circuit shown in described Fig. 4 can be equivalent to the circuit shown in described Fig. 2, and therefore the shown circuit of described Fig. 4 is suitable with the circuit shown in described Fig. 2 in ESD barrier propterty.Preferably, described ESD protection circuit adopts 1.0um technique, with 5V device, realizes, and it is 20/1 (being w/l=20/1) that the PMOS pipe adding is got positive breadth length ratio, and the area taking is very little.
Fig. 5 shows according to one of the first embodiment of the present invention and changes example, the structural representation of ESD protector.Particularly, in the present embodiment, described ESD protector comprises RC testing circuit 2, active driving circuit 3 and ESD current drain device 4.The difference of the first embodiment shown in itself and described Fig. 4 is, a side at the capacitive device of described RC testing circuit 2 in the present embodiment is in series with a plurality of PMOS pipes, particularly, after PMOS pipe 231, PMOS pipe 232 and 233 series connection of PMOS pipe, be connected across between described PMOS pipe 21 and described electric capacity 22, the grid of described PMOS pipe 231, PMOS pipe 232 and PMOS pipe 233 connects GND.Those skilled in the art, the PMOS pipe of cross-over connection any amount between described PMOS pipe 21 and described electric capacity 22, does not repeat them here according to actual needs.
Fig. 6 shows according to a second embodiment of the present invention, the structural representation of ESD protector.Particularly, in the present embodiment, described ESD protector comprise RC testing circuit 2 ', active driving circuit 3 ' and ESD current drain device 4, wherein, described RC testing circuit 2 ' comprise NMOS pipe 21, electric capacity 22 and NMOS pipe 23 '.The source electrode of described NMOS pipe 21 connects GND, its drain electrode connect described NMOS pipe 23 ' source electrode, its grid connects VDD.Described NMOS pipe 23 ' source electrode connect the drain electrode of described NMOS pipe 21, its drain electrode connects described electric capacity 22, its grid connects VDD.The two ends of described electric capacity 22 respectively with described NMOS pipe 23 ' drain electrode and VDD be connected.
The difference of the first embodiment shown in the present embodiment and described Fig. 4 is, the present embodiment capacitive device one side of described RC testing circuit added a NMOS pipe 23 ', those skilled in the art understand, the principle of electric current that flows through ESD protective device in the first embodiment shown in described Fig. 4 while suppressing normally to power on is applicable equally in the present embodiment, does not repeat them here.
Fig. 7 illustrates according to a second embodiment of the present invention one and changes example, the structural representation of ESD protector.Particularly, in the present embodiment, described ESD protector comprise RC testing circuit 2 ', active driving circuit 3 ' and ESD current drain device 4.The difference of the second embodiment shown in itself and described Fig. 6 is, in the present embodiment described RC testing circuit 2 ' a side of capacitive device be in series with a plurality of NMOS pipes, particularly, NMOS pipe 231 ', NMOS pipe 232 ' and the 233 ' series connection of NMOS pipe after be connected across described NMOS pipe 21 ' with described electric capacity 22 between, described NMOS pipe 231 ', NMOS pipe 232 ' and NMOS pipe 233 ' grid connection VDD.Those skilled in the art, can be according to actual needs described NMOS pipe 21 ' and described electric capacity 22 between the NMOS pipe of cross-over connection any amount, do not repeat them here.
Those skilled in the art understand, in the variation example of first and second embodiment, PMOS pipe wherein can be changed to corresponding NMOS pipe, NMOS pipe can be changed to corresponding PMOS pipe, for example, in the embodiment shown in described Fig. 4 to Fig. 6, the PMOS resistance that described PMOS pipe 21 forms can be changed to by the NMOS pipe NMOS resistance of realizing.And change in example more, PMOS pipe and NMOS pipe wherein can also be changed to the components and parts that other can realize identical function, and those skilled in the art can, in conjunction with the such variation of existing techniques in realizing, not repeat them here.Further, described active driving circuit 3 comprises line and inverter, and according to logic needs, described inverter can be one-level or multistage, and this can't affect flesh and blood of the present invention.
According to the present invention, Fig. 4 is to embodiment illustrated in fig. 7 and change example, the invention provides a kind of control method that flows through the electric current of ESD protective device in improved ESD protector when suppressing normally to power on.Preferably include the impedance that improves capacitive device one side in RC testing circuit.
According to the present invention, Fig. 4 is to embodiment illustrated in fig. 7 and variation example, and the present invention also provides a kind of integrated circuit.Described integrated circuit comprises power pins, internal circuit and ESD protection circuit, also comprises for improving an impedance circuit of capacitive device one side impedance in the RC testing circuit of ESD protection circuit.Preferably, described impedance circuit comprises the first MOS transistor.Preferably, described the first MOS transistor comprises one or more PMOS pipes or NMOS pipe.
Further, it will be appreciated by those skilled in the art that integrated circuit provided by the invention can be various types of integrated circuits, and need to change according to concrete enforcement.In other words, the scheme that all integrated circuits that flow through the electric current of ESD protective device while need suppressing normally to power on can adopt above-described embodiment to provide.Particularly, those skilled in the art can be in conjunction with prior art and above-mentioned enforcement, change example realizes such integrated circuit, does not repeat them here.
Above specific embodiments of the invention are described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and those skilled in the art can make various distortion or modification within the scope of the claims, and this does not affect flesh and blood of the present invention.
Claims (7)
1. an improved ESD protector, it flows through the electric current of ESD protective device when suppressing normally to power on, comprise RC testing circuit, drive circuit and current drain device, it is characterized in that: the resistive device of RC testing circuit is MOS transistor, in capacitive device one side of RC testing circuit, be connected with an impedance circuit; Described impedance circuit at least comprises first MOS transistor; This first MOS transistor is connected across between the resistive device and capacitive device of RC testing circuit, and described drive circuit one side is coupled between described resistive device and described the first MOS transistor.
2. ESD protector according to claim 1, is characterized in that: described the first MOS transistor is PMOS pipe, and wherein, the drain electrode of described PMOS pipe connects the capacitive device of RC testing circuit, and source electrode connects the resistive device of RC testing circuit, and grid connects ground.
3. ESD protector according to claim 1, is characterized in that: described the first MOS transistor is NMOS pipe, and wherein, the drain electrode of described NMOS pipe connects the capacitive device of RC testing circuit, and source electrode connects the resistive device of RC testing circuit, and grid connects VDD.
4. ESD protector according to claim 1, it is characterized in that, described the first MOS transistor comprises a plurality of PMOS pipes, wherein, after described a plurality of PMOS pipe string connection, be connected across between the resistive device and capacitive device of RC testing circuit the grounded-grid of described PMOS pipe.
5. ESD protector according to claim 1, it is characterized in that, described the first MOS transistor comprises a plurality of NMOS pipes, wherein, after described a plurality of NMOS pipe string connection, be connected across between the resistive device and capacitive device of RC testing circuit, the grid of described NMOS pipe meets VDD.
6. an integrated circuit, comprise power pins, internal circuit and ESD protection circuit, it is characterized in that, the resistive device of RC testing circuit is MOS transistor, also comprises for improving an impedance circuit of capacitive device one side impedance in the RC testing circuit of ESD protection circuit; Described impedance circuit comprises the first MOS transistor; This first MOS transistor is connected across between the resistive device and capacitive device of RC testing circuit, and one drive circuit one side is coupled between described resistive device and described the first MOS transistor.
7. integrated circuit according to claim 6, is characterized in that, described the first MOS transistor comprises any in one or more following transistors:
-PMOS pipe;
-NMOS pipe.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010173260.0A CN101924356B (en) | 2010-05-13 | 2010-05-13 | Improved ESD protective device, corresponding integrated circuit |
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| CN201010173260.0A CN101924356B (en) | 2010-05-13 | 2010-05-13 | Improved ESD protective device, corresponding integrated circuit |
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| CN101924356A CN101924356A (en) | 2010-12-22 |
| CN101924356B true CN101924356B (en) | 2014-11-05 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105990330A (en) * | 2015-01-28 | 2016-10-05 | 旺宏电子股份有限公司 | Electrostatic discharge protection device |
| CN108321117A (en) * | 2017-12-15 | 2018-07-24 | 西安科技大学 | TSV pinboards based on metal-oxide-semiconductor and preparation method thereof |
| CN109217278B (en) * | 2018-11-20 | 2023-09-22 | 上海艾为电子技术股份有限公司 | Surge protection circuit, circuit system and electronic equipment |
| CN109524949A (en) * | 2018-12-20 | 2019-03-26 | 西安电子科技大学 | A kind of electrostatic protection Esd protection device |
| CN112968437B (en) * | 2021-04-01 | 2022-07-08 | 长鑫存储技术有限公司 | Electrostatic protection circuit and electrostatic protection network of chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6157530A (en) * | 1999-01-04 | 2000-12-05 | International Business Machines Corporation | Method and apparatus for providing ESD protection |
| CN1447427A (en) * | 2002-03-26 | 2003-10-08 | 华邦电子股份有限公司 | Electrostatic discharge protection circuit |
| CN101099278A (en) * | 2004-11-12 | 2008-01-02 | 德州仪器公司 | Electrostatic discharge protection power rail clamp with feedback-enhanced triggering and conditioning circuitry |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW307913B (en) * | 1996-04-24 | 1997-06-11 | Winbond Electronics Corp | Protection circuit of CMOS integrated circuit |
| US7098717B2 (en) * | 2004-06-25 | 2006-08-29 | Altera Corporation | Gate triggered ESD clamp |
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2010
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6157530A (en) * | 1999-01-04 | 2000-12-05 | International Business Machines Corporation | Method and apparatus for providing ESD protection |
| CN1447427A (en) * | 2002-03-26 | 2003-10-08 | 华邦电子股份有限公司 | Electrostatic discharge protection circuit |
| CN101099278A (en) * | 2004-11-12 | 2008-01-02 | 德州仪器公司 | Electrostatic discharge protection power rail clamp with feedback-enhanced triggering and conditioning circuitry |
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| CN101924356A (en) | 2010-12-22 |
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