CN1447427A - Electrostatic discharge protection circuit - Google Patents
Electrostatic discharge protection circuit Download PDFInfo
- Publication number
- CN1447427A CN1447427A CN 02108107 CN02108107A CN1447427A CN 1447427 A CN1447427 A CN 1447427A CN 02108107 CN02108107 CN 02108107 CN 02108107 A CN02108107 A CN 02108107A CN 1447427 A CN1447427 A CN 1447427A
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- Prior art keywords
- bond pad
- protection circuit
- esd protection
- esd
- circuit
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Abstract
A circuit suitable to IC consists of the discharging assembly and the electro-static discharge (ESD) testing circuit including the series capacitance, the first resistance and the second resistance. The capacitance and the first resistance are coupled to the point between the control end of the discharging assembly and the first joint soldering pad of the IC. The second resistance is connected to the point between the control end and the second joint soldering pad. In normal condition, the discharging assembly is in off state. When ESD happens, the capacitance is in short circuit and the first and second resistances play the function of partial pressure. Thus, ESD testing circuit provides a suitable voltage for the control end making the discharging assembly release ESD current under optimal condition.
Description
Technical field
The present invention relates to a kind of ESD protection circuit, relate in particular to a kind of esd protection circuit that is applicable to integrated circuit.
Background technology
Fig. 1 is a known esd protection circuit that is used in integrated circuit.This esd protection circuit 10 has a NMOS N
ESDBe coupled to bond pad 12 and V
SSBetween the power line.Capacitor C and resistance R constitute a RC coupling circuit.When one with respect to V
-SSWhen coming across bond pad 12 for positive ESD voltage, N
ESDGrid can obtain positive voltage, to quicken N
ESD-Triggering speed.And the human body discharge mode of general commercial IC (human body mode, HBM) under, esd protection circuit must bear the ESD voltage of 2KV at least.
Yet, by experiment as can be known, work as N
ESDGrid bias excessive or cross when low, all can lower the ESD tolerance of integrated circuit.
See also Fig. 2 and Fig. 3, Fig. 2 is the N among Fig. 1
ESDGrid add the schematic diagram of a fixed voltage.Fig. 3 is the experimental result schematic diagram of Fig. 2, is the graph of a relation of grid voltage and ESD tolerance.Grid voltage can effectively reduce N
ESDTrigger voltage.Therefore, when less grid bias, the ESD tolerance will increase along with the increase of grid bias, as shown in Figure 3.Yet when grid bias was excessive, most ESD electric current will pass through very thin N
ESDSurface channel, thereby be very easy to damage N
ESDSo during bigger grid bias, the ESD tolerance will reduce along with the increase of grid bias, as shown in Figure 3.That is to say, when grid bias is arranged in particular value (as the V of Fig. 3
Gopt) time, the circuit of Fig. 2 just has best esd protection tolerance.Therefore, how to make N among Fig. 1
ESDGrid when ESD takes place, have V
GoptBias voltage, just become the target that circuit designers is made great efforts.
Yet the esd protection circuit of Fig. 1 when the ESD of reality takes place, but often is difficult to reach the demand of high ESD tolerance.The 1st reason is N
ESDHas many parasitic capacitances (such as C
Gd, C
GsDeng), its value can be along with processing procedure zero be waftd.Clearly, the variation of capacitance has also influenced the withstand voltage N of being coupled to of the ESD that comes across bond pad 12
ESDThe magnitude of voltage of grid.The 2nd reason is that different ESD is withstand voltage, and its voltage climbing speed on bond pad 12 is also different, relative, is coupled to N
ESDGrid on voltage also can be different.The very possible peculiar phenomenon that occurs is that the circuit among Fig. 1 has passed through the HBM ESD voltage-withstand test of 5KV, but has but but failed in the HBM of 2KV ESD voltage-withstand test.
In other words, when the circuit of the construction drawing 1 of reality, will face N
ESDGrid voltage be difficult to the situation controlling or predict.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of esd protection circuit.Esd detection circuit wherein can provide the grid voltage of a MOS very accurately, to guarantee the ESD tolerance of whole esd protection circuit.
For achieving the above object, (electrostatic discharge, ESD) protective circuit are applicable in the integrated circuit (integrated circuit), include: a main discharge assembly has a control end to the invention provides a kind of static discharge; It is characterized in that, also comprise: an electrostatic discharge testing circuit, this testing circuit includes: electric capacity of series connection and one first resistance are coupled between one first bond pad of this control end and this IC; One second resistance is coupled between one second bond pad of this control end and this IC;
When normal running, this main discharge assembly is a closed condition, and when a static discharge took place, this electrostatic discharge testing circuit was in order to trigger this main discharge assembly;
Described main discharge assembly is that (metal-oxide-semiconductor MOS), is coupled between this first bond pad and this second bond pad N type metal-oxide semiconductor transistor; When normal running, first operating voltage of described first bond pad is higher than second operating voltage of described second bond pad; Described first bond pad is an output inlet, and described second bond pad is as a V
SSPower supply; Described first bond pad also can be used as a V
DDPower line, second bond pad are then as a V
SSPower supply;
Described main discharge assembly also is a P type MOS, is coupled between this first bond pad and this second bond pad; When normal running, first operating voltage of described first bond pad is lower than second operating voltage of described second bond pad; Described first bond pad is an output inlet, and described second bond pad is as a V
DDPower supply; Described first bond pad also can be used as a V
SSPower line, described second bond pad is then as a V
DDPower supply.
Described ESD protection circuit is as the elementary ESD protection circuit (primary ESD protection circuit) in the output inlet; Also can be used as the level ESD protection circuit (secondary ESD protection circuit) in the output inlet, be coupled to this first bond pad or this second bond pad by a buffer resistance.
The present invention also provides a kind of and foregoing invention to belong to a kind of ESD protection circuit of same inventive concept; be coupled between one first bond pad and one second bond pad of an integrated circuit; include: a main discharge assembly; be coupled between this first bond pad and this second bond pad; has a control end; it is characterized in that; also comprise: an electrostatic discharge testing circuit; be coupled to this first bond pad; this second bond pad and this control end; at least one first resistance and one second resistance that include series connection; when normal running; this bleeder circuit cuts out this main discharge assembly; when static discharge took place, this bleeder circuit triggered this main discharge assembly, with the release electrostatic discharging current.
Described electrostatic discharge testing circuit includes an electric capacity, takes place and normal running in order to isolate static discharge; Described first resistance and capacitance series are between first bond pad and control end, and described second resistance is coupled between the control end and second bond pad;
Described main discharge assembly is a N type MOS, is coupled between this first bond pad and this second bond pad; When normal running, first operating voltage of described first bond pad is lower than second operating voltage of described second bond pad.
Described main discharge assembly also can be a P type MOS, is coupled between this first bond pad and this second bond pad.When normal running, first operating voltage of described first bond pad is higher than second operating voltage of described second bond pad.
Effect of the present invention is: compared with prior art; esd protection circuit of the present invention is when ESD takes place; utilize an electric capacity and a resistor voltage divider circuit just as short circuit, a voltage potential that is fit to can be provided, make NMOS or the maximum effect of PMOS performance of being responsible for discharging the ESD electric current.
Description of drawings
Fig. 1 is at the esd protection circuit figure of integrated circuit in the prior art;
Fig. 2 is the N among Fig. 1
ESDGrid add the schematic diagram of a fixed voltage;
Fig. 3 is the graph of a relation of grid voltage and ESD tolerance;
Fig. 4 is one according to the present invention, has the esd protection circuit of NMOS;
Fig. 5 is one according to the present invention, has the esd protection circuit of PMOS;
Fig. 6 has shown the N among Fig. 4
ESDIn grid bias is V
GoptThe time volt-ampere characteristics of figure;
Fig. 7 is for applying to the present invention in the schematic diagram of one secondary formula esd protection circuit;
Fig. 8 is according to the present invention, clamped circuit between the power line of utilization NMOS; And
Fig. 9 is according to the present invention, clamped circuit between the power line of utilization NMOS.
The number in the figure explanation
10,20～esd protection circuit
12,30～bond pad
22～esd detection circuit
24～elementary esd protection circuit
26～secondary esd protection circuit
28～internal circuit
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Fig. 4 is one according to the present invention, has the esd protection circuit of NMOS.Esd protection circuit 20 among Fig. 4 is coupled between an anode and the negative electrode, includes a NMOS N
ESDAnd esd detection circuit 22.Esd detection circuit 22 can distinguish general normal running and an ESD takes place.When normal running, esd detection circuit 22 has been closed N
ESDWhen ESD takes place.Esd detection circuit 22 has triggered N
ESDThe most of system of ESD electric current passes through N
ESDAnd discharge.
Esd detection circuit 22 has a capacitor C
n, a resistance R
N1An and resistance R
N2C
nWith R
N1Be serially connected with this anode and N
ESDGrid between, its order can exchange arbitrarily.R
N2Be coupled to this negative electrode and N
ESDGrid between.
Anode and negative electrode are couple to two bond pads respectively, may be that bond pad or power line etc. are gone in output.Anode means when normal running to have the higher voltage potential with respect to negative electrode.
C
nCapacitance must do suitable selection, on the one hand must be little make is coupled to N during normal running (lower frequency)
ESDThe voltage of grid be unlikely to big to making N
ESDTrigger; On the other hand must be big to when (upper frequency) takes place ESD, compared to R
N1With R
N2, C
nTwo ends just as short circuit.This is to utilize C
nImpedance (=1/ (2*pi*C
n* different and different characteristic f)) along with frequency of operation f.
When normal running, N
ESDGrid passed through R
N2And be couple to negative electrode (having lower voltage), so N
ESDPresent closing state, can avoid unnecessary leakage current to take place.
When the anode target is the ESD generation of positive voltage, N
ESD_ grid (V
G) voltage experienced can represent with following equation (1)
V
G＝V
A-C*(R
n2)/(R
n1+R
n2+1/(2*pi*C
n*f))---- (1)
Wherein, V
A-CThe expression anode is to the cross-pressure of negative electrode.Compared to R
N1With R
N2, when ESD takes place, C
nTwo ends just as short circuit; Be R
N1, R
N2＞＞1/ (2*pi*C
n* f).So equation (1) can be reduced to following equation (2).
V
G～V
A-C*R
n2/(R
n1+R
n2) --------- (2)
As shown in Figure 3, whole esd protection circuit 20 is to design in grid bias in V
GoptIn time, trigger, and esd protection circuit 20 just has best ESD tolerance.Fig. 6 has shown the N among Fig. 4
ESDIn grid bias is V
GoptThe time voltage-current curve figure.Clearly, work as N
ESDGrid bias at V
GoptThe time, the voltage of anode is in case up to V
Break_optThe time, N
ESDJust enter and return (snapback) state of speeding, can discharge a large amount of ESD electric currents.In other words, work as N
ESDIn grid bias at V
GoptThe time, the voltage of anode can arrive V at the most
Break_otpUtilize this characteristic, for the esd protection circuit that makes Fig. 4 has best ESD tolerance, behind equation (2), R
N1With R
N2The relation with following equation (3) that just should design.
V
Gopt～V
bread_opt*R
n2/(R
n1+R
n2) ----------(3)
If, R
N1With R
N2Meet above relation, when ESD takes place, when the cross-pressure of anode and negative electrode reaches V
Break_optThe time, N
ESDGrid also just in time arrive V
Gopt, and then trigger N
ESDTo discharge the ESD electric current.Under this situation, can obtain best esd protection effect.
Identical reason, the present invention also can use PMOS to implement, as shown in Figure 5.Fig. 5 is one according to the present invention, has the esd protection circuit of PMOS.Contrast Fig. 4, the assembly method of attachment among Fig. 5 can be learnt by being familiar with esd protection operator derivation, seldom do explanation at this.
Fig. 7 is for applying to the present invention in the schematic diagram of one secondary formula esd protection circuit.Secondary formula esd protection circuit includes an elementary esd protection circuit 24, a resistance R haply
BuffAnd level esd protection circuit 26.In elementary esd protection circuit 24, bond pad 30 and V
SSBetween power line with N
ESD1, R
N1, R
N2And C
N1Constitute an esd protection circuit of the present invention.Similar structure also comes across bond pad 30 and V
DDBetween, internal circuit 28 and V
DDBetween the power line, internal circuit 28 and V
SSBetween the power line.Secondary esd protection circuit 26 mainly is that the voltage that internal circuit 28 is received is lived in strangulation, and elementary esd protection circuit 24 mainly is to discharge most ESD electric current.Therefore, the P in the secondary esd protection circuit 26
ESD2With N
ESD2Size of components can be smaller, and the P in the elementary esd protection circuit 24
ESD1With N
ESD1Then must be to have big size of components.
Esd protection circuit of the present invention is also applicable to the clamped circuit between power line, as Fig. 8 and shown in Figure 9.Fig. 8 is according to the present invention, clamped circuit between the power line of utilization NMOS; Fig. 9 is according to the present invention, clamped circuit between the power line of utilization NMOS.
Though the present invention with preferred embodiment openly as above; but; it is not to be used for limiting the present invention; anyly have the knack of this manufacturing technology process person; without departing from the spirit and scope of the present invention; when can doing to change and retouching, so protection scope of the present invention is as the criterion when the scope that claims defined that look present patent application.
Claims (18)
1. an ESD protection circuit is applicable in the integrated circuit, includes: a main discharge assembly has a control end; It is characterized in that, also comprise:
One electrostatic discharge testing circuit, this testing circuit includes:
One electric capacity and one first resistance of series connection are coupled to one the of this control end and this IC
Between one bond pad;
One second resistance is coupled between one second bond pad of this control end and this IC;
When normal running, this main discharge assembly is a closed condition, when a static discharge is sent out
When giving birth to, this electrostatic discharge testing circuit is in order to trigger this main discharge assembly.
2. ESD protection circuit as claimed in claim 1 is characterized in that, described main discharge assembly is a N type metal-oxide semiconductor transistor, is coupled between this first bond pad and this second bond pad.
3. ESD protection circuit as claimed in claim 2 is characterized in that, when normal running, first operating voltage of described first bond pad is higher than second operating voltage of described second bond pad.
4. ESD protection circuit as claimed in claim 2 is characterized in that, described first bond pad is an output inlet, and described second bond pad is as a V
SSPower supply.
5. ESD protection circuit as claimed in claim 2 is characterized in that, described first bond pad is as a V
DDPower line, described second bond pad is as a V
SSPower supply.
6. ESD protection circuit as claimed in claim 1 is characterized in that, described main discharge assembly is-P type MOS to be coupled between this first bond pad and this second bond pad.
7. ESD protection circuit as claimed in claim 6 is characterized in that, when normal running, first operating voltage of described first bond pad is lower than second operating voltage of described second bond pad.
8. ESD protection circuit as claimed in claim 6 is characterized in that, described first bond pad is an output inlet, and described second bond pad is as a V
DDPower supply.
9. ESD protection circuit as claimed in claim 2 is characterized in that, described first bond pad is as a V
SSPower line, described second bond pad is as a V
DDPower supply.
10. ESD protection circuit as claimed in claim 1 is characterized in that, described ESD protection circuit is as the elementary ESD protection circuit in the output inlet.
11. ESD protection circuit as claimed in claim 1; it is characterized in that; described ESD protection circuit is coupled to this first bond pad or this second bond pad as a level ESD protection circuit in the output inlet by a buffer resistance.
12. an ESD protection circuit is coupled between one first bond pad and one second bond pad of an integrated circuit, includes:
One main discharge assembly, be coupled to this first bond pad and this second bond pad it
Between, have a control end, it is characterized in that, also comprise:
One electrostatic discharge testing circuit is coupled to this first bond pad, this second seam welding
Fill up and this control end, include one first resistance and one second resistance of series connection at least,
When normal running, this bleeder circuit cuts out this main discharge assembly, takes place at static discharge
The time, this bleeder circuit triggers this main discharge assembly, with the release electrostatic discharging current.
13. ESD protection circuit as claimed in claim 12 is characterized in that, described electrostatic discharge testing circuit includes an electric capacity, takes place and normal running in order to isolate static discharge.
14. ESD protection circuit as claimed in claim 13 is characterized in that, described first resistance and capacitance series are between first bond pad and control end, and described second resistance is coupled between the control end and second bond pad.
15. ESD protection circuit as claimed in claim 12 is characterized in that, described main discharge assembly is a N type MOS, is coupled between this first bond pad and this second bond pad.
16. ESD protection circuit as claimed in claim 15, tool be characterised in that, when normal running, first operating voltage of described first bond pad is lower than second operating voltage of described second bond pad.
17. ESD protection circuit as claimed in claim 12 is characterized in that, described main discharge assembly is a P type MOS, is coupled between this first bond pad and this second bond pad.
18. ESD protection circuit as claimed in claim 17 is characterized in that, when normal running, first operating voltage of described first bond pad is higher than second operating voltage of described second bond pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02108107 CN1275326C (en) | 2002-03-26 | 2002-03-26 | Electrostatic discharge protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02108107 CN1275326C (en) | 2002-03-26 | 2002-03-26 | Electrostatic discharge protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1447427A true CN1447427A (en) | 2003-10-08 |
| CN1275326C CN1275326C (en) | 2006-09-13 |
Family
ID=28048474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02108107 Expired - Fee Related CN1275326C (en) | 2002-03-26 | 2002-03-26 | Electrostatic discharge protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1275326C (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924356A (en) * | 2010-05-13 | 2010-12-22 | 彩优微电子(昆山)有限公司 | Improved ESD protective device, corresponding method and integrated circuit |
| CN101273507B (en) * | 2005-07-26 | 2010-12-29 | 德克萨斯仪器股份有限公司 | System and method for protecting IC components |
| CN101826513B (en) * | 2009-03-04 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Resistor string bleeding device with embedded capacitor |
| CN102593122A (en) * | 2011-01-10 | 2012-07-18 | 英飞凌科技股份有限公司 | Semiconductor ESD circuit and method |
| CN103247621A (en) * | 2012-02-07 | 2013-08-14 | 联发科技股份有限公司 | ESD protection circuit |
| CN103427826A (en) * | 2012-05-03 | 2013-12-04 | 联发科技股份有限公司 | Output circuit |
| CN104681543A (en) * | 2013-12-03 | 2015-06-03 | 上海北京大学微电子研究院 | Encapsulating structure with clamping and ESD (Electro-Static Discharge) protection |
| CN104836565A (en) * | 2014-02-11 | 2015-08-12 | 台湾类比科技股份有限公司 | Output buffer capable of rapidly switching grid potential and electrostatic protection circuit |
| CN104979814A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protecting circuit |
| US9306389B2 (en) | 2012-02-07 | 2016-04-05 | Mediatek Inc. | ESD protection circuit |
| CN107403796A (en) * | 2016-05-20 | 2017-11-28 | 中芯国际集成电路制造(上海)有限公司 | High pressure ESD protection circuits |
| CN109342837A (en) * | 2018-10-31 | 2019-02-15 | 许继集团有限公司 | A kind of electrostatic measurement Circuits and Systems |
| CN111884490A (en) * | 2019-05-03 | 2020-11-03 | 台达电子工业股份有限公司 | Power circuit and integrated circuit |
-
2002
- 2002-03-26 CN CN 02108107 patent/CN1275326C/en not_active Expired - Fee Related
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101273507B (en) * | 2005-07-26 | 2010-12-29 | 德克萨斯仪器股份有限公司 | System and method for protecting IC components |
| CN101826513B (en) * | 2009-03-04 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Resistor string bleeding device with embedded capacitor |
| CN101924356A (en) * | 2010-05-13 | 2010-12-22 | 彩优微电子(昆山)有限公司 | Improved ESD protective device, corresponding method and integrated circuit |
| CN101924356B (en) * | 2010-05-13 | 2014-11-05 | 彩优微电子(昆山)有限公司 | Improved ESD protective device, corresponding integrated circuit |
| US9013842B2 (en) | 2011-01-10 | 2015-04-21 | Infineon Technologies Ag | Semiconductor ESD circuit and method |
| CN102593122A (en) * | 2011-01-10 | 2012-07-18 | 英飞凌科技股份有限公司 | Semiconductor ESD circuit and method |
| US9478979B2 (en) | 2011-01-10 | 2016-10-25 | Infineon Technologies Ag | Semiconductor ESD circuit and method |
| CN102593122B (en) * | 2011-01-10 | 2014-12-17 | 英飞凌科技股份有限公司 | Semiconductor ESD circuit and method |
| CN103247621B (en) * | 2012-02-07 | 2015-11-25 | 联发科技股份有限公司 | ESD protection circuit |
| US9305915B2 (en) | 2012-02-07 | 2016-04-05 | Mediatek Inc. | ESD protection circuit |
| CN103247621A (en) * | 2012-02-07 | 2013-08-14 | 联发科技股份有限公司 | ESD protection circuit |
| US9306389B2 (en) | 2012-02-07 | 2016-04-05 | Mediatek Inc. | ESD protection circuit |
| CN103427826A (en) * | 2012-05-03 | 2013-12-04 | 联发科技股份有限公司 | Output circuit |
| US9263882B2 (en) | 2012-05-03 | 2016-02-16 | Mediatek Inc. | Output circuits with electrostatic discharge protection |
| CN103427826B (en) * | 2012-05-03 | 2016-06-08 | 联发科技股份有限公司 | Output circuit |
| CN104681543A (en) * | 2013-12-03 | 2015-06-03 | 上海北京大学微电子研究院 | Encapsulating structure with clamping and ESD (Electro-Static Discharge) protection |
| CN104836565A (en) * | 2014-02-11 | 2015-08-12 | 台湾类比科技股份有限公司 | Output buffer capable of rapidly switching grid potential and electrostatic protection circuit |
| CN104979814A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protecting circuit |
| CN104979814B (en) * | 2014-04-02 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of ESD protection circuit |
| CN107403796A (en) * | 2016-05-20 | 2017-11-28 | 中芯国际集成电路制造(上海)有限公司 | High pressure ESD protection circuits |
| CN107403796B (en) * | 2016-05-20 | 2020-02-07 | 中芯国际集成电路制造(上海)有限公司 | High-voltage ESD protection circuit |
| CN109342837A (en) * | 2018-10-31 | 2019-02-15 | 许继集团有限公司 | A kind of electrostatic measurement Circuits and Systems |
| CN111884490A (en) * | 2019-05-03 | 2020-11-03 | 台达电子工业股份有限公司 | Power circuit and integrated circuit |
| CN111884490B (en) * | 2019-05-03 | 2022-07-08 | 台达电子工业股份有限公司 | Power circuit and integrated circuit |
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|---|---|
| CN1275326C (en) | 2006-09-13 |
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Granted publication date: 20060913 |