CN107403796B

CN107403796B - High-voltage ESD protection circuit

Info

Publication number: CN107403796B
Application number: CN201610341917.7A
Authority: CN
Inventors: 王俊; 卢斌; 刘森; 郭之光
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-05-20
Filing date: 2016-05-20
Publication date: 2020-02-07
Anticipated expiration: 2036-05-20
Also published as: CN107403796A

Abstract

The invention provides a high-voltage ESD protection circuit, which comprises a bias circuit, an ESD trigger circuit and an ESD release circuit, wherein the bias circuit, the ESD trigger circuit and the ESD release circuit are arranged between a high-voltage power line and a ground wire and are sequentially coupled, and a plurality of voltage division nodes are arranged on the bias circuit; the ESD trigger circuit is mainly composed of an RC delay network connected by at least one resistor and a plurality of capacitors, and each capacitor is correspondingly coupled to a voltage division node of the bias circuit; the ESD release circuit is mainly composed of an LDMOS tube, wherein a grid electrode of the LDMOS tube is coupled to the RC delay network. The high-voltage ESD protection circuit is simple in structure, compatible with a BCD (bipolar transistor diode) process and high in reliability.

Description

High-voltage ESD protection circuit

Technical Field

The invention relates to the technical field of integrated circuit electrostatic protection, in particular to a high-voltage ESD protection circuit.

Background

As integrated circuit manufacturing technology advances, feature sizes are shrinking, and ESD (Electro-static discharge) affects integrated circuits more and more. Statistically, the above failures of the integrated circuit 1/3 are caused by ESD, and in order to reduce the adverse effects of ESD on the integrated circuit and to improve the reliability and performance of the integrated circuit, the most effective method is to add ESD protection circuits. The ESD protection circuit can convert high-voltage static electricity into transient low-voltage heavy current to discharge the current, thereby achieving the purpose of protecting the integrated circuit. Therefore, the ESD protection circuit is designed to have a high working voltage, and therefore, the ESD performance and the reliability requirement are considered when designing the performance of the ESD protection circuit. In a common ESD protection circuit, a Silicon Controlled Rectifier (SCR) is used as an ESD protection device, or an auxiliary trigger circuit is used to trigger the SCR to implement ESD protection. For example, the electrostatic discharge protection structure disclosed in chinese patent application CN103378087A, as shown in fig. 1A, includes a well region counter-doped region 133, an n-well 121, a p-type substrate 110, a lateral silicon controlled rectifier SCR formed by a substrate counter-doped region 134, a communication region 135 communicating the p-type substrate 110 and the n-well 121, the n-well 121 extending into the p-type substrate 110 on the surface of the p-type substrate 110 and the n-well 121 to form a unidirectional diode, when electrostatic discharge occurs, an anode potential rises, a depletion region is formed in the p-type substrate 110 and the n-well 121, a field plate structure 161 electrically connected to a cathode as an electric field plate, a width of the depletion region on the surface of the p-type substrate 110 is limited by a width of the field plate structure 161 (i.e. a position of an edge of the field plate structure 161), as the anode voltage further rises, an electric field strength gradually increases until a breakdown voltage of the unidirectional diode is reached, a large number of electron-hole pairs, the silicon controlled rectifier SCR is triggered, an NPN triode formed by the substrate counter doping region 134, the p-type substrate 110 and the n well 121 and a PNP triode formed by the well counter doping region 133, the n well 121 and the p-type substrate 110 are conducted, an electrostatic discharge path is formed, and the effect of electrostatic discharge protection is achieved. For another example, as shown in fig. 1B, an embedded PMOS auxiliary trigger Silicon Controlled Rectifier (SCR) device disclosed in chinese patent application CN101789428A is formed by a first P + injection region 35 a-N well 33, a second N + injection region 34-P well 32, and a second P + injection region 35B-third N + injection region 37, which respectively form a P-N-P-N structure of a silicon controlled SCR, wherein the first N + injection region 34 and the first P + injection region 35a are connected by a metal wire as an electrical anode, the third N + injection region 37 and the third P + injection region 38 are as an electrical cathode, a PMOS gate is externally connected with an RC trigger circuit, and an RC time constant is about 1us, so as to ensure that the PMOS has enough on-time to assist triggering the SCR to discharge ESD current, and meanwhile, the PMOS cannot be turned on when being normally powered on. When an ESD signal appears at the anode, a larger voltage can cause avalanche breakdown of the N trap, the PN junction of the second N + injection region and the P trap, the generated avalanche current flows through a trap resistor R _ pwell of the P trap to generate a voltage drop, when the voltage drop is larger than the starting voltage of the parasitic NPN triode, the NPN parasitic triode is started, and simultaneously the PNP parasitic triode is also started due to positive feedback, the whole SCR device is conducted to start discharging the ESD current, the voltage of the two ends of the SCR is clamped at a lower potential, the lower breakdown voltage of the P trap/N + junction can be realized due to the arrangement of the second N + injection region, the parallel PMOS structure is started due to the fact that the ESD high potential appearing at the anode (namely a PMOS source) and the low potential caused by the RC delay of a grid electrode form a voltage difference, the auxiliary current flows into the P trap from the N trap, and the current caused by the PMOS generates the voltage drop through the.

The ESD protection devices triggered by SCR described above have the following disadvantages:

1) although the ESD protection devices have the advantages of small structural area and strong discharge capacity, the compatibility and reliability of the ESD protection devices are often difficult to verify due to the use of parasitic paths and structures;

2) the trigger circuit is also manufactured in an abnormal way, and the reliability of the trigger circuit is to be verified.

3) There is also a risk of latch-up which is difficult to control.

To circumvent the latchup risk of SCR, ESD bleed circuits using some conventional devices have been studied and published. For example, U.S. patent application No. US 8913359B2 discloses an electrostatic discharge protection device BASED on RC LATCH-UP Free RC-BASED NMOS ESD POWER-CLAMP IN HV USE, as shown in fig. 1C, the ESD protection device with RC structure can discharge ESD circuit through RC trigger circuit, but there is still a reliability problem in BCD process (i.e. monolithic integration process for simultaneously manufacturing bipolar device and CMOS device on the same chip), because the gate withstand voltage of LDMOS device in BCD process is only 5V, and its

inverter structures

24, 26, 28 must bear the high voltage of VDD during normal operation, otherwise, it cannot work, such requirement can only be used in general HV process (i.e. high voltage CMOS manufacturing process), and BCD process has no such device, and therefore cannot be realized. FOR example, an ELECTROSTATIC DISCHARGE PROTECTION device (ELECTROSTATIC DISCHARGE PROTECTION device FOR HIGH VOLTAGE capacitor DOMIANS) disclosed in U.S. patent application No. US8830641B2, as shown in fig. 1D, a structure of full network stack is used to solve the reliability problem of HV (HIGH VOLTAGE) process, and the VOLTAGE endurance problem of an inverter structure is mainly avoided by using a stack structure of a plurality of common devices, but all the devices are stacked structures and are too complicated, if the devices are used in a BCD process, the advantages of the LDMOS device are not considered, and the implementation area is also large.

Therefore, it is an urgent technical problem to be solved by those skilled in the art to provide a high voltage ESD protection circuit structure with good compatibility and high reliability.

Disclosure of Invention

The invention aims to provide a high-voltage ESD circuit which is compatible with a BCD (bipolar transistor-diode) process and has high reliability.

In order to solve the above problems, the present invention provides a high voltage ESD protection circuit, which includes a bias circuit, an ESD trigger circuit, and an ESD discharging circuit, which are disposed between a high voltage power line and a ground line and coupled in sequence, wherein the bias circuit is provided with a plurality of voltage dividing nodes; the ESD trigger circuit is mainly composed of an RC delay network connected by at least one resistor and a plurality of capacitors, and each capacitor is correspondingly coupled to a voltage division node of the bias circuit; the ESD release circuit is mainly composed of an LDMOS tube, wherein a grid electrode of the LDMOS tube is coupled to the RC delay network.

Further, the bias circuit is composed of a plurality of voltage dividing resistors connected in series between the high-voltage power supply line and the ground line.

Further, the RC delay network is composed of a trigger resistor and a plurality of capacitors connected in series between the high voltage power line and the ground line in sequence.

Further, the number of the capacitors connected in series in the RC delay network is the same as the number of the voltage dividing resistors in the bias circuit.

Furthermore, the number of the capacitors and the number of the voltage dividing resistors are both 4.

Furthermore, one end of a capacitor directly connected in series with the trigger resistor in the RC delay network is coupled to the gate of the LDMOS transistor, and the other end of the capacitor is coupled to a first voltage dividing node at the high-voltage power line terminal in the bias circuit.

Further, the capacitance of the RC delay network is selected according to the voltage value of the voltage dividing node of the bias circuit coupled thereto.

Furthermore, the resistance values of the divider resistors in the bias circuit are the same, and the capacitance values of the capacitors in the RC delay network are the same.

Further, the capacitors in the RC delay network are all MIM (metal-insulator-metal) capacitors.

Further, the LDMOS transistor is a P-type MOS transistor.

Compared with the prior art, the high-voltage ESD protection circuit provided by the invention has the following beneficial effects:

1) the ESD release circuit is formed by the LDMOS transistor, a BCD (bipolar transistor-diode) process can be compatible without using a structure that low-voltage structures such as diodes are connected in series, and the LDMOS transistor is high in reliability.

2) An ESD trigger circuit of an RC delay network is directly adopted to trigger and push a driving signal to an LDMOS tube, so that the reliability problem of a driving part of an ESD discharge structure in the prior art is solved.

3) A bias circuit formed by serially connecting voltage-dividing resistors is adopted to bias the capacitor voltage division of the RC time-delay network, so that the voltage difference of an upper polar plate and a lower polar plate of the capacitor is ensured to be within the bearable range.

4) The bias circuit, the ESD trigger circuit and the ESD release circuit all use conventional high-voltage devices verified by a process, can be compatible with a BCD process, have no reliability problem and have no latch-up risk.

Drawings

Fig. 1A to 1D are schematic diagrams of ESD protection structures in the prior art;

FIG. 2 is a schematic diagram of a high voltage ESD protection circuit in accordance with an embodiment of the present invention;

FIG. 3 is a simulation diagram of the ESD result of the high voltage ESD protection circuit shown in FIG. 2;

fig. 4 is a TLP plot over a BCD process for the high voltage ESD protection circuit shown in fig. 2.

Detailed Description

The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.

Referring to fig. 2, the present invention provides a high voltage ESD protection circuit, which mainly comprises three parts disposed between and sequentially coupled to a high voltage power line HVDD and a ground line HVSS: a bias circuit 201, an ESD trigger circuit 202, and an ESD bleed circuit 203.

In this embodiment, the bias circuit 201 is used to bias the ESD trigger circuit 202 to provide a bias voltage thereto. The bias circuit 201 is mainly composed of 4 voltage dividing resistors R1, R2, R3 and R4 which are sequentially connected in series between a high-voltage power line HVDD and a ground line HVSS, a first voltage dividing node n1 is arranged between the voltage dividing resistors R1 and R2, a second voltage dividing node n2 is arranged between the voltage dividing resistors R2 and R3, and a third voltage dividing node n3 is arranged between the voltage dividing resistors R3 and R4.

In this embodiment, the ESD trigger circuit 202 is mainly composed of a trigger resistor R0 and 4 capacitors C1, C2, C3, and C4, which are sequentially connected in series between a high voltage power line HVDD and a ground line HVSS, and the trigger resistor R0 and the 4 capacitors C1, C2, C3, and C4 form an RC delay network, a series node p0 of the trigger resistor R0 and the capacitor C1 is coupled to the gate of the LDMOS transistor of the ESD bleeder circuit 203, a series node p1 of the capacitors C1 and C2 is coupled to a first voltage dividing node n1 of the bias circuit 201, a series node p2 of the capacitors C2 and C3 is coupled to a second voltage dividing node n2 of the bias circuit 201, and a series node p3 of the capacitors C3 and C4 is coupled to a third voltage dividing node n3 of the bias circuit 201. That is, one end of the capacitor C1 is coupled to the first voltage-dividing node n1 of the bias circuit 201, and the other end is coupled to the second voltage-dividing node n2 of the bias circuit 201, and the number of capacitors in the RC delay network of the ESD trigger circuit 202 is the same as the number of voltage-dividing resistors in the bias circuit 201, so that the selection of the capacitors in the RC delay network depends on the voltage value of the voltage-dividing node of the bias circuit 201 to which the capacitors are coupled. In this embodiment, the capacitors C1, C2, C3, and C4 may all be MIM capacitors, and the voltage dividing node in the bias circuit 201 may perform bias voltage division on the voltage on the capacitors, so as to ensure that the voltage difference between the upper and lower plates of the MIM capacitor is within the tolerable range of the MIM capacitor.

In this embodiment, the ESD protection circuit 203 adopts an LDMOS transistor to form an electrostatic discharge structure, and does not need to use a structure in which low-voltage structures such as diodes are connected in series in the prior art, and the process compatibility and reliability of the LDMOS transistor are utilized to ensure that the high-voltage ESD protection circuit is compatible with the BCD process, and improve the reliability thereof. Meanwhile, the RC time delay network is directly adopted to push driving signals to the high-voltage LDMOS transistor, and some variable frequency (INV) driving structures of a discharge structure in the prior art are eliminated, so that the reliability problem of a driving part is solved. The LDMOS transistor may be a P-type MOS transistor, and has a gate coupled to the node P0 of the ESD trigger circuit 202, a drain coupled to the ground line HVSS, and a source coupled to the high voltage power line HVDD.

As can be seen from the above, the bias circuit 201, the ESD trigger circuit 202, and the ESD bleeder circuit 203 of the high-voltage ESD protection circuit of the embodiment are all formed by conventional high-voltage devices, and therefore can be directly manufactured by the BCD process, wherein each voltage dividing resistor of the bias circuit 201 and the trigger resistor of the ESD trigger circuit 202 can be formed on the first layer plate M1 of the PCB circuit board, the ESD bleeder circuit 203 can be formed on the fourth layer plate M2 of the PCB circuit board, and the capacitors C1, C2, C3, and C4 of the ESD trigger circuit 202 can be formed on the fourth layer plate M4 of the PCB circuit board.

The working principle of the high-voltage ESD protection circuit is as follows:

when an ESD current enters the input terminal of the high-voltage power line HVDD, the bias circuit 201 provides a bias voltage to the ESD trigger circuit 202, and due to a certain delay generated by the RC delay network of the ESD trigger circuit 202, the voltage at the point P0 at the ESD event is smaller than the voltage of the HVDD, so that the gate voltage of the LDMOS transistor of the ESD discharge circuit 203 is smaller than the source voltage thereof, and the LDMOS transistor P opens the channel of the LDMOS transistor to discharge the ESD current entering the high-voltage power line HVDD.

Since the high-voltage ESD protection circuit of the present embodiment is constructed using a standard device structure, its ESD performance can be evaluated by simulation. Referring to fig. 3 and 4, fig. 3 and 4 show simulation test results of a 20V high voltage ESD protection circuit (i.e., 20V-ESD CLAMP). As can be seen from fig. 3, the ESD current discharged 1.33A is equivalent to 2KV HBM (human body mode, i.e., simulating the discharge of a human body to a sensitive device, testing the highest static voltage endured by the sensitive device, and determining the static level of the sensitive device), the HVDD peak voltage is only 15V, and completely conforms to the device operating voltage range of 20V, so that the performance is reliable. As can be seen from fig. 4, the 20V high voltage ESD protection circuit is fully in line with the design expectations on the 0.18 μmBCD process.

It should be noted that, in other embodiments of the present invention, because the application occasions of the high-voltage ESD protection circuit are different, the number of the voltage dividing resistors in the bias circuit 201 may be more than 4 or less than 4, and the resistance values of the voltage dividing resistors may not be completely the same or completely different, while the number of the capacitors in the ESD trigger circuit 202 may be increased or decreased adaptively, and the capacitance values of the capacitors may be changed adaptively according to the voltage of the voltage dividing node of the bias circuit 201 coupled thereto; in addition, an N-type LDMOS transistor can be adaptively selected in the ESD discharging circuit 203.

In conclusion, the high-voltage ESD protection circuit disclosed by the invention is simple in structure, high in reliability and compatible with a BCD (bipolar transistor-diode) process.

It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A high-voltage ESD protection circuit is characterized by comprising a bias circuit, an ESD trigger circuit and an ESD release circuit which are arranged between a high-voltage power line and a ground wire and are sequentially coupled, wherein the bias circuit is provided with a plurality of voltage division nodes; the ESD trigger circuit is mainly composed of an RC delay network connected by at least one resistor and a plurality of capacitors, and each capacitor is correspondingly coupled to a voltage division node of the bias circuit; the ESD release circuit is mainly composed of an LDMOS tube, wherein a grid electrode of the LDMOS tube is coupled to the RC delay network.

2. The high-voltage ESD protection circuit of claim 1, wherein the bias circuit is comprised of a plurality of voltage dividing resistors connected in series between the high-voltage power supply line and ground.

3. The high-voltage ESD protection circuit of claim 2, wherein said RC delay network is comprised of a trigger resistor and a plurality of capacitors connected in series between said high-voltage power line and ground.

4. The high-voltage ESD protection circuit of claim 3, wherein a number of capacitors in series in the RC delay network is the same as a number of voltage dividing resistors in the bias circuit.

5. The high-voltage ESD protection circuit according to claim 4, wherein the number of capacitors and the number of voltage dividing resistors are each 4.

6. The high-voltage ESD protection circuit of claim 3, wherein the capacitor in the RC delay network directly connected in series with the trigger resistor has one end coupled to the gate of the LDMOS transistor and the other end coupled to a first voltage-dividing node of the high-voltage power line terminal of the biasing circuit.

7. The high-voltage ESD protection circuit of claim 3, wherein the capacitance of the RC delay network is selected based on a voltage value of a voltage-dividing node of the bias circuit coupled thereto.

8. The high-voltage ESD protection circuit according to claim 4 or 7, wherein the resistances of the voltage dividing resistors in the bias circuit are the same, and the capacitances of the capacitors in the RC delay network are the same.

9. The high-voltage ESD protection circuit of claim 1, wherein the capacitors in the RC delay network are MIM capacitors.

10. The high-voltage ESD protection circuit of claim 1, wherein the LDMOS transistor is a P-type MOS transistor.