CN1381885A - I/O port with high voltage tolerance and electrostatic discharge protection circuit - Google Patents
I/O port with high voltage tolerance and electrostatic discharge protection circuit Download PDFInfo
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- CN1381885A CN1381885A CN 01110716 CN01110716A CN1381885A CN 1381885 A CN1381885 A CN 1381885A CN 01110716 CN01110716 CN 01110716 CN 01110716 A CN01110716 A CN 01110716A CN 1381885 A CN1381885 A CN 1381885A
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Abstract
An I/O port with high voltage tolerance and related electrostatic discharge protector circuit are disclosed. The said I/O port coupled to a connection pad of an IC is composed of a voltage divider circuit and a switch circuit, and the said voltage divider circu8it coupled and the said connection pad to generate a reference voltage lower than the voltage of connection pad. The said switch circuit has a controlling grid. The said grid can reduce the stress of oxidized layer under grid, so allowing higher voltage.
Description
The invention relates to the high-tension output/input port of a kind of tolerable (highvoltage tolerance input/output port), refer to especially a kind of can allowable input voltage greater than the I/O port of the supply voltage of integrated circuit and relevant ESD protection circuit.
Along with the evolution of semiconductor technology, the characteristic size on the semiconductor chip (feature size) constantly reduces, and the employed supply voltage of integrated circuit also and then reduces.But when often a new integrated circuit occurred, the external integrated circuit that is associated was to use old semiconductor technology more, just uses higher supply voltage.What therefore, the I/O port of new integrated circuit just must design can accept the bigger voltage of extraneous input, the environment that is used for reality that can be real.
See also the 1st figure, the 1st figure is a kind of circuit diagram of existing I/O port.A kind of existing output/input port is to use two clamp diodes (clampingdiode) 10,12 to come the voltage of clamper joint sheet (pad) 14 in the internal circuit 16, makes the magnitude of voltage that is received in the internal circuit 16 can not surpass the value of power vd D and power supply VSS.But, when so output/input port runs into the external world and sends into than the high voltage of power vd D, the compulsory filling electricity of power vd D meeting (charge up), can cause the malfunction (mis-fuction) of internal circuit, so as the 1st figure as circuit be to be used as a high-tension output/input port of tolerable.
See also the 2nd figure and the 3rd figure, the 2nd figure is the circuit diagram that a kind of existing input port adds two semiconductor controlled rectifiers, and the 3rd figure is the chip profile schematic diagram of the semiconductor controlled rectifier among the 2nd figure.Existing input port also can cause the problem of gate oxide aging (gate oxide aging) except meeting causes the malfunction of internal circuit.Shown in the 2nd figure, in case occurred being higher than the burning voltage of power vd D on the joint sheet 14, such high voltage just can come across all contacts that link to each other with joint sheet 14, for example the grid of the n type MOS (metal-oxide-semiconductor) transistor 18 of input port and an end of two semiconductor controlled rectifiers 20.Because in the consideration of semiconductor technology, the gate oxide of n type MOS (metal-oxide-semiconductor) transistor 18 all is that the magnitude of voltage that is about as much as power vd D is born in design, just can impel gate oxide aging rapidly so steady voltage difference that is higher than power vd D appears on the gate oxide of n type MOS (metal-oxide-semiconductor) transistor 18, the result is that the reliability of the gate oxide (as 22 zones that indicated) of n type MOS (metal-oxide-semiconductor) transistor 18 has problem.Identical reason, the n type MOS (metal-oxide-semiconductor) transistor 24 in the semiconductor controlled rectifier also has the same problem, shown in the 3rd figure.The voltage of joint sheet 14 has passed through a source/drain electrode 25 that n type well is transmitted to n type MOS (metal-oxide-semiconductor) transistor 24, and the grid of n type MOS (metal-oxide-semiconductor) transistor 24 remains in the magnitude of voltage (promptly being ground connection) of power supply VSS, in case so the voltage of joint sheet 14 continue remain on high potential, the gate oxide in 26 zones that indicated just has aging problem.
See also the 4th figure, the 4th figure is the high-tension I/O port of a kind of existing tolerable.In order to solve the aging problem of gate oxide, there is the method for many kinds all to be delivered, but must increases technologic complexity often.Shown in the 4th figure, a kind of solution is in joint sheet 14 and vague and general formula n type MOS (metal-oxide-semiconductor) transistor 32 of 30 serial connections of internal circuit, be used for stopping that the voltage that is higher than power vd D on the joint sheet 14 arrives the grid place of internal circuit 30, aging to prevent gate oxide.But so method certainly will be added one mask and relevant ion implantation technology in semiconductor technology, has increased the cost of technology.
In view of this, main purpose of the present invention is to provide high-tension I/O port of a kind of tolerable and ESD protection circuit.ESD protection circuit of the present invention is in order to discharge the electrostatic stress on the joint sheet.Under the condition that does not change semiconductor technology, after the design via circuit, the voltage difference on the gate oxide in the n type MOS (metal-oxide-semiconductor) transistor in the output/input port no longer has the situation greater than power vd D, so there is not the aging problem of gate oxide.
The present invention reaches by following measure:
The high-tension I/O port of a kind of tolerable is coupled in a joint sheet of an integrated circuit, and it includes:
One bleeder circuit is coupled in this joint sheet, and according to the voltage on this joint sheet to produce one
Than the little reference voltage of the voltage on this joint sheet; And
One switching circuit, it includes a control grid, and this control grid is according to this reference voltage
Control the switch of this switching circuit.
The high-tension ESD protection circuit of a kind of tolerable is coupled in a joint sheet of an integrated circuit, and it includes:
One bleeder circuit is coupled in this joint sheet, and according to the voltage on this joint sheet to produce one
Than the little reference voltage of the voltage on this joint sheet; And
Semiconductor control rectifier is coupled in this joint sheet, and it includes one the one n type gold oxygen
Semitransistor, the grid of a n type MOS (metal-oxide-semiconductor) transistor is to touch according to this reference voltage
Send out this semiconductor controlled rectifier and reach the purpose of static discharge.
According to above-mentioned purpose, the present invention proposes the high-tension I/O port of a kind of tolerable, is coupled in a joint sheet of an integrated circuit.I/O port includes a bleeder circuit and a switching circuit.Bleeder circuit is coupled on the joint sheet, and according to the voltage on the joint sheet to produce a reference voltage little than the voltage on the joint sheet.Switching circuit includes a control grid, and the control grid is a switch of controlling this switching circuit according to reference voltage.
The present invention provides an ESD protection circuit in addition, in order to discharge the electrostatic stress on the joint sheet.ESD protection circuit is coupled to an internal circuit and a joint sheet.ESD protection circuit has comprised a bleeder circuit and semiconductor control rectifier.Bleeder circuit is coupled in joint sheet, and according to the voltage on the joint sheet to produce a reference voltage little than the voltage on the joint sheet.Semiconductor controlled rectifier is coupled in joint sheet, includes one the one n type MOS (metal-oxide-semiconductor) transistor.The grid of the one n type MOS (metal-oxide-semiconductor) transistor is the purpose that reaches static discharge according to reference voltage to trigger semiconductor controlled rectifier 54.
The structure of semiconductor rectifier includes a p type substrate, a n type wellblock, a p type doped region, a n type contact zone, a n type doped region, a p type contact zone, one the 2nd n type MOS (metal-oxide-semiconductor) transistor and a n type MOS (metal-oxide-semiconductor) transistor.N type wellblock is located in the substrate of p type, and forms a pn interface.The one n type MOS (metal-oxide-semiconductor) transistor is located in the substrate of p type, and a source/drain electrode of a n type MOS (metal-oxide-semiconductor) transistor is to be located on the pn interface.P type doped region and n type contact zone all are located in the n type wellblock, and coupled in common is in joint sheet.N type doped region and p type contact zone are located in the substrate of p type, and coupled in common is in a power port.The 2nd n type MOS (metal-oxide-semiconductor) transistor is connected in series with a n type MOS (metal-oxide-semiconductor) transistor, and is located at the p type substrate surface between a n type doped region and the n type MOS (metal-oxide-semiconductor) transistor.Wherein the grid of the 2nd n type MOS (metal-oxide-semiconductor) transistor and a source/drain electrode are to be coupled in n type doped region.
The present invention also provides many kinds of methods to implement bleeder circuit among the present invention, and main notion is to make reference voltage that bleeder circuit produced be no more than the working voltage value of integrated circuit, prevents the problem that gate oxide is aging.Bleeder circuit can be forward to be connected in series to a power port by joint sheet with a plurality of diodes to be constituted, and reference voltage is exactly a magnitude of voltage of being pulled out by one in diode serial connection point.Bleeder circuit can constitute with the series connection of two resistance, and reference voltage is exactly the serial connection point voltage of two resistance.The same reason, bleeder circuit can be that a plurality of diodes blend together to be connected in series with at least one resistance and form, and one of them is connected in series point voltage promptly is reference voltage.
Each diode among the present invention can be a pn junction diode, golden oxygen half diode and one of them person of Schottky diode.
Compared to existing output/input port, the invention has the advantages that does not need to change under the situation of semiconductor technology, via the design on the circuit, can allow that just the high voltage of the employed voltage of integrated circuit appears using in joint sheet.Because bleeder circuit provides one all the time less than the little reference voltage of the voltage on the joint sheet,, therefore, do not have the aging problem of gate oxide again so the control grid of switching circuit just can reduce the stress to the gate oxide under the control grid.And ESD protection circuit provided by the invention can discharge the electrostatic stress on the joint sheet.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
The 1st figure is a kind of circuit diagram of existing I/O port; The 2nd figure is the circuit diagram that a kind of existing input port adds two semiconductor controlled rectifiers; The 3rd figure is the chip profile schematic diagram of the semiconductor controlled rectifier among the 2nd figure; The 4th figure is the high-tension I/O port of a kind of existing tolerable; The 5th figure is according to output of the present invention/input port schematic diagram; The 6th figure is the circuit diagram of ESD protection circuit of the present invention; The 7th figure is the chip profile figure of the ESD protection circuit of the 6th figure; 8a figure is that 8h figure is the various embodiment schematic diagrames of the bleeder circuit among the 7th figure. symbol description: 68 N-shaped doped regions, 70 p-type contact zones, 64 p-type doped regions, 66 N-shaped contact zones, 40 output/input port 42 joint sheets, 44 bleeder circuit 46 on-off circuits, 47 ESD protection circuit 48 N-shaped MOS transistors, 50 internal circuit 52 first N-shaped MOS transistors, 54 semiconductor rectifier 60 p-type substrates, 62 N-shaped wellblock, 72 second N-shaped MOS transistors, 74 VSS power ports, 80 diodes, 82 resistance, 84 current sources, 86 electric capacity
See also the 5th figure, the 5th figure is according to output of the present invention/input port schematic diagram.The present invention proposes the high-tension I/O port 40 of a kind of tolerable, is coupled in a joint sheet 42 of an integrated circuit.I/O port 40 includes a bleeder circuit 44 and a switching circuit 46.Bleeder circuit 44 is coupled on the joint sheet 42, and according to the voltage on the joint sheet 42 to produce a reference voltage little than the voltage on the joint sheet 42.Switching circuit 46 includes a control grid, such as the grid of the n type MOS (metal-oxide-semiconductor) transistor 48 on the 5th figure, and the control grid is the switch according to reference voltage control switch circuit 46.
For example, switching circuit 46 can be the reverser of the CMOS of an input port, and reverser is made of p type MOS (metal-oxide-semiconductor) transistor and n type MOS (metal-oxide-semiconductor) transistor, and at this moment, the control grid is exactly the grid of n type MOS (metal-oxide-semiconductor) transistor.Because reference voltage is littler than the voltage on the joint sheet, so the gate oxide under the grid of n type MOS (metal-oxide-semiconductor) transistor does not have aging problem.
See also the 6th figure, the 6th figure is the circuit diagram of ESD protection circuit of the present invention.The present invention also can be used for an ESD protection circuit 47, in order to discharge the electrostatic stress on the joint sheet 42.Shown in the 6th figure, ESD protection circuit 47 is coupled to an internal circuit 50 and a joint sheet 42.ESD protection circuit 47 has comprised a bleeder circuit 44 and semiconductor control rectifier 54.Bleeder circuit 44 is coupled in joint sheet 42, and according to joint sheet 42 voltages to produce a reference voltage little than the voltage on the joint sheet 42.Semiconductor controlled rectifier 54 is coupled in joint sheet 42, includes one the one n type MOS (metal-oxide-semiconductor) transistor 52.The grid of the one n type MOS (metal-oxide-semiconductor) transistor 52 is the purposes that reach static discharge according to reference voltage to trigger semiconductor controlled rectifier 54.
See also the 7th figure, the 7th figure is the chip profile figure of the ESD protection circuit of the 6th figure.The structure of semiconductor rectifier includes a p type substrate 60, a n type wellblock 62, a p type doped region 64, a n type contact zone 66, a n type doped region 68, a p type contact zone 70, one the 2nd n type MOS (metal-oxide-semiconductor) transistor 72 and a n type MOS (metal-oxide-semiconductor) transistor 52.N type wellblock 62 is located in the p type substrate 60, and forms a pn interface.The one n type MOS (metal-oxide-semiconductor) transistor 52 is located in the p type substrate 60, and a source/drain electrode of a n type MOS (metal-oxide-semiconductor) transistor 52 is to be located on the pn interface.P type doped region 64 all is located in the n type wellblock 62 with n type contact zone 66, and coupled in common is in joint sheet 42.N type doped region 68 is located in the p type substrate 60 with p type contact zone 70, and coupled in common is in a power port, as the VSS power port 74 among the 6th figure.The 2nd n type MOS (metal-oxide-semiconductor) transistor 72 is connected in series with a n type MOS (metal-oxide-semiconductor) transistor 52, and is located at p type substrate 60 surfaces between a n type doped region 68 and the n type MOS (metal-oxide-semiconductor) transistor 52.The grid of the 2nd n type MOS (metal-oxide-semiconductor) transistor 72 and a source/drain electrode are to be coupled in n type doped region 68.
The present invention also provides many kinds of methods to implement bleeder circuit 44 among the present invention, main notion is the working voltage value that the reference voltage that makes bleeder circuit 44 be produced is no more than integrated circuit, as the magnitude of voltage on the VDD power port, with the problem that prevents that gate oxide is aging.
See also 8a figure, 8a figure is the schematic diagram when bleeder circuit constitutes with diode among the 7th figure.Bleeder circuit 44 can be forward to be connected in series to a power port (as the VSS power port 74 among the figure) by joint sheet 42 with a plurality of diodes 80 to be constituted.Reference voltage is exactly the magnitude of voltage of being pulled out by one in the diode 80 serial connection point.A diode 80 approximately can provide 0.7 volt voltage drop, if between the grid of joint sheet 42 to the one n type MOS (metal-oxide-semiconductor) transistor 52 N diode 80 arranged, then the suffered reference voltage of the grid of a n type MOS (metal-oxide-semiconductor) transistor 52 lacks the magnitude of voltage of N*0.7 volt to I haven't seen you for ages than the voltage on the joint sheet 42.
See also 8b figure, 8b figure is the schematic diagram when bleeder circuit constitutes with diode and resistance among the 7th figure.Bleeder circuit 44 is after forward being connected in series by joint sheet 42 with a plurality of diodes 80, being coupled to VSS power port 74 through a resistance 82 again and constituting, and reference voltage is a plurality of diodes 80 and the point voltage that is connected in series of resistance 82.
See also 8c figure, 8c figure is the schematic diagram when bleeder circuit constitutes with resistance among the 7th figure.Bleeder circuit 44 can be connected serially to VSS power port 74 with two resistance 82 and constitute, and reference voltage is exactly the serial connection point voltage of two resistance 82.The same reason, bleeder circuit 44 can be that a plurality of diodes blend together to be connected in series with at least one resistance and form, and one of them is connected in series point voltage promptly is reference voltage.
Each diode among the present invention can be a pn junction diode, golden oxygen half diode and one of them person of Schottky diode, as long as select according to designer's demand.
See also 8d figure, 8d figure is the schematic diagram when bleeder circuit constitutes with a plurality of diodes and a current source among the 7th figure.Bleeder circuit 44 can be with a plurality of diodes 80 by joint sheet along 42 after serial connection, is connected in series a current source 84 to VSS power ports 74 again and constitutes, and reference voltage is a diode 80 and the point voltage that is connected in series of current source 84.
See also 8g figure, 8g figure is the schematic diagram when bleeder circuit constitutes with two electric capacity among the 7th figure.Bleeder circuit 44 is made of joint sheet 42 serial connection to VSS power ports 74 with two electric capacity 86.Reference voltage is the serial connection point voltage in two electric capacity 86.If the capacitance of an electric capacity 86 is M, and the capacitance of another electric capacity 86 is N, then reference voltage can be calculated by the dividing potential drop of electric capacity and learn, for the voltage on the joint sheet 42 multiply by M/ (M+N), therefore can design according to demand.
In order to obtain a bigger capacitance, preventing the interference of some parasitic capacitances, so each electric capacity 86 can constitute with a reverse diode 80, shown in 8h figure.Diode 80 can oppositely mix the district with a wellblock and one of them and constitute, such as n type well and p type wherein mix the district, and so capacitance can be than greatly and be easy to control.
Output of the present invention/input port uses a bleeder circuit 44 that the voltage on the joint sheet 42 is done the action of dividing potential drop, provide then one than the little reference voltage of the voltage on the joint sheet 42 to switching circuit 46, come the switch of control switch circuit 46.So,,, and the aging problem of gate oxide is arranged just switching circuit 46 can not be subjected to the injury of too high voltage if provide one during when external circuit than the high voltage of the employed voltage source of integrated circuit.When switching circuit 46 was an ESD protection circuit, output/input port of the present invention also can prevent to be responsible in the ESD protection circuit gate oxide problem of the n type MOS (metal-oxide-semiconductor) transistor of triggering, and reached the purpose of static discharge.The present invention has proposed many implementation methods simultaneously, can produce bleeder circuit 44, reaches the purpose of dividing potential drop.
Compared to existing output/input port, the invention has the advantages that does not need to change under the situation of semiconductor technology, via the design on the circuit, can allow that just the high voltage of the employed voltage of integrated circuit appears using in joint sheet.Because bleeder circuit provides one all the time less than the little reference voltage of the voltage on the joint sheet,, therefore, do not have the aging problem of gate oxide again so the control grid of switching circuit just can reduce the stress to the gate oxide under the control grid.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking claim of the present invention and being as the criterion in conjunction with specification and accompanying drawing.
Claims (22)
1. high-tension I/O port of tolerable is coupled in a joint sheet of an integrated circuit, it is characterized in that: include:
One bleeder circuit is coupled in this joint sheet, and according to the voltage on this joint sheet to produce one
Than the little reference voltage of the voltage on this joint sheet; And
One switching circuit, it includes a control grid, and this control grid is according to this reference voltage
Control the switch of this switching circuit.
2. output/input port as claimed in claim 1, it is characterized in that: this switching circuit is the reverser of a CMOS, this reverser is made of a p type MOS (metal-oxide-semiconductor) transistor and a n type MOS (metal-oxide-semiconductor) transistor, and this control gate grid of n type MOS (metal-oxide-semiconductor) transistor very.
3. output/input port as claimed in claim 1 is characterized in that: the reference voltage that this bleeder circuit produced can not surpass the working voltage value of this integrated circuit.
4. output/input port as claimed in claim 1 is characterized in that: this bleeder circuit is forward to be connected in series to a power port by this joint sheet with a plurality of diodes to be constituted, and this reference voltage is the voltage of a serial connection point in these diodes.
5. output/input port as claimed in claim 4 is characterized in that: each diode is a pn junction diode, golden oxygen half diode and one of them person of Schottky diode.
6. output/input port as claimed in claim 1, it is characterized in that: this bleeder circuit is after forward being connected in series by this joint sheet with a plurality of diodes, be coupled to a power port through a resistance again and constitute, and this reference voltage is these a plurality of diodes and the point voltage that is connected in series of this resistance.
7. output/input port as claimed in claim 1 is characterized in that: this bleeder circuit is made of this joint sheet serial connection to power port with two resistance, and the serial connection point voltage that this reference voltage is this two resistance.
8. output/input port as claimed in claim 1, it is characterized in that: this bleeder circuit is after forward being connected in series by this joint sheet with a plurality of diodes, be connected in series current source to a power port again and constitute, and this reference voltage is these diodes and the point voltage that is connected in series of this current source.
9. output/input port as claimed in claim 8, it is characterized in that: this current source is a MOS (metal-oxide-semiconductor) transistor, one source/drain electrode of this MOS (metal-oxide-semiconductor) transistor is an end that is connected in the diode of these serial connections, and another source/drain electrode of this MOS (metal-oxide-semiconductor) transistor is to be connected in this power port, and this MOS (metal-oxide-semiconductor) transistor is to be biased in the inferior beginning zone of opening.
10. output/input port as claimed in claim 1 is characterized in that: this bleeder circuit is made of this joint sheet serial connection to power port with two electric capacity, and this reference voltage is the serial connection point voltage in this two electric capacity.
11. output/input port as claimed in claim 10 is characterized in that: each these electric capacity is constituted with a reverse diode.
12. the high-tension ESD protection circuit of tolerable is coupled in a joint sheet of an integrated circuit, it is characterized in that: include:
One bleeder circuit is coupled in this joint sheet, and according to the voltage on this joint sheet to produce one
Than the little reference voltage of the voltage on this joint sheet; And
Semiconductor control rectifier is coupled in this joint sheet, and it includes one the one n type gold oxygen
Semitransistor, the grid of a n type MOS (metal-oxide-semiconductor) transistor is to touch according to this reference voltage
Send out this semiconductor controlled rectifier and reach the purpose of static discharge.
13. ESD protection circuit as claimed in claim 12 is characterized in that: this semiconductor controlled rectifier includes:
One p type substrate;
One n type wellblock is located in this p type substrate, and forms a pn interface, wherein this first
N type MOS (metal-oxide-semiconductor) transistor is to be located in this p type substrate, and n type gold oxygen semi-crystal
One source/drain electrode of pipe is to be located on this pn interface;
One p type doped region is located in this n type wellblock;
One n type contact zone is located in this n type wellblock, this n type contact zone and this p type doped region
Be to be coupled in this joint sheet;
One n type doped region is located in this p type substrate;
One p type contact zone is located in this p type substrate, this p type contact zone and this n type doped region
Be to be coupled in a power port; And
One the 2nd n type MOS (metal-oxide-semiconductor) transistor that is connected in series with a n type MOS (metal-oxide-semiconductor) transistor is located at
P type substrate surface between this a n type doped region and the n type MOS (metal-oxide-semiconductor) transistor, and
The grid of the 2nd n type MOS (metal-oxide-semiconductor) transistor and a source/drain electrode are to be coupled in this n type to mix
The district.
14. ESD protection circuit as claimed in claim 12 is characterized in that: the reference voltage that this bleeder circuit produced can not surpass the working voltage value of this integrated circuit.
15. ESD protection circuit as claimed in claim 12 is characterized in that: this bleeder circuit is forward to be connected in series to a power port by this joint sheet with a plurality of diodes to be constituted, and this reference voltage is the voltage of a serial connection point in these diodes.
16. ESD protection circuit as claimed in claim 15 is characterized in that: each diode is a pn junction diode, golden oxygen half diode and one of them person of Schottky diode.
17. ESD protection circuit as claimed in claim 12; it is characterized in that: this bleeder circuit is after forward being connected in series by this joint sheet with a plurality of diodes; be coupled to a power port through a resistance again and constitute, and this reference voltage is these a plurality of diodes and the point voltage that is connected in series of this resistance.
18. ESD protection circuit as claimed in claim 12 is characterized in that: this bleeder circuit is made of this joint sheet serial connection to power port with two resistance, and this reference voltage is the serial connection point voltage of this two resistance.
19. ESD protection circuit as claimed in claim 12; it is characterized in that: this bleeder circuit is after forward being connected in series by this joint sheet with a plurality of diodes; be connected in series current source to a power port again and constitute, and this reference voltage is these diodes and the point voltage that is connected in series of this current source.
20. ESD protection circuit as claimed in claim 19; it is characterized in that: this current source is a MOS (metal-oxide-semiconductor) transistor; one source/drain electrode of this MOS (metal-oxide-semiconductor) transistor is an end that is connected in the diode of these serial connections; and another source/drain electrode of this MOS (metal-oxide-semiconductor) transistor is to be connected in this power port, and this MOS (metal-oxide-semiconductor) transistor is to be biased in the inferior beginning zone of opening.
21. ESD protection circuit as claimed in claim 12 is characterized in that: this bleeder circuit is made of this joint sheet serial connection to power port with two electric capacity, and this reference voltage is the serial connection point voltage in this two electric capacity.
22. ESD protection circuit as claimed in claim 21 is characterized in that: each these electric capacity is constituted with a reverse diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01110716 CN1252814C (en) | 2001-04-13 | 2001-04-13 | I/O port with high voltage tolerance and electrostatic discharge protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01110716 CN1252814C (en) | 2001-04-13 | 2001-04-13 | I/O port with high voltage tolerance and electrostatic discharge protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1381885A true CN1381885A (en) | 2002-11-27 |
| CN1252814C CN1252814C (en) | 2006-04-19 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01110716 Expired - Fee Related CN1252814C (en) | 2001-04-13 | 2001-04-13 | I/O port with high voltage tolerance and electrostatic discharge protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1252814C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297002C (en) * | 2003-02-14 | 2007-01-24 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection circuit |
| CN100442510C (en) * | 2005-08-26 | 2008-12-10 | 联咏科技股份有限公司 | Static discharging protection circuit for collimation shifter considering power starting sequence |
| CN100485922C (en) * | 2003-08-20 | 2009-05-06 | 台湾积体电路制造股份有限公司 | Static discharge protection sensor and circuit |
| CN102693978A (en) * | 2011-03-25 | 2012-09-26 | 瑞昱半导体股份有限公司 | Electrostatic discharge protection circuit |
| CN106558582A (en) * | 2016-11-22 | 2017-04-05 | 北京时代民芯科技有限公司 | The Method and circuits that ESD to high-tension circuit is protected is realized based on low-voltage device |
| CN107946299A (en) * | 2017-12-14 | 2018-04-20 | 上海艾为电子技术股份有限公司 | A kind of load switch and electronic equipment |
| CN112764451A (en) * | 2019-10-21 | 2021-05-07 | 圣邦微电子（北京）股份有限公司 | Protection circuit for improving withstand voltage of logic input port |
| CN114079420A (en) * | 2020-08-13 | 2022-02-22 | 致新科技股份有限公司 | Overvoltage protection circuit |
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2001
- 2001-04-13 CN CN 01110716 patent/CN1252814C/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297002C (en) * | 2003-02-14 | 2007-01-24 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection circuit |
| CN100485922C (en) * | 2003-08-20 | 2009-05-06 | 台湾积体电路制造股份有限公司 | Static discharge protection sensor and circuit |
| US7583484B2 (en) | 2003-08-20 | 2009-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit and method for ESD protection |
| CN100442510C (en) * | 2005-08-26 | 2008-12-10 | 联咏科技股份有限公司 | Static discharging protection circuit for collimation shifter considering power starting sequence |
| CN102693978A (en) * | 2011-03-25 | 2012-09-26 | 瑞昱半导体股份有限公司 | Electrostatic discharge protection circuit |
| CN102693978B (en) * | 2011-03-25 | 2015-05-20 | 瑞昱半导体股份有限公司 | Electrostatic discharge protection circuit |
| CN106558582A (en) * | 2016-11-22 | 2017-04-05 | 北京时代民芯科技有限公司 | The Method and circuits that ESD to high-tension circuit is protected is realized based on low-voltage device |
| CN106558582B (en) * | 2016-11-22 | 2019-06-04 | 北京时代民芯科技有限公司 | The method and circuit of the ESD protection to high-tension circuit are realized based on low-voltage device |
| CN107946299A (en) * | 2017-12-14 | 2018-04-20 | 上海艾为电子技术股份有限公司 | A kind of load switch and electronic equipment |
| CN107946299B (en) * | 2017-12-14 | 2020-06-02 | 上海艾为电子技术股份有限公司 | Load switch and electronic equipment |
| CN112764451A (en) * | 2019-10-21 | 2021-05-07 | 圣邦微电子（北京）股份有限公司 | Protection circuit for improving withstand voltage of logic input port |
| CN114079420A (en) * | 2020-08-13 | 2022-02-22 | 致新科技股份有限公司 | Overvoltage protection circuit |
Also Published As
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| CN1252814C (en) | 2006-04-19 |
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