CN106558582B - The method and circuit of the ESD protection to high-tension circuit are realized based on low-voltage device - Google Patents

The method and circuit of the ESD protection to high-tension circuit are realized based on low-voltage device Download PDF

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Publication number
CN106558582B
CN106558582B CN201611046358.3A CN201611046358A CN106558582B CN 106558582 B CN106558582 B CN 106558582B CN 201611046358 A CN201611046358 A CN 201611046358A CN 106558582 B CN106558582 B CN 106558582B
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voltage
grid
circuit
bias voltage
capacitor
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CN201611046358.3A
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Chinese (zh)
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CN106558582A (en
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张硕
王宗民
张铁良
王瑛
周亮
冯文晓
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北京时代民芯科技有限公司
北京微电子技术研究所
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Abstract

It is realized based on low-voltage device to the ESD of the high-tension circuit method protected and circuit the invention discloses a kind of; wherein, which comprises when capacitor C0 receives esd pulse, generate charging current; pressure drop is generated on resistance R0, controls the second PMOS transistor MP1 and third PMOS transistor is opened;When the output voltage Vb1 exported by the second PMOS transistor MP1 and the first NMOS transistor MN0 is high level, and, when bias voltage Vb2 by third PMOS transistor MP2 and the first PMOS transistor MP0 output is high level, open third NMOS transistor MN2 and the second NMOS transistor MN1, leakage current.The ESD protection capability for improving chip through the invention ensure that the yield rate and reliability of chip.

Description

The method and circuit of the ESD protection to high-tension circuit are realized based on low-voltage device

Technical field

The invention belongs to field of circuit technology more particularly to a kind of ESD guarantors realized based on low-voltage device to high-tension circuit The method and circuit of shield.

Background technique

Static discharge (Electro Static Discharge, ESD) refer to limited charge two short distances, simultaneously And the event shifted between the object with different electrostatic potentials, the lifting of the electric current as caused by the event and potential is electrostatic Discharge the main object studied.

In the semiconductor industry, there are problems that the largely chip failure due to caused by static discharge phenomenon, according to statistics, The chip failure as caused by ESD accounts for about the 30%~50% of chip failure sum.In the production process of chip, transportational process In, even arrived system integration stage and user's service stage, all these processes are likely to generate on its pin quiet Discharge of electricity phenomenon, causes chip failure.Instantaneous large-current pulse caused by ESD flows through chip interior by chip pin, into And leads to chip interior line impairment and can not work normally.In addition, being potential there are also ESD damage suffered by segment chip , that is, the soft failure often said, this failure type be generally difficult to be found in test phase, but when final products are delivered to When in terminal user's hand, the service life of product will greatly reduce.

As it can be seen that how to realize that the ESD protection to chip, the yield rate of guarantee chip and reliability are those skilled in the art The problem of urgent need to resolve.

Summary of the invention

Technology of the invention solves the problems, such as: overcoming the deficiencies of the prior art and provide one kind and is realized based on low-voltage device to height The method and circuit of the ESD protection of volt circuit, it is intended to which the ESD protection capability for improving chip guarantees the yield rate of chip and reliable Property.

In order to solve the above-mentioned technical problem, the invention discloses a kind of ESD realized based on low-voltage device to high-tension circuit The method of protection, comprising:

When capacitor C0 receives esd pulse, charging current is generated, pressure drop is generated on resistance R0, the 2nd PMOS of control is brilliant Body pipe MP1 and third PMOS transistor MP2 is opened;

It is high level when passing through the output voltage Vb1 that the second PMOS transistor MP1 and the first NMOS transistor MN0 is exported, And when by the bias voltage Vb2 that third PMOS transistor MP2 and the first PMOS transistor MP0 are exported being high level, the is opened Three NMOS transistor MN2 and the second NMOS transistor MN1, leakage current.

In the above-mentioned method for realizing the ESD protection to high-tension circuit based on low-voltage device, the method also includes:

When the esd pulse on capacitor C0 disappears, the pressure drop on resistance R0 reduces, and controls MP1 and MP2 shutdown;

It is low level when passing through the output voltage Vb1 that MP1 and MN0 is exported, and, pass through the bias voltage that MP2 and MP0 is exported When Vb2 is low level, MN1 and MN2 is turned off.

In the above-mentioned method for realizing the ESD protection to high-tension circuit based on low-voltage device, the method also includes:

When capacitor C0 is without charging and discharging currents, without pressure drop on resistance R0, MP1 shutdown is controlled.

In the above-mentioned method for realizing the ESD protection to high-tension circuit based on low-voltage device, the company of resistance R0 and capacitor C0 Contact is connect with the grid of the grid of MP1 and MP2 respectively, the method also includes:

Grid voltage is provided for MP1 and MP2 by the tie point, and, grid voltage biasing is provided for MP2;Wherein, the grid voltage For controlling being switched on and off for MP1.

In the above-mentioned method for realizing the ESD protection to high-tension circuit based on low-voltage device, the method also includes:

Bias voltage Vb0 is exported to the grid of the grid of MN0 and MP0 respectively by biasing circuit VBIAS.

In the above-mentioned method for realizing the ESD protection to high-tension circuit based on low-voltage device, bias voltage Vb2 is more than or equal to The difference of supply voltage VDD and voltage rating;Wherein, the voltage rating are as follows: the gate-drain reversed bias voltage upper limit of MN1.

Correspondingly, the invention also discloses a kind of circuit realized based on low-voltage device and protected to the ESD of high-tension circuit, packet It includes: capacitor C0, resistance R0, MP0, MP1, MP2, MN0, MN1 and MN2;

Capacitor C0 and resistance R0 series connection;Wherein, capacitor C0, for generating discharge current when receiving esd pulse;Electricity R0 is hindered, for generating pressure drop when receiving the discharge current, MP1 and MP2 is controlled and opens;

The drain electrode of MP1 is connected with the drain electrode of MN0, for generating output voltage Vb1;Wherein, output voltage Vb1 export to The grid of MN2;The drain electrode of MP2 is connected with the source electrode of MP0, for generating bias voltage Vb2;Wherein, bias voltage Vb2 export to The grid of MN1;

The source electrode of MN1 is connected with the drain electrode of MN2;Wherein, MN1, for being opened when received bias voltage Vb2 is high level It opens, leakage current;MN2, for the unlatching when the output voltage Vb1 received is high level, leakage current.

In the above-mentioned circuit for realizing the ESD protection to high-tension circuit based on low-voltage device, the circuit further include: biasing Circuit VBIAS;

The biasing circuit VBIAS, for exporting bias voltage Vb0;Wherein, the bias voltage Vb0 export respectively to The grid of MN0 and the grid of MP0.

In the above-mentioned circuit for realizing the ESD protection to high-tension circuit based on low-voltage device, the company of capacitor C0 and resistance R0 Contact is connect with the grid of the grid of MP1 and MP2 respectively, for providing grid voltage for MP1 and MP2, and, grid voltage is provided for MP2 Biasing.

The invention has the following advantages that

(1) present invention has supplied GCNMOS (the Gate coupling NMOS) structure constituted based on MN0, MP1 and MN2 to realize ESD protection to high-tension circuit, the electric current that ESD is generated can pass through MOS (Metal Oxide Semiconductor, metal oxygen Compound semiconductor) pipe surface releases, and design is simple, charge discharging resisting ability is strong, opening speed is fast, versatile, improves chip ESD protection capability, ensure that the yield rate and reliability of chip, non-epitaxial and epitaxial wafer be applicable in, and can be real The substrate isolation of existing MN2, enhances the latch-up immunity of circuit.

(2) present invention can carry out comprehensive simulation on normal integrated circuit emulation tool, without the specific emulation of design Tool can determine the specifications parameter of each component by emulation, improve reliability while reducing design cost.

(3) present invention can be completed low-voltage device and tolerate high drain terminal voltage by adjusting the value of output voltage Vb2, have Stronger versatility is suitable under any technique, realizes that low-voltage device realizes the ESD protection of high-tension circuit in any circuit, special It is not the ESD protection for the composite signal integrated circuits in engineer application with more practical significance.

(4) present invention can call directly the component in standard cell lib as protection circuit without in addition design device In component, it is easy to accomplish.

Detailed description of the invention

Fig. 1 is a kind of knot for the circuit that the ESD protection to high-tension circuit is realized based on low-voltage device in the embodiment of the present invention Structure schematic diagram;

Fig. 2 is a kind of step for the method that the ESD protection to high-tension circuit is realized based on low-voltage device in the embodiment of the present invention Rapid flow chart.

Specific embodiment

To make the object, technical solutions and advantages of the present invention clearer, public to the present invention below in conjunction with attached drawing Embodiment is described in further detail.

Referring to Fig.1, it shows and a kind of in the embodiment of the present invention is realized based on low-voltage device to the ESD of high-tension circuit protection The structural schematic diagram of circuit.As shown in Figure 1, MP1 is connected with MN0 drain electrode constitutes inverter structure, output voltage Vb1, Vb1 are generated The grid of MN2 is connect, provides control voltage for MN2;The drain electrode of MP2 is connected with the source electrode of MP0 generates bias voltage Vb2, and Vb2 connects The grid of MN1 provides bias voltage for MN1;The source electrode of MN1 is connected with the drain electrode of MN2, constitutes electrostatic induced current and releases access;Partially The bias voltage Vb0 that circuits VBIAS is generated connects the grid of MN0 and the grid of MP0, provides grid voltage biasing for MN0 and MP0;Electricity Hold C0 be connected with resistance R0, the tie point of capacitor C0 and resistance R connects with the grid of the grid of MP1 and MP2 respectively, for MP1 with MP2 provides grid voltage, and control MP1 is opened and shut off, while providing grid voltage biasing for MP2.Wherein, MN0, MN1 and MN2 are NMOS (Negative channel-metal-oxide-semiconductor, N-type metal-oxide semiconductor (MOS)) transistor;MP0, MP1 and MP2 is that PMOS (partly lead by Positive channel-metal-oxide-semiconductor, p-type metal oxide Body) transistor.

In the present embodiment, the method that the ESD protection to high-tension circuit is realized based on low-voltage device can pass through base Realize that the circuit of the ESD protection to high-tension circuit is realized in low-voltage device.Referring to Fig. 2, show a kind of in the embodiment of the present invention The step flow chart of the method for the ESD protection to high-tension circuit is realized based on low-voltage device.In the present embodiment, described based on low The method that voltage device realizes the ESD protection to high-tension circuit can specifically include:

Step 201, when capacitor C0 receives esd pulse, charging current is generated, generates pressure drop on resistance R0, second PMOS transistor MP1 and third PMOS transistor MP2 is opened.

Step 202, when the output voltage Vb1 by the second PMOS transistor MP1 and the first NMOS transistor MN0 output is High level, and, it is high level by the bias voltage Vb2 that third PMOS transistor MP2 and the first PMOS transistor MP0 is exported When, open third NMOS transistor MN2 and the second NMOS transistor MN1, leakage current.

In the present embodiment, bias voltage Vb2 is more than or equal to the difference of supply voltage VDD and voltage rating;Wherein, described Voltage rating are as follows: the gate-drain reversed bias voltage upper limit of MN1.

On the basis of the above-mentioned method protected based on ESD of the low-voltage device realization to high-tension circuit, the method is also wrapped It includes:

Step 203, when the esd pulse on capacitor C0 disappears, the pressure drop on resistance R0 reduces, and controls MP1 and MP2 and closes It is disconnected.

It step 204, is low level when passing through the output voltage Vb1 that MP1 and MN0 is exported, and, pass through what MP2 and MP0 was exported When bias voltage Vb2 is low level, MN1 and MN2 is turned off.

On the basis of the above-mentioned method protected based on ESD of the low-voltage device realization to high-tension circuit, the method is also wrapped It includes:

Step 205, when capacitor C0 is without charging and discharging currents, without pressure drop on resistance R0, MP1 shutdown is controlled.

On the basis of the above-mentioned method protected based on ESD of the low-voltage device realization to high-tension circuit, the method is also wrapped It includes:

Step 206, bias voltage Vb0 is exported to the grid of the grid of MN0 and MP0 respectively by biasing circuit VBIAS.

Further, in conjunction with above-mentioned Fig. 1, the ESD protection to high-tension circuit is realized based on low-voltage device to described below Circuit is described in further detail.In the present embodiment, the circuit may include: capacitor C0, resistance R0, MP0, MP1, MP2, MN0, MN1 and MN2;It is specific:

Capacitor C0 and resistance R0 series connection;Wherein, capacitor C0, for generating charging current when receiving esd pulse;Electricity R0 is hindered, for generating pressure drop when receiving the charging current, control MP1 is opened;

The drain electrode of MP1 is connected with the drain electrode of MN0, for generating output voltage Vb1;Wherein, output voltage Vb1 export to The grid of MN2;The drain electrode of MP2 is connected with the source electrode of MP0, for generating bias voltage Vb2;Wherein, bias voltage Vb2 export to The grid of MN1;

The source electrode of MN1 is connected with the drain electrode of MN2;Wherein, MN1, for being opened when received bias voltage Vb2 is high level It opens, leakage current;MN2, for the unlatching when the output voltage Vb1 received is high level, leakage current.

The tie point of capacitor C0 and resistance R0 are connect with the grid of the grid of MP1 and MP2 respectively, for mentioning for MP1 and MP2 For grid voltage, and, grid voltage biasing is provided for MP2.

Further, as shown in Fig. 2, the circuit further include: biasing circuit VBIAS.The biasing circuit VBIAS is used In output bias voltage Vb0;Wherein, the bias voltage Vb0 exports the grid to the grid of MN0 and MP0 respectively.

In the present embodiment, MN0, MP1 and MN2 in circuit constitute GCNMOS (Gate coupling NMOS) structure, It realizes and the ESD of entire circuit is protected.Wherein, biasing circuit VBIAS provides bias voltage Vb0 for MN0;Output voltage Vb1 control Electric current bleeder pipe MN2's processed opens and shuts off;MP0 and MP1 series connection generates bias voltage Vb2, provides grid voltage for MN1.Wherein, it closes The value of reason design Vb2 can prevent MN2 gate-drain end to be reversed breakdown, and biasing circuit VBIAS provides bias voltage simultaneously for MP0 Vb0。

The circuit (hereinafter referred to as esd protection circuit) that the ESD protection to high-tension circuit is realized based on low-voltage device is main It may include two kinds of working conditions: esd protection circuit closed state (hereinafter referred to as state 1) and esd protection circuit opening state State (hereinafter referred to as state 2).

When state 1:

When chip is in power-down mode, entire chip internal circuits include that esd protection circuit is in floating state, institute There is device not work;When chip is in normal mode of operation, the working condition of esd protection circuit are as follows:

(1) capacitor C0 is without charging and discharging currents, then without pressure drop on R0 resistance, MP1 grid voltage is VDD, MP1 shutdown, output electricity Pressure Vb1 is low level, i.e. the grid voltage Vb1 of MN2 is low level, and MN2 shutdown does not generate leakage current.

(2) bias voltage Vb0 and MP0 generates bias voltage Vb2 jointly, and bias voltage Vb2 is used to guarantee the grid leak electricity of MN1 Pressure difference is within the patient maximum voltage of MN1 (namely upper voltage limit of MN1), to realize that low-voltage device tolerates high drain terminal electricity Pressure, such as: VDD=3.3V, MN1 can tolerate that maximum voltage is 2.5V, then Vb2 should be not less than 800mV.Rationally design the ruler of MN1 It is very little that the drain-source voltage difference of MN1 in this state is maintained in particular range, guarantee that MN2 gate-drain end is not reversed breakdown.

When state 2:

Due to ESD static discharge, vdd terminal generates esd pulse, and the upper voltage limit pulse of MN1 generates charging by capacitor C0 Electric current, charging current generate pressure drop on resistance R0, and MP1 is opened, and output voltage Vb1 and bias voltage Vb2 is high electricity at this time Flat, MN1 and MN2 are opened simultaneously, leakage current.As esd pulse disappears, the pressure drop on R0 becomes smaller, MP1 and MP2 shutdown, output Voltage Vb1 and bias voltage revert to low level, MN1 and MN2 shutdown.

Therefore in practical applications, it can be determined according to the demand of two kinds of working conditions of esd protection circuit each The specifications parameter of a device: determining the size of MN2 first, since MN2 is the transistor released as electric current, therefore, it is typically chosen Large-sized NMOS tube is as MN2, to guarantee that electric current is released speed;Likewise, select with the comparable NMOS tube of MN2 size as MN1.Then, it is determined that the bias voltage Vb2 of MN1, as described above, on the voltage that the size of bias voltage Vb2 can bear by MN1 Supply voltage VDD locating for limit and esd protection circuit is determined;Again, the ruler of MP2 and MP0 are determined according to the value of bias voltage Vb2 It is very little, and determine the output bias voltage Vb0 of biasing circuit VBIAS.Finally, according to the condition of above-mentioned determination, selection matching rule R0, C0, MP1 and MN0 of lattice parameter.Wherein, it should be noted that since MN1 and MN2 is series relationship, Vb2 and Vb1 Triggered time in state 2 should be consistent, therefore MP1, MN0 are suitable with the size needs of MP0 and MP2.Further, Ke Yitong It crosses normal integrated circuit emulation tool to verify the feasibility of circuit: the circuit is verified in state 1 by l-G simulation test With the working condition of state 2, each specifications parameter is adjusted repeatedly according to simulation result, to meet circuit actual requirement.

In conclusion scheme described in the embodiment of the present invention, is realized based on the GCNMOS structure that MN0, MP1 and MN2 are constituted ESD protection to high-tension circuit, the electric current that ESD is generated can be released by metal-oxide-semiconductor surface, design simple, charge discharging resisting ability By force, opening speed is fast, versatile, improves the ESD protection capability of chip, ensure that the yield rate and reliability of chip, right It is applicable in non-epitaxial and epitaxial wafer, and the substrate isolation of MN2 may be implemented, enhance the latch-up immunity of circuit.

Secondly, the present invention can carry out comprehensive simulation on normal integrated circuit emulation tool, it is specific imitative without design True tool can determine the specifications parameter of each component by emulation, improve reliability while reducing design cost.

Again, the present invention can be completed low-voltage device by adjusting the value of output voltage Vb2 and tolerate high drain terminal voltage, have There is stronger versatility, be suitable under any technique, realizes that low-voltage device realizes the ESD protection of high-tension circuit in any circuit, There is more practical significance especially for the ESD protection of the composite signal integrated circuits in engineer application.

Finally, the present invention without in addition design device, can call directly the component in standard cell lib as protection electricity Component in road, it is easy to accomplish.

The above, optimal specific embodiment only of the invention, but scope of protection of the present invention is not limited thereto, In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art, It should be covered by the protection scope of the present invention.

The content that description in the present invention is not described in detail belongs to the well-known technique of professional and technical personnel in the field.

Claims (7)

1. a kind of circuit of ESD protection characterized by comprising capacitor C0, resistance R0, MP0, MP1, MP2, MN0, MN1 and MN2;
Capacitor C0 and resistance R0 series connection;Wherein, capacitor C0, for generating charging current when receiving esd pulse;Resistance R0, For generating pressure drop when receiving discharge current, controls MP1 and MP2 and open;
The drain electrode of MP1 is connected with the drain electrode of MN0, for generating output voltage Vb1;Wherein, output voltage Vb1 is exported to MN2's Grid;The drain electrode of MP2 is connected with the source electrode of MP0, for generating bias voltage Vb2;Wherein, bias voltage Vb2 is exported to MN1's Grid;
The source electrode of MN1 is connected with the drain electrode of MN2;Wherein, MN1, for being opened when received bias voltage Vb2 is high level, Leakage current;MN2, for the unlatching when the output voltage Vb1 received is high level, leakage current;
Wherein, the circuit of the ESD protection, further includes: biasing circuit VBIAS;
The biasing circuit VBIAS, for exporting bias voltage Vb0;Wherein, the bias voltage Vb0 is exported respectively to MN0's The grid of grid and MP0;
Wherein, the tie point of capacitor C0 and resistance R0 are connect with the grid of the grid of MP1 and MP2 respectively, for being MP1 and MP2 Grid voltage is provided, and, grid voltage biasing is provided for MP2.
2. a kind of method of the ESD protection of the circuit of ESD protection as described in claim 1 characterized by comprising
When capacitor C0 receives esd pulse, charging current is generated, pressure drop is generated on resistance R0, controls the second PMOS transistor MP1 and third PMOS transistor MP2 is opened;
It is high level when passing through the output voltage Vb1 that the second PMOS transistor MP1 and the first NMOS transistor MN0 is exported, and, lead to When the bias voltage Vb2 for crossing third PMOS transistor MP2 and the first PMOS transistor MP0 output is high level, third is opened NMOS transistor MN2 and the second NMOS transistor MN1, leakage current.
3. the method according to claim 1, wherein the method also includes:
When the esd pulse on capacitor C0 disappears, the pressure drop on resistance R0 reduces, and controls MP1 and MP2 shutdown;
It is low level when passing through the output voltage Vb1 that MP1 and MN0 is exported, and, pass through the bias voltage Vb2 that MP2 and MP0 is exported When for low level, MN1 and MN2 is turned off.
4. the method according to claim 1, wherein the method also includes:
When capacitor C0 is without charging and discharging currents, without pressure drop on resistance R0, MP1 shutdown is controlled.
5. the method according to claim 1, wherein the tie point of resistance R0 and capacitor C0 grid with MP1 respectively Pole is connected with the grid of MP2, the method also includes:
Grid voltage is provided for MP1 and MP2 by the tie point, and, grid voltage biasing is provided for MP2;Wherein, the grid voltage is used for Control MP1's is switched on and off.
6. the method according to claim 1, wherein the method also includes:
Bias voltage Vb0 is exported to the grid of the grid of MN0 and MP0 respectively by biasing circuit VBIAS.
7. the method according to claim 1, wherein
Bias voltage Vb2 is more than or equal to the difference of supply voltage VDD and voltage rating;Wherein, the voltage rating are as follows: MN1's The gate-drain reversed bias voltage upper limit.
CN201611046358.3A 2016-11-22 2016-11-22 The method and circuit of the ESD protection to high-tension circuit are realized based on low-voltage device CN106558582B (en)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1381885A (en) * 2001-04-13 2002-11-27 华邦电子股份有限公司 I/O port with high voltage tolerance and electrostatic discharge protection circuit
TW518736B (en) * 2001-09-06 2003-01-21 Faraday Tech Corp Gate-driven or gate-coupled electrostatic discharge protection circuit
CN101022274A (en) * 2007-03-12 2007-08-22 北京时代民芯科技有限公司 Circuit capable of eliminating NMOS single tube transmission to form static short circuit current
CN101030574A (en) * 2006-03-02 2007-09-05 财团法人工业技术研究院 High-voltage tolerant power-rail electrostatic discharge protection circuit for mixed-voltage i/o interface
CN101640411A (en) * 2009-09-07 2010-02-03 北京时代民芯科技有限公司 Dual-channel electrostatic discharge protecting circuit based on RC-triggering
CN102170118A (en) * 2011-04-28 2011-08-31 北京大学 Power supply clamping position ESD (electronic static discharge) protecting circuit
CN102593122A (en) * 2011-01-10 2012-07-18 英飞凌科技股份有限公司 Semiconductor ESD circuit and method
CN103219718A (en) * 2012-01-18 2013-07-24 三星电子株式会社 Electrostatic discharge protection circuit
CN103400827A (en) * 2013-07-04 2013-11-20 西安电子科技大学 Static discharge clamping circuit with bias circuit in 90 nanometer CMOS (complementary metal-oxide-semiconductor transistor) process

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7385793B1 (en) * 2006-01-24 2008-06-10 Cypress Semiconductor Corporation Cascode active shunt gate oxide project during electrostatic discharge event

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1381885A (en) * 2001-04-13 2002-11-27 华邦电子股份有限公司 I/O port with high voltage tolerance and electrostatic discharge protection circuit
TW518736B (en) * 2001-09-06 2003-01-21 Faraday Tech Corp Gate-driven or gate-coupled electrostatic discharge protection circuit
CN101030574A (en) * 2006-03-02 2007-09-05 财团法人工业技术研究院 High-voltage tolerant power-rail electrostatic discharge protection circuit for mixed-voltage i/o interface
CN101022274A (en) * 2007-03-12 2007-08-22 北京时代民芯科技有限公司 Circuit capable of eliminating NMOS single tube transmission to form static short circuit current
CN101640411A (en) * 2009-09-07 2010-02-03 北京时代民芯科技有限公司 Dual-channel electrostatic discharge protecting circuit based on RC-triggering
CN102593122A (en) * 2011-01-10 2012-07-18 英飞凌科技股份有限公司 Semiconductor ESD circuit and method
CN102170118A (en) * 2011-04-28 2011-08-31 北京大学 Power supply clamping position ESD (electronic static discharge) protecting circuit
CN103219718A (en) * 2012-01-18 2013-07-24 三星电子株式会社 Electrostatic discharge protection circuit
CN103400827A (en) * 2013-07-04 2013-11-20 西安电子科技大学 Static discharge clamping circuit with bias circuit in 90 nanometer CMOS (complementary metal-oxide-semiconductor transistor) process

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