CN101834433B - Electrostatic discharge prevention circuit based on complementary SCR (Silicon Controlled Rectifier) - Google Patents
Electrostatic discharge prevention circuit based on complementary SCR (Silicon Controlled Rectifier) Download PDFInfo
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- CN101834433B CN101834433B CN2010101259778A CN201010125977A CN101834433B CN 101834433 B CN101834433 B CN 101834433B CN 2010101259778 A CN2010101259778 A CN 2010101259778A CN 201010125977 A CN201010125977 A CN 201010125977A CN 101834433 B CN101834433 B CN 101834433B
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Abstract
The invention discloses an electrostatic discharge prevention circuit based on a complementary SCR (Silicon Controlled Rectifier) for preventing the electrostatic discharge among an input/output end of a core circuit, a positive power line and a negative power line. The electrostatic discharge prevention circuit comprises a power supply clamping unit of which both ends are respectively connected with a positive power line and a negative power line, a PNPNP type bidirection SCR of which both connection terminals are respectively connected with the positive power line and an input/output end of the core circuit, and an NPNPN type bidirection SCR of which both connection terminals are respectively connected with the negative power line and an input/output end of the core circuit. The prevention scheme of the complementary SCR utilizes the power supply clamping unit as an auxiliary trigger unit, can realize the electrostatic discharge prevention of low trigger voltage, and has reliable electrostatic discharge prevention on the internal core circuit.
Description
Technical field
The present invention relates to technical field of integrated circuits, relate in particular to a kind of ESD protection circuit based on complementary SCR.
Background technology
Natural Electrostatic Discharge phenomenon is to cause one of topmost integrity problem that IC products lost efficacy.Relevant research shows that 30% of ic failure product all is owing to suffer the static discharge phenomenon caused.Therefore, the reliability of improving electrostatic discharge protective on the integrated circuit chip is to the rate of finished products that improves IC products and even drive whole national economy and have very important effect.
The static discharge phenomenon is divided into three kinds of discharge mode: HBM (human body discharge mode) usually according to the difference of charge source, MM (machine discharge mode), CDM (assembly charging and discharging pattern).And the most common two kinds of static discharge patterns that also are the industrial quarters product must pass through are HBM and MM.When static discharge took place, electric charge flowed into and flows out from the another pin from a pin of chip usually, and the electric current that this moment, electrostatic charge produced is usually up to several amperes, and the voltage that produces at the electric charge input pin is up to several volts even tens volts.Can cause the damage of inside chip if bigger ESD electric current flows into inside chip, simultaneously, the high pressure that produces at input pin also can cause internal components generation grid oxygen punch-through, thereby causes the inefficacy of circuit function.Therefore, damaged by ESD, all will carry out effective ESD protection each pin of chip in order to prevent inside chip.And two main points are mainly considered in the design of ESD protective unit: the one, and the ESD electric current that the ESD protective unit can be released bigger; The 2nd, the ESD protective unit can be with the strangulation of input pin terminal voltage at electronegative potential.
In the research and development process of ESD protection, diode, GGNMOS (NMOS of grid ground connection), SCR devices such as (controllable silicons) are used as the ESD protective unit usually.Along with the development of CMOS technology, the CMOS integrated circuit has become the main flow of integrated circuit development.For the CMOS integrated circuit, the input of chip output have usually the input buffering level output buffer stage or the grid of MOS device as input.Therefore; When esd event takes place; The stress (voltage) that ESD produces can directly act on the gate oxide of MOS device; If the ESD protective unit can not in time be opened and with the input strangulation electronegative potential (being often referred to the gate oxide breakdown voltage that is lower than the MOS device), then can cause input the gate oxide generation punch-through of output MOS device, thereby cause the inefficacy of chip functions.
Because the SCR structure has the very low voltage of keeping, and there is positive feedback loop in inside, and therefore, the SCR structure has very strong ESD current drain ability, becomes the safeguard structure of main flow in ESD protection field.
United States Patent (USP) 5473169 discloses a kind of complementary SCR of the CMOS of being used for integrated circuit, and it adopts single trap CMOS technology, utilizes N type silicon to be substrate.The shortcoming of this complementary SCR protectiving scheme mainly is the parasitic diode that there is forward in the relative power vd D of input IN; There is parasitic forward diode in power supply VSS to input; Cause input IN bigger, reduced the performance of some high speed circuits to the total parasitic capacitance of power vd D and VSS.
Summary of the invention
The invention provides a kind of ESD protection circuit, solved the problem that traditional complementary SCR parasitic capacitance is big, reduce the high speed circuit performance based on complementary SCR.
A kind of ESD protection circuit based on complementary SCR is used to protect the static discharge between core circuit I/O end (I/O), positive power line (VDD), negative power line (VSS) three, comprising:
Power supply clamp units, two ends connect positive power line and negative power line respectively, are used for the electrostatic discharge protective between positive power line and the negative power line;
Two-way SCR of interconnective PNPNP type and the two-way SCR of NPNPN type; Wherein two of the two-way SCR of PNPNP type splicing ears connect the I/O end of positive power line and core circuit respectively, are used for the electrostatic discharge protective between the I/O end of positive power line and core circuit; Two splicing ears of the two-way SCR of NPNPN type connect the I/O end of negative power line and core circuit respectively, are used for the electrostatic discharge protective between the I/O end of negative power line and core circuit.
Preferably; The two-way SCR of described PNPNP type comprises a P type substrate; Be provided with first n type buried layer in the one P type substrate, be marked with a P trap on first n type buried layer, be marked with a N trap of the annular identical between a P trap side and the P type substrate with a P trap junction depth; Be marked with a N type drift region and the 2nd N type drift region in the one P trap; Be provided with a P+ injection region and a N+ injection region in the one N type drift region, be provided with the 2nd P+ injection region and the 2nd N+ injection region in the 2nd N type drift region, wherein a P+ injection region and the 2nd P+ injection region are positioned at the inboard; P trap between the one N type drift region and the 2nd N type drift region is provided with the 5th P+ injection region, all is covered with the oxidation separator on a P type substrate, a N trap and the P trap;
The two-way SCR of described NPNPN type comprises the 2nd P type substrate; Be provided with second n type buried layer in the 2nd P type substrate; Be marked with the 2nd P trap and the 3rd P trap on second n type buried layer; The 2nd P trap is located at the interior two N trap identical with their junction depths of P type substrate with the 3rd P trap and is surrounded, and is provided with the 3rd N+ injection region and the 3rd P+ injection region in the 2nd P trap.Be provided with the 4th N+ injection region and the 4th P+ injection region in the 3rd P trap; Wherein the 3rd N+ injection region and the 4th N+ injection region are positioned at the inboard; Be provided with the 5th N+ injection region in the 2nd N trap between the 3rd P trap and the 3rd P trap, be covered with the oxidation separator on the 2nd P type substrate, the 2nd P trap, the 3rd P trap and the 2nd N trap;
The 5th N+ injection region and the 5th P+ injection region interconnect; The one N+ injection region is connected VDD with a P+ injection region; The 4th N+ injection region is connected VSS with the 4th P+ injection region, and the 2nd N+ injection region, the 3rd N+ injection region, the 2nd P+ injection region and the 3rd P+ injection region connect I/O.
N type drift region generally is the drain terminal drift region that in high tension apparatus LDNMOS (laterally double diffusion NMOS), is used to realize LDNMOS; The doping content of N type drift region generally greater than the doping content of N trap less than the doping content of N+ injection region, N type drift region junction depth (vertically the degree of depth) is darker and more shallow than the junction depth of N trap and P trap than the junction depth of N+ injection region and P+ injection region.
Described power supply clamp units comprises:
A RC testing circuit that is composed in series by electric capacity and resistance;
An inverter of forming by NMOS pipe and PMOS pipe;
The 2nd NMOS pipe of the ESD that is used to release;
The substrate of the resistance terminal of RC testing circuit, PMOS pipe is connected VDD with the drain electrode of source electrode and the 2nd NMOS pipe; The substrate of the capacitance terminal of RC testing circuit, NMOS pipe is connected VSS with the substrate of source electrode and the 2nd NMOS pipe with source electrode, and the grid of the 2nd NMOS pipe connects the drain electrode of PMOS pipe and NMOS pipe.
Preferably, the RC time constant of described RC testing circuit is 0.1～0.2us.
Preferably, described protection phone comprises that also two ends connect the I/O end of core circuit and the current-limiting resistance of core circuit respectively.
Utilize ESD protection circuit of the present invention can realize the electrostatic discharge protective of I/O end to various situation between positive power line and negative power line.This complementary SCR protectiving scheme utilizes the power supply clamp units as the auxiliary triggering unit, can realize the electrostatic discharge protective of low trigger voltage, and inner core circuit is played reliable electrostatic discharge protective.
Description of drawings
Fig. 1 is the equivalent circuit diagram of complementary SCR under the existing CMOS technology;
Fig. 2 is the longitudinal sectional drawing of complementary SCR under the existing CMOS technology;
The structural representation of circuit of the present invention when Fig. 3 adopts 5 layers of semiconductor to represent for SCR;
Fig. 4 is the two-way SCR parasitic element of a present invention equivalent circuit diagram;
Fig. 5 occurs in I/O for ESD, during VSS ground connection, and the path profile of releasing of ESD trigger current;
Fig. 6 occurs in VSS for ESD, during I/O ground connection, and the path profile of releasing of ESD trigger current;
Fig. 7 occurs in VDD for ESD, during I/O ground connection, and the path profile of releasing of ESD trigger current;
Fig. 8 occurs in I/O for ESD, during VDD ground connection, and the path profile of releasing of ESD trigger current;
Fig. 9 is the longitudinal sectional drawing of the two-way SCR of PNPNP type of the present invention;
Figure 10 is that two-way SCR shown in Figure 9 realizes domain;
Figure 11 is the longitudinal sectional drawing of the two-way SCR of NPNPN type of the present invention;
Figure 12 is that two-way SCR shown in Figure 11 realizes domain;
Figure 13 is the structural representation of power supply clamp units of the present invention.
Embodiment
Like Fig. 3 and shown in Figure 4, a kind of ESD protection circuit based on complementary SCR comprises:
A current-limiting resistance Rp who connects I/O;
The two-way SCR of one PNPNP type; Like Fig. 9 and shown in Figure 10; Comprise in P type substrate 101, the P type substrate 101 and be provided with n type buried layer 102; Be marked with P trap 103 on the n type buried layer 102, be marked with the N trap 104 of the annular identical with P trap 103 junction depths between P trap 103 sides and the P type substrate 101, N trap 104 is isolated P trap 102 and P type substrate 101 with n type buried layer 102.
Be marked with N type drift region 105a and N type drift region 105b in the P trap 103; Be provided with P+ injection region 107 and N+ injection region 106 in the N type drift region 105a; Be provided with P+ injection region 108 and N+ injection region 109 in the N type drift region 105b; Wherein P+ injection region 107 is positioned at the inboard with P+ injection region 108, and the P trap 103 between N type drift region 105a and the N type drift region 105b is provided with P+ injection region 110, all is covered with oxidation separator 111 on P type substrate 101, N trap 104 and the P trap 103.
The two-way SCR of one NPNPN type; Like Figure 11 and shown in Figure 12; Comprise in P type substrate 201, the P type substrate 201 being provided with n type buried layer 202, be marked with P trap 203 and P trap 205 on the n type buried layer 202, P trap 203 is located at 204 encirclements of N trap in the P type substrate 201 with P trap 205; The junction depth of N trap 204 is identical with the junction depth of P trap 203 and P trap 205, and it and n type buried layer 202 are isolated P type substrate and P trap.
Be provided with P+ injection region 206 and N+ injection region 207 in the P trap 203; Be provided with P+ injection region 209 and N+ injection region 208 in the P trap 205; Wherein N+ injection region 207 is positioned at the inboard with N+ injection region 208; N trap 204 between P trap 203 and the P trap 205 is provided with N+ injection region 210, all is covered with oxidation separator 211 on P type substrate 201, N trap 204, P trap 203, the P trap 205.
One power supply clamp units, shown in figure 13, comprise the RC testing circuit that constitutes by the series connection of resistance R and capacitor C (the release NMOS pipe 303 of ESD of the reverser that the RC time constant generally is set in 0.1～0.2us), PMOS pipe 301 and NMOS pipe 302 constitute and being used to.
When above-mentioned protection circuit is applied in the physical circuit, need the core circuit two ends of protection to connect VDD and VSS respectively, current-limiting resistance Rg two ends connect the I/O and the core circuit of core circuit respectively,
The grid of PMOS pipe 301 is connected the tie point of resistance R and capacitor C with the grid of NMOS pipe 302; The drain electrode of the substrate of the resistance terminal of RC testing circuit, PMOS pipe 301, source electrode and NMOS pipe 303 connects VDD; Substrate, source electrode and the NMOS of the capacitance terminal of RC testing circuit, NMOS pipe 302 manages 303 substrates, source electrode connects VSS, and the grid of NMOS pipe 303 connects the drain electrode of PMOS pipe 301 and NMOS pipe 302.During the core circuit operate as normal, the two-way SCR of NPNPN type, the two-way SCR of PNPNP type, power supply clamp units all are in cut-off state
As shown in Figure 5; When esd event occurs in I/O end (I/O); And during VSS ground connection, the ESD trigger current can at first be released through forward diode 51, power supply clamp units parasitic between forward diode 50, P trap 103 and the N type drift region 105a of P trap 203 and 204 parasitisms of N trap, when the ESD electric current reaches certain numerical value; Forward diode 50 conductings; Cause SCR3 unlatching in NPNPN type two-way SCR and be in latch mode owing to have internal positive feedback between triode 44 and the triode 45 this moment, and the ESD electric current can be released through SCR3.
As shown in Figure 6; When esd event occurs in power end VSS; And during I/O end (I/O) ground connection, the ESD trigger current at first can be released through forward diode 61 parasitic between forward diode 60, P trap 103 and the N type drift region 105b of P trap 205 and 204 parasitisms of N trap, when the ESD trigger current reaches certain numerical value; Diode 60 forward conductions; Cause SCR4 unlatching in NPNPN type two-way SCR and be in latch mode because there is internal positive feedback in triode 43 with triode 44 this moment, and the ESD electric current can be released through SCR4.
As shown in Figure 7; When esd event occurs in power end VDD; And during I/O end (I/O) ground connection, the ESD trigger current at first can be released through forward diode 61 parasitic between forward diode 60, P trap 103 and the N type drift region 105b of power supply clamp units, P trap 205 and 204 parasitisms of N trap, when the ESD trigger current reaches certain numerical value; Diode 61 forward conductions; Cause SCR1 unlatching in PNPNP type two-way SCR and be in latch mode because there is internal positive feedback in triode 40 with triode 41 this moment, and the ESD electric current can be released through SCR1.
As shown in Figure 8; When esd event occurs in I/O end (I/O); And during power end VDD ground connection, the ESD trigger current at first can be released through forward diode 51 parasitic between forward diode 50, P trap 103 and the N type drift region 104a of P trap 203 and 204 parasitisms of N trap; When the ESD trigger current reaches certain numerical value, diode 61 forward conductions, cause SCR2 unlatching in PNPNP type two-way SCR and be in latch mode because there is internal positive feedback in triode 42 with triode 41 this moment, and the ESD electric current can be released through SCR2.
Claims (5)
1. the ESD protection circuit based on complementary SCR is used to protect the static discharge between core circuit I/O end, positive power line, the negative power line three, it is characterized in that, comprising:
Power supply clamp units, two ends connect positive power line and negative power line respectively, are used for the electrostatic discharge protective between positive power line and the negative power line;
Two-way SCR of interconnective PNPNP type and the two-way SCR of NPNPN type; Wherein two of the two-way SCR of PNPNP type splicing ears connect the I/O end of positive power line and core circuit respectively, are used for the electrostatic discharge protective between the I/O end of positive power line and core circuit; Two splicing ears of the two-way SCR of NPNPN type connect the I/O end of negative power line and core circuit respectively, are used for the electrostatic discharge protective between the I/O end of negative power line and core circuit;
The two-way SCR of described PNPNP type comprises a P type substrate (101); Be provided with first n type buried layer (102) in the one P type substrate (101); Be marked with a P trap (103) on first n type buried layer (102); Be marked with a N trap (104) of the annular identical between the one P trap (a 103) side and the P type substrate (101) with P trap (a 103) junction depth; Be marked with a N type drift region (105a) and the 2nd N type drift region (105b) in the one P trap (103); Be provided with a P+ injection region (107) and a N+ injection region (106) in the one N type drift region (105a); Be provided with the 2nd P+ injection region (108) and the 2nd N+ injection region (109) in the 2nd N type drift region (105b); Wherein a P+ injection region (107) and the 2nd P+ injection region (108) are positioned between a N+ injection region (106) and the 2nd N+ injection region (109), and the P trap (103) between a N type drift region and the 2nd N type drift region is provided with the 5th P+ injection region (110), all are covered with the oxidation separator on a P type substrate (103), a N trap (104) and the P trap (101);
The two-way SCR of described NPNPN type comprises the 2nd P type substrate (201); Be provided with second n type buried layer (202) in the 2nd P type substrate (201); Be marked with the 2nd P trap (203) and the 3rd P trap (205) on second n type buried layer (202); The 2nd P trap (203) is located at the interior two N trap (204) identical with their junction depths of the 2nd P type substrate (201) with the 3rd P trap (205) and is surrounded, and is provided with the 3rd N+ injection region (207) and the 3rd P+ injection region (206) in the 2nd P trap (203); Be provided with the 4th N+ injection region (208) and the 4th P+ injection region (209) in the 3rd P trap (205); Wherein the 3rd N+ injection region (207) and the 4th N+ injection region (208) are positioned between the 3rd P+ injection region (206) and the 4th P+ injection region (209); Be marked with the 5th N+ injection region (210) in the 2nd N trap (204) between the 2nd P trap (203) and the 3rd P trap (205), be covered with the oxidation separator on the 2nd P type substrate (201), the 2nd P trap (203), the 3rd P trap (205) and the 2nd N trap (204).
2. ESD protection circuit according to claim 1 is characterized in that:
Described the 5th N+ injection region (210) and the 5th P+ injection region (110) interconnect; The one a N+ injection region (106) and a P+ injection region (107) are connected to positive power line; The 4th N+ injection region (208) is connected negative power line with the 4th P+ injection region (209), and the 2nd N+ injection region (109), the 3rd N+ injection region (207), the 2nd P+ injection region (108) and the 3rd P+ injection region (206) connect the I/O end of core circuit.
3. ESD protection circuit according to claim 1 is characterized in that, described power supply clamp units comprises:
A RC testing circuit that is composed in series by electric capacity and resistance;
An inverter of forming by NMOS pipe (302) and PMOS pipe (301);
The 2nd NMOS pipe (303) of the ESD that is used to release;
The substrate of the resistance terminal of RC testing circuit, PMOS pipe (301) is connected positive power line with the drain electrode of source electrode and the 2nd NMOS (302) pipe; The substrate of the capacitance terminal of RC testing circuit, NMOS pipe (302) is connected negative power line with the substrate of source electrode and the 2nd NMOS pipe (303) with source electrode, and the grid of the 2nd NMOS pipe (303) connects the drain electrode of PMOS pipe (301) and NMOS pipe (302).
4. ESD protection circuit according to claim 3 is characterized in that: the RC time constant of described RC testing circuit is 0.1～0.2us.
5. ESD protection circuit according to claim 1 is characterized in that: comprise that two ends connect the I/O end of core circuit and the current-limiting resistance (Rp) of core circuit respectively.
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| CN2010101259778A CN101834433B (en) | 2010-03-17 | 2010-03-17 | Electrostatic discharge prevention circuit based on complementary SCR (Silicon Controlled Rectifier) |
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| CN2010101259778A CN101834433B (en) | 2010-03-17 | 2010-03-17 | Electrostatic discharge prevention circuit based on complementary SCR (Silicon Controlled Rectifier) |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102013112283B4 (en) | 2012-11-20 | 2023-08-31 | Analog Devices, Inc. | Junction isolated reverse voltage devices with integrated protection structures and methods of forming them |
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| CN102956632B (en) * | 2011-08-31 | 2016-09-14 | 北京中电华大电子设计有限责任公司 | A kind of two-way SCR ESD-protection structure of low parasitic capacitance |
| CN104733445B (en) * | 2015-03-17 | 2017-12-29 | 北京中科新微特科技开发股份有限公司 | Esd protection structure includes the gated power device and manufacture method of the structure |
| CN106099883A (en) * | 2015-06-29 | 2016-11-09 | 苏州森特克测控技术有限公司 | A kind of chip ESD protection circuit |
| US10147717B2 (en) * | 2015-09-03 | 2018-12-04 | Novatek Microelectronics Corp. | Electrostatic discharge protection circuit |
| CN106653745B (en) * | 2016-11-30 | 2019-01-08 | 辽宁大学 | A kind of two-way longitudinal direction NPN structure for ESD protection |
| CN106876388B (en) * | 2017-03-09 | 2019-07-30 | 东南大学 | A kind of ghyristor circuit for prevention at radio-frequency port electrostatic discharge protective |
| CN108258673B (en) * | 2018-02-11 | 2019-09-03 | 上海天马微电子有限公司 | Electrostatic protection circuit, display panel and display device |
| CN108520875B (en) * | 2018-06-07 | 2023-08-22 | 湖南静芯微电子技术有限公司 | High-maintenance voltage NPNPN type bidirectional silicon controlled rectifier electrostatic protection device |
| CN109103182B (en) * | 2018-08-24 | 2022-03-29 | 电子科技大学 | Bidirectional ESD protection device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102013112283B4 (en) | 2012-11-20 | 2023-08-31 | Analog Devices, Inc. | Junction isolated reverse voltage devices with integrated protection structures and methods of forming them |
| DE102013112283B8 (en) | 2012-11-20 | 2023-12-14 | Analog Devices, Inc. | Junction isolated reverse voltage devices with integrated protection structures and method of forming same |
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