CN109103182B - Bidirectional ESD protection device - Google Patents
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- CN109103182B CN109103182B CN201810972070.1A CN201810972070A CN109103182B CN 109103182 B CN109103182 B CN 109103182B CN 201810972070 A CN201810972070 A CN 201810972070A CN 109103182 B CN109103182 B CN 109103182B
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- 230000002457 bidirectional effect Effects 0.000 title abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 23
- 238000000407 epitaxy Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000013461 design Methods 0.000 description 10
- 238000004088 simulation Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000012423 maintenance Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000005374 Kerr effect Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
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- 230000036039 immunity Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
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- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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Abstract
The invention provides a bidirectional ESD protection device, comprising: the device comprises a P-type substrate, an N-type epitaxy layer, an NTOP layer, a first PWELL area, a first N + contact area, a first P + contact area, a first NTOP layer, a second PWELL area, a second N + contact area, a second P + contact area and a second NTOP layer, wherein the first N + contact area and the first P + contact area form a metal anode through metal short circuit, and the second N + contact area and the second P + contact area form a metal cathode through metal short circuit; according to the invention, the NTOP layer is introduced above the N-type epitaxial layer to change the current distribution, so that the IV curve of the device presents the characteristic of multiple snapback, and the robustness of the device under the ESD pulse current is improved; to avoid device latch-up, the sustain current can be adjusted by adjusting the spacing between the NTOP layer and the first and second PWELL regions.
Description
Technical Field
The invention belongs to the field of electronic science and technology, mainly relates to an ElectroStatic Discharge (ESD) protection technology on an integrated circuit chip, and particularly relates to an ESD protection device which has low power consumption and strong latch-up resistance and is used for a high-voltage integrated circuit.
Background
ESD, i.e., electrostatic discharge, is a phenomenon that is ubiquitous in nature. ESD exists in every corner of people's daily life. Such conventional electrical phenomena are a fatal threat to sophisticated integrated circuits. However, for a chip that has completed packaging, each power/input/output pin becomes a path for entering of a pulse current such as a Human Body Model (HBM), a Machine Model (MM), a human body metal model (HMM), and the like. The strong ESD pulse not only causes hard failure of the chip, but also induces various effects (such as latch-up, soft failure, etc.) due to improper design of the ESD protection device. In addition, very few ESD failures can be detected directly during the chip manufacturing process. Most of the ESD damage does not have obvious influence on the performance of the chip, so that the ESD damage passes the standard test and finally enters the hands of customers. Such chips "work with trouble" in various applications, continuously threatening the reliability of the system in which they are located.
For high voltage integrated circuits, LDMOS structures (as shown in fig. 1) cannot generally be used directly for ESD protection due to latch-up like effects. For example, the sustaining voltage of the LDMOS is raised above the VDD voltage in some way to meet the conventional design window of the ESD protection device. Although the latch-up phenomenon can be eliminated by the high-maintenance voltage design, the voltage borne by the device in the on state can be improved so as to improve the power, and the robustness of the LDMOS is greatly reduced due to the influence of the Kerr effect under large current.
In order to enable the LDMOS to have high robustness, the multi-finger layout design can improve the ESD robustness linearly theoretically, but the influence of process errors and the like is added due to the strong snapback. Each finger may not be turned on at the same time. More related technologies (such as ESD gate coupling technologies proposed in IEDM) are therefore well suited to solve this problem. However, in a high voltage application chip with strong ESD requirements, the area of the ESD device may be large, thereby increasing the manufacturing cost. Therefore, the layout area of the ESD device, the avoidance of latch-up and the strong ESD robustness form a contradiction which is difficult to compromise. Namely: latch-up less robust operation is required and increased area is required to improve ESD robustness of latch-up less devices.
To solve this problem, research results show that increasing the holding current can solve the latch-up-like problem of the device to some extent. If the maximum current provided by the power supply cannot guarantee the minimum holding current requirement of the ESD device, latch-up will not occur. This provides a new idea for the design of low holding voltage latch-up free ESD protection device. The ESD protection device breaks through a conventional high-maintenance voltage design window, and provides a design of the device with the high-maintenance current design window. Therefore, the maintaining voltage of the device is lower than that of the traditional ESD protective device with high maintaining voltage, the power consumption when ESD pulse is discharged is reduced, and the ESD robustness of the device is improved. Specifically, on the basis of the traditional SCR, the NTOP layer is introduced above the PWELL area and the N epitaxial layer, so that the characteristics of adjustable trigger voltage and holding current, low discharge power, high robustness and the like are realized.
Disclosure of Invention
The invention aims to solve the problems that: under the condition of a certain process, the characteristics of accurate and quick triggering (proper triggering voltage), high maintaining current, low ESD power consumption, high robustness and the like of the ESD device are realized.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a bi-directional ESD protection device comprising: a P-type substrate 00, an N-type epitaxy 01 located above the P-type substrate, and an NTOP layer 13 located above the N-type epitaxy; a first PWELL region 201 on the left side above the N-type epitaxy, a first N + contact region 111 above the inside of the first PWELL region, a first P + contact region 211 above the inside of the first PWELL region, a first NTOP layer 121 above the inside of the first PWELL region; wherein the first P + contact region 211 is located at the left side of the first N + contact region 111, and the first NTOP layer 121 is located at the right side of the first N + contact region 111; a second PWELL region 202 located right above the N-type epitaxy, a second N + contact region 112 located above an inner portion of the second PWELL region, a second P + contact region 212 located above an inner portion of the second PWELL region, a second NTOP layer 122 located above an inner portion of the second PWELL region; wherein the second P + contact region 212 is located at the right side of the second N + contact region 112, and the second NTOP layer 122 is located at the left side of the second N + contact region 112; wherein the NTOP layer 13 is located on the upper surface of the N-type epitaxy 01 and is separated from the first PWELL area 201 and the second PWELL area 202; the first N + contact region 111 and the first P + contact region 211 form a metal anode 31 by metal shorting, and the second N + contact region 112 and the second P + contact region 212 form a metal cathode 32 by metal shorting.
Preferably, the NWELL area 10 is disposed between the first PWELL area 201 and the second PWELL area 202, and the NTOP layer 13 is disposed over the NWELL area 10.
Preferably, a first N + low trigger area 141 is disposed between the first PWELL area 201 and the NWELL area 10, and a part of the first N + low trigger area 141 is located in the first PWELL area 201 and a part is located in the NWELL area 10; a second N + low trigger area 142 is provided between the second PWELL area 202 and the NWELL area 10, and the second N + low trigger area 142 is partially within the second PWELL area 202 and partially within the NWELL area 10.
Preferably, the first NTOP layer 121 and the second NTOP layer 122 are both a continuous region or a plurality of discontinuous spaced sub-regions.
Preferably, a gate oxide layer 03 is disposed above the first N + contact region 111 and the leftmost subregion of the first NTOP layer 121, above the adjacent subregions of the first NTOP layer 121, above the rightmost subregion of the first NTOP layer 121 and the first N + low trigger region 141, above the first N + low trigger region 141 and the NTOP layer 13, above the NTOP layer 13 and the second N + low trigger region 142, above the second N + low trigger region 142 and the leftmost subregion of the second NTOP layer 122, above the adjacent subregions of the second NTOP layer 122, above the rightmost subregion of the second NTOP layer 122 and the second N + contact region 112, and a gate electrode 04 is disposed above the gate oxide layer 03.
Preferably, the gate electrode 04 is a polysilicon electrode or a metal electrode.
Preferably, each doping type in the device is correspondingly changed into opposite doping, namely, the P-type doping is changed into the N-type doping, and meanwhile, the N-type doping is changed into the P-type doping.
The invention has the beneficial effects that: 1. the high-maintenance-current ESD protection device provided by the invention can adjust the maintenance current by adjusting the distance between the NTOP layer and the first PWELL area and the second PWELL area, thereby avoiding the latch-up effect; and 2, the introduction of the NTOP layer changes the current distribution, so that the IV curve of the device presents the characteristics of multiple snapback, and the robustness of the device under the ESD pulse current is improved.
Drawings
FIG. 1(a) is a conventional high-holding-voltage ESD design window;
FIG. 1(b) is a high holding current ESD design window;
FIG. 2 is a block diagram of a conventional bi-directional SCR device;
FIG. 3 is a structural view of embodiment 1;
FIG. 4 is a structural view of embodiment 2;
FIG. 5 is a structural view of embodiment 3;
FIG. 6 is a structural view of embodiment 4;
FIG. 7 is a structural view of embodiment 5;
FIG. 8 is a graph comparing I-V characteristics of example 2 and a conventional bidirectional SCR device;
FIG. 9 is a HBM hybrid emulation circuit diagram;
FIG. 10 shows the time domain simulation results of example 2;
00 is a P-type substrate, 01 is an N-type epitaxy, 10 is an NWELL region, 13 is an NTOP layer, 03 is a gate oxide layer, 04 is a gate electrode, 31 is a metal anode, 32 is a metal cathode, 201 is a first PWELL region, 111 is a first N + contact region, 211 is a first P + contact region, 121 is a first N + low trigger region, 121 is a first NTOP layer, 202 is a second PWELL region, 112 is a second N + contact region, 212 is a second P + contact region, 122 is a second N + low trigger region, and 122 is a second NTOP layer.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
As shown in fig. 3, the device structure of the present embodiment includes: a P-type substrate 00, an N-type epitaxy 01 located above the P-type substrate, and an NTOP layer 13 located above the N-type epitaxy; a first PWELL region 201 on the left side above the N-type epitaxy, a first N + contact region 111 above the inside of the first PWELL region, a first P + contact region 211 above the inside of the first PWELL region, a first NTOP layer 121 above the inside of the first PWELL region; wherein the first P + contact region 211 is located at the left side of the first N + contact region 111, and the first NTOP layer 121 is located at the right side of the first N + contact region 111; a second PWELL region 202 located right above the N-type epitaxy, a second N + contact region 112 located above an inner portion of the second PWELL region, a second P + contact region 212 located above an inner portion of the second PWELL region, a second NTOP layer 122 located above an inner portion of the second PWELL region; wherein the second P + contact region 212 is located at the right side of the second N + contact region 112, and the second NTOP layer 122 is located at the left side of the second N + contact region 112; wherein the NTOP layer 13 is located on the upper surface of the N-type epitaxy 01 and is separated from the first PWELL area 201 and the second PWELL area 202; the first N + contact region 111 and the first P + contact region 211 form a metal anode 31 by metal shorting, and the second N + contact region 112 and the second P + contact region 212 form a metal cathode 32 by metal shorting.
Example 2
As shown in fig. 4, the NWELL area 10 is disposed between the first PWELL area 201 and the second PWELL area 202, and the NTOP layer 13 is disposed on the NWELL area 10.
The working principle of the embodiment is as follows:
when the anode ESD voltage rises, the device first breaks down at the PN junction formed by the second PWELL region 202/NWELL region 10 at the surface. The broken hole current flows through the second PWELL region 202 and the second P + contact region 212, and is pumped away by the metal cathode 32. When the current flowing through the second P + contact region 212 increases to a certain value, so that the voltage drop between the second PWELL202 and the second N + contact region 112 reaches 0.7V, the parasitic NPN transistor is turned on. The second N + contact region 112 injects electrons into the second PWELL region and most of the electrons pass through the second NTOP layer 122 and are collected by the NWELL region 10. The NTOP layer 13 provides a low resistance path for the electron current, and most of the electron current flows through the NWELL region 10, the NTOP layer 13, the first PWELL region 201, the first NTOP layer 121, and the first N + contact region 111, and is pumped away by the metal anode 31. Due to the presence of the NTOP layer 13, the electron current flows away from the low resistance region and current concentration will occur to the right of the NTOP layer 13. Accordingly, a peak of the electric field occurs at the right side of NTOP layer 13 due to kirk effect, and the electric field causes the sustaining voltage V of the device at small currenthHigher. As the current increases, impact ionization will generate more electron-hole pairs, the NWELL 10 decreases in resistance due to conductance modulation effects, and when the current rises to a certain value, the NWELL 10 pairsThe electron current is shunted, the electron current flowing through the NTOP layer 13 is reduced, the electric field peak value on the right side of the NTOP layer 13 is reduced, and the sustain voltage V of the device is reducedhAnd decreases.
In order to prove that the device can work under the condition that the VDD is higher than the maintaining voltage of the VDD and the latch-up phenomenon does not occur, the circuit hybrid simulation verification is carried out.
Fig. 8 is an I-V characteristic simulation of example 2, and conv. As can be seen from the simulation results, the trigger voltage of the embodiment 2 is the same as that of the conventional bidirectional SCR device, and the conventional bidirectional SCR device cannot realize high holding current; the IV curve of example 2 is in agreement with the above analysis of the working principle.
Fig. 9 is a circuit diagram of a Human Body Model (HBM) simulation. The HBM circuit part in the dashed frame on the left side of the circuit is used for simulating an ESD pulse waveform when a human body discharges static electricity; the right loop is the power supply loop of the device, where HV source is the supply voltage, RLFor load resistance, the DUT is the test module and isolates the HBM circuit from the HV source loop through a diode to ensure that ESD pulses generated by the HBM circuit do not affect the HV source.
FIG. 10 is a graph showing the results of the simulation of the latch-up immune hybrid of example 2, which is obtained by the simulation of the HBM circuit shown in FIG. 9. As can be seen from the figure, after the analog waveform of the HBM is input, the conventional bidirectional SCR device latches, so that the device cannot be normally turned off after the HBM waveform is passed, and the power supply voltage VDD is clamped below 15V. The bi-directional ESD protection device proposed in this patent is clamped to a potential lower than the power supply voltage VDD for ESD discharge, but due to the holding current I of the devicehVery high, when the ESD pulse is removed, the current of the whole loop cannot be maintained at I only by the power supply voltagehThus, the aim of latch-up immunity is achieved.
Example 3
As shown in fig. 5, the main differences between this embodiment and embodiment 2 are: a first N + low trigger area 141 is disposed between the first PWELL area 201 and the NWELL area 10, and a part of the first N + low trigger area 141 is located in the first PWELL area 201 and a part is located in the NWELL area 10; a second N + low trigger area 142 is provided between the second PWELL area 202 and the NWELL area 10, and the second N + low trigger area 142 is partially within the second PWELL area 202 and partially within the NWELL area 10.
Example 4
As shown in fig. 6, the present embodiment is different from embodiment 3 in that: the first NTOP layer 121 and the second NTOP layer 122 are both discontinuous sub-regions.
Example 5
As shown in fig. 7, the present embodiment is different from embodiment 4 in that: a gate oxide layer 03 is arranged above the first N + contact region 111 and the leftmost subregion of the first NTOP layer 121, above the adjacent subregions of the first NTOP layer 121, above the rightmost subregion of the first NTOP layer 121 and the first N + low trigger region 141, above the first N + low trigger region 141 and the NTOP layer 13, above the NTOP layer 13 and the second N + low trigger region 142, above the leftmost subregion of the second N + low trigger region 142 and the second NTOP layer 122, above the adjacent subregions of the second NTOP layer 122, above the rightmost subregion of the second NTOP layer 122 and the second N + contact region 112, and a gate electrode 04 is arranged above the gate oxide layer 03. This has the advantage that a self-aligned process can be used to achieve the corresponding N-type impurity implantation.
Claims (7)
1. A bi-directional ESD protection device, comprising: a P-type substrate (00), an N-type epitaxy (01) positioned above the P-type substrate, and an NTOP layer (13) positioned above the N-type epitaxy; a first PWELL region (201) on the left side above the N-type epitaxy, a first N + contact region (111) above an inner portion of the first PWELL region, a first P + contact region (211) above an inner portion of the first PWELL region, a first NTOP layer (121) above an inner portion of the first PWELL region; wherein the first P + contact region (211) is located at the left side of the first N + contact region (111), and the first NTOP layer (121) is located at the right side of the first N + contact region (111); a second PWELL region (202) on the right side over the N-type epitaxy, a second N + contact region (112) over an interior of the second PWELL region, a second P + contact region (212) over an interior of the second PWELL region, a second NTOP layer (122) over an interior of the second PWELL region; wherein the second P + contact region (212) is located to the right of the second N + contact region (112), and the second NTOP layer (122) is located to the left of the second N + contact region (112); wherein the NTOP layer (13) is positioned on the upper surface of the N-type epitaxy (01) and is separated from the first PWELL area (201) and the second PWELL area (202); the first N + contact area (111) and the first P + contact area (211) form a metal anode (31) through metal short-circuiting, and the second N + contact area (112) and the second P + contact area (212) form a metal cathode (32) through metal short-circuiting.
2. A bi-directional ESD protection device as claimed in claim 1, wherein: an NWELL area (10) is arranged between the first PWELL area (201) and the second PWELL area (202), and the NTOP layer (13) is positioned above the inner part of the NWELL area (10).
3. A bi-directional ESD protection device as claimed in claim 2, wherein: a first N + low trigger area (141) is arranged between the first PWELL area (201) and the NWELL area (10), and a part of the first N + low trigger area (141) is positioned in the first PWELL area (201) and a part of the first N + low trigger area is positioned in the NWELL area (10); a second N + low trigger area (142) is disposed between the second PWELL area (202) and the NWELL area (10), and the second N + low trigger area (142) is partially within the second PWELL area (202) and partially within the NWELL area (10).
4. A bi-directional ESD protection device as claimed in claim 3, wherein: the first NTOP layer (121) and the second NTOP layer (122) are both a continuous region or a plurality of discontinuous spaced-apart sub-regions.
5. A bi-directional ESD protection device, according to claim 4, wherein: the gate oxide layer (03) is arranged above the first N + contact region (111) and the leftmost subregion of the first NTOP layer (121), above the adjacent subregions of the first NTOP layer (121), above the rightmost subregion of the first NTOP layer (121) and the first N + low trigger region (141), above the first N + low trigger region (141) and the NTOP layer (13), above the NTOP layer (13) and the second N + low trigger region (142), above the second N + low trigger region (142) and the leftmost subregion of the second NTOP layer (122), above the adjacent subregions of the second NTOP layer (122), above the rightmost subregion of the second NTOP layer (122) and the second N + contact region (112), and the gate electrode (04) is arranged above the gate oxide layer (03).
6. A bi-directional ESD protection device according to claim 5, wherein: the gate electrode (04) is a polysilicon electrode or a metal electrode.
7. A bi-directional ESD protection device according to any of claims 1-6, characterized in that: the doping types in the device are correspondingly changed into opposite doping, namely P-type doping is changed into N-type doping, and simultaneously N-type doping is changed into P-type doping.
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| CN111092076A (en) * | 2019-12-27 | 2020-05-01 | 电子科技大学 | High-maintenance-voltage transverse SCR device |
| US12002890B2 (en) | 2021-05-21 | 2024-06-04 | Samsung Electronics Co., Ltd. | Semiconductor protection device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241274A (en) * | 2014-08-30 | 2014-12-24 | 电子科技大学 | Both-way ESD protection device based on transverse PNP structure |
| CN205376532U (en) * | 2015-12-24 | 2016-07-06 | 大唐恩智浦半导体有限公司 | Electrostatic protection circuit and gthyristor thereof |
| CN107731814A (en) * | 2017-11-15 | 2018-02-23 | 淮阴师范学院 | A kind of bi-directional ESD safeguard structure of embedded low trigger voltage positive-negative-positive structure |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7427787B2 (en) * | 2005-07-08 | 2008-09-23 | Texas Instruments Incorporated | Guardringed SCR ESD protection |
| TW200905860A (en) * | 2007-07-31 | 2009-02-01 | Amazing Microelectroing Corp | Symmetric type bi-directional silicon control rectifier |
| CN101834433B (en) * | 2010-03-17 | 2012-05-30 | 浙江大学 | Electrostatic discharge prevention circuit based on complementary SCR (Silicon Controlled Rectifier) |
| US9754929B2 (en) * | 2014-06-20 | 2017-09-05 | Texas Instruments Incorporated | Positive strike SCR, negative strike SCR, and a bidirectional ESD structure that utilizes the positive strike SCR and the negative strike SCR |
| CN106158959B (en) * | 2015-04-15 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and electronic device |
| CN106920843B (en) * | 2015-12-24 | 2024-01-09 | 大唐恩智浦半导体有限公司 | Electrostatic protection circuit and silicon controlled rectifier thereof |
| CN106206569B (en) * | 2016-08-12 | 2019-05-10 | 电子科技大学 | A kind of two-way SCR device of low trigger voltage based on buried layer triggering |
| CN106783942A (en) * | 2016-11-30 | 2017-05-31 | 辽宁大学 | A kind of two-way SCR structure for ESD protections |
| CN106876388B (en) * | 2017-03-09 | 2019-07-30 | 东南大学 | A kind of ghyristor circuit for prevention at radio-frequency port electrostatic discharge protective |
-
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241274A (en) * | 2014-08-30 | 2014-12-24 | 电子科技大学 | Both-way ESD protection device based on transverse PNP structure |
| CN205376532U (en) * | 2015-12-24 | 2016-07-06 | 大唐恩智浦半导体有限公司 | Electrostatic protection circuit and gthyristor thereof |
| CN107731814A (en) * | 2017-11-15 | 2018-02-23 | 淮阴师范学院 | A kind of bi-directional ESD safeguard structure of embedded low trigger voltage positive-negative-positive structure |
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