CN102034857B - Bidirectional triode thyristor auxiliarily triggered by POMS field effect transistor - Google Patents
Bidirectional triode thyristor auxiliarily triggered by POMS field effect transistor Download PDFInfo
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- CN102034857B CN102034857B CN 201010522594 CN201010522594A CN102034857B CN 102034857 B CN102034857 B CN 102034857B CN 201010522594 CN201010522594 CN 201010522594 CN 201010522594 A CN201010522594 A CN 201010522594A CN 102034857 B CN102034857 B CN 102034857B
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- trap
- injection region
- triode thyristor
- bidirectional triode
- auxiliarily
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 15
- 230000001960 triggered effect Effects 0.000 title abstract 3
- 230000005669 field effect Effects 0.000 title abstract 2
- 238000002347 injection Methods 0.000 claims abstract description 75
- 239000007924 injection Substances 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 10
- 230000003068 static effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/747—Bidirectional devices, e.g. triacs
Abstract
The invention discloses a bidirectional triode thyristor auxiliarily triggered by a P-channel metal oxide semiconductor (POMS) field effect transistor. The bidirectional triode thyristor comprises a P-type substrate; a deep N trap is formed on the P-type substrate; an N trap, and a first P trap and a second P trap which are positioned on the two sides of the N trap are formed in the deep N trap; a first N+ injection region and a first P+ injection region which are separated by a first shallow ditch are formed on the first P trap; the first P+ injection region is positioned on the inner side and crosses the junction of the first P trap and the N trap; a second N+ injection region and a second P+ injection region which are separated by a second shallow ditch are formed on the second P trap; the second P+ injection region is positioned on the inner side and crosses the junction of the second P trap and the N trap; and laminated gate oxides and polysilicon gates are coated on the surface of the N trap between the first P+ injection region and the second P+ injection region. The silicon controlled thyristor can be auxiliarily triggered by a POMS tube, has a small start voltage, a simple structure, small occupied layout area, high robustness, and high starting speed and can provide a bidirectional current path.
Description
Technical field
The present invention relates to technical field of integrated circuits, relate in particular to a kind of bidirectional triode thyristor of pmos fet auxiliary triggering.
Background technology
Natural Electrostatic Discharge phenomenon is the key factor that influences IC reliability.In industrial quarters, the inefficacy 30% of integrated circuit (IC) products all is owing to suffer the static discharge phenomenon caused, and along with the continuous progress of chip manufacture technology, thinner grid oxide layer thickness, littler device size all make integrated circuit be subjected to the probability that static discharge destroys to be increased greatly.Therefore, the reliability of improving integrated circuit electrostatic discharge protection has very important effect to the rate of finished products that improves product.
The pattern of static discharge phenomenon is divided into four kinds usually: HBM (human body discharge mode), MM (machine discharge mode), CDM (assembly charging and discharging pattern) and electric field induction pattern (FIM).When static discharge took place, electric charge flowed into and flows out from the another pin from a pin of chip usually, and the electric current that this moment, electrostatic charge produced is usually up to several amperes, and the voltage that produces at the electric charge input pin is up to several volts even tens volts.Can cause the damage of inside chip if bigger ESD electric current flows into inside chip, simultaneously, the high pressure that produces at input pin also can cause internal components generation grid oxygen punch-through, thereby causes circuit malfunction.
Therefore, damaged by ESD, all will carry out effective ESD protection, the ESD electric current is released each pin of chip in order to prevent inside chip.Compare the ESD of HBM pattern simultaneously, because the CDM discharge mode usually occurs in the shorter time, so the ESD protective device has the ESD requirement of shelter that opening speed faster just can reach the CDM pattern.
In the evolution of ESD protection, diode, GGNMOS (NMOS of grid ground connection), SCR devices such as (controllable silicons) are used as the ESD protective unit usually.Wherein generally acknowledge effect reasonable be controllable silicon (silicion controlled rectifier, SCR).
Controllable silicon commonly used is the two traps of P, N on the P type substrate as shown in Figure 1, respectively is provided with two injection regions on P trap and the N trap, is respectively N+ injection region and P+ injection region.Wherein the N+ injection region of N trap is arranged on the end away from the P trap, and the P+ injection region of N trap is arranged on the end near the P trap; The P+ injection region of P trap is arranged on the end away from the N trap, and the N+ injection region of P trap is arranged on the end near the N trap.A N+ injection region is arranged on N trap and top, P trap junction and is connected across the cut-in voltage that is used for reducing SCR between N trap and the P trap, uses shallow trench to isolate (STI) between all injection regions.The N+ injection region of N trap and P+ injection region connect electrical anode (Anode), and the N+ injection region of P trap and P+ injection region connect electrical cathode (Cathode).Fig. 2 is and the corresponding circuit theory diagrams of this SCR structure.
Under the normal operating conditions of integrated circuit, electrostatic discharge protector is to be in closing state, can not influence the current potential on the input and output pin.And externally static pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, emits electrostatic induced current rapidly.But this SCR trigger voltage is generally higher, can not effectively protect for the chip of 5V and following operating voltage.
Summary of the invention
The invention provides a kind of bidirectional triode thyristor of pmos fet auxiliary triggering, this device trigger voltage is low, and opening speed is fast, and the bi-directional ESD protection can be provided.
A kind of bidirectional triode thyristor of pmos fet auxiliary triggering comprises P type substrate, and P type substrate is provided with dark N trap, the P trap and the 2nd P trap that are provided with the N trap and are positioned at N trap both sides in the dark N trap;
The one P trap is provided with a N+ injection region and a P+ injection region that isolates by the first shallow trench, and a P+ injection region is positioned at the inboard and across the intersection of a P trap and N trap; The 2nd P trap is provided with the 2nd N+ injection region and the 2nd P+ injection region that isolates by the second shallow trench, and second injects that the P+ injection region is positioned at the inboard and across the intersection of the 2nd P trap and N trap;
N trap surface between the one P+ injection region and the 2nd P+ injection region is covered with stacked grid oxygen and polysilicon gate.
The present invention also provides the application of above-mentioned bidirectional triode thyristor in the ESD protection, comprising:
The one N+ injection region is connected electrical anode with a P+ injection region, and the 2nd N+ injection region is connected electrical cathode with the 2nd P+ injection region, and polysilicon gate connects power supply.
A P+ injection region is equivalent to the source electrode of PMOS structure in the device of the present invention, and the 2nd P+ injection region is equivalent to the drain electrode of PMOS structure, and the polysilicon gate of grid oxygen top is equivalent to the grid of PMOS structure, and the N trap of polysilicon gate below is the raceway groove of PMOS pipe.
Use controllable silicon, controllable silicon of the present invention to utilize PMOS pipe auxiliary triggering with respect to traditional ESD protection, cut-in voltage is little, and is simple in structure, and it is little to take chip area, and the bidirectional current path can be provided, and robustness is good, and opening speed is fast.
Description of drawings
Fig. 1 is existing ESD protection silicon controlled structural representation;
Fig. 2 is a protection silicon controlled equivalent circuit diagram shown in Figure 1;
Fig. 3 is the profile of ESD protection bidirectional triode thyristor of the present invention;
Fig. 4 is the vertical view of ESD protection bidirectional triode thyristor shown in Figure 3;
Fig. 5 is the equivalent circuit diagram of ESD protection bidirectional triode thyristor shown in Figure 3.
Embodiment
As shown in Figure 3 and Figure 4, a kind of bidirectional triode thyristor of pmos fet auxiliary triggering, comprise 4 layers of structure, wherein bottom is a P type substrate 31, the second layer is the dark N trap 33a that is located on the P type substrate 31, and 33a is provided with N trap 33b, a P trap 32a and the 2nd P trap 32b in the dark N trap, and wherein a P trap 32a and the 2nd P trap 32b are positioned at the both sides of N trap 33b, dark N trap 33a is a P substrate 31 and a P trap 32a, and the 2nd P trap 32b separates.
The 3rd layer is 2 N+ injection regions and 2 the P+ injection regions above being located at well region, wherein a N+ injection region 34a and the 2nd N+ injection region 34b are located at the top of a P trap 32a and the 2nd P trap 32b respectively and are positioned at the outside, the one P+ injection region 36a and the 2nd P+ injection region 36b are positioned at the inboard, wherein a P+ injection region 36a is across the intersection of a N trap 33b and a P trap 32a, and the 2nd P+ injection region 36b is across the intersection of N trap 33b and the 2nd P trap 32b.Isolate by the first shallow trench 35a between the one a N+ injection region 34a and the P+ injection region 36a, isolate by the second shallow trench 35b between the 2nd N+ injection region 34b and the 2nd P+ injection region 36b.
The 4th layer for being overlying on the grid oxygen 37 and the polysilicon gate 38 on the N trap surface between a P+ injection region 36a and the 2nd P+ injection region 36b.
In this controllable silicon, a P+ injection region 36a is equivalent to the source electrode of PMOS structure, and the 2nd P+ injection region 36b is equivalent to the drain electrode of PMOS structure, and the polysilicon gate 38 of grid oxygen 37 tops is equivalent to the grid of PMOS structure, and the N trap of grid oxygen 37 belows is the raceway groove of PMOS structure.P type substrate in the present embodiment, the P trap, the N trap, P+ injection region, N+ injection region and pmos fet structure adopt existing standard CMOS integrated circuit fabrication process to realize.
During application, a N+ injection region 34a and a P+ injection region 36a all insert electrical anode, and the 2nd N+ injection region 34b and the 2nd P+ injection region 36b all insert electrical cathode; Polysilicon gate 38 inserts the chip operation power supply by resistance.Under the ESD signal from the anode to the negative electrode, constitute silicon controlled P-N-P-N structure by a P+ injection region 36a and a P trap 32a-N trap 33b-the 2nd P trap 32b-the 2nd N+ injection region 34b respectively.Under the ESD signal from the negative electrode to the anode, constitute reverse silicon controlled P-N-P-N structure by the 2nd P trap 32b and the 2nd P+ injection region 36b-N trap 33b-the one P trap 32a-the one N+ injection region 34a respectively.
As shown in Figure 5, by a N+ injection region 34a, a P trap 32a and N trap 33b constitute NPN parasitic transistor Q1; By a P+ injection region 36a, N trap 33b and the 2nd P+ injection region 36b constitute PNP parasitic transistor Q2; By N trap 33b, the 2nd P trap 32b and the 2nd N+ injection region 34b constitute NPN parasitic transistor Q3.
As shown in Figure 5, when the ESD signal appears in anode, bigger voltage difference can cause PMOS to open between anode and PMOS grid, electric current arrives a P+ injection region earlier from anode, flow to the 2nd P+ injection region through the N trap and enter negative electrode, the trap resistance that the trigger current of the PMOS that produces flows through the 2nd P trap produces pressure drop, when the cut-in voltage of this pressure drop greater than NPN parasitic triode Q3, NPN parasitic triode Q3 opens, simultaneously because positive feedback is also opened PNP parasitic triode Q2, the whole SCR device that is made of PNP parasitic triode Q2 and NPN parasitic triode Q3 is switched on, and the ESD electric current that begins to release is clamped down on the SCR both end voltage simultaneously than electronegative potential.Because symmetrical configuration, same principle, when the ESD signal appearred in negative electrode, the whole SCR device that is made of PNP parasitic triode Q2 and NPN parasitic transistor Q1 also can discharge the ESD electric current from the negative electrode to the anode.
In actual applications, change the polysilicon gate and the length of grid oxygen and the length and width that width is PMOS and can adjust the size of PMOS trigger current, thereby adjust the cut-in voltage of this structure under the ESD signal.Change negative electrode and can adjust clamp voltage to the distance of anode.Gate series resistance rationally is set realizes chip when being subjected to ESD, electrical cathode or anode and PMOS grid produce voltage difference, thereby guarantee that PMOS in time opens with the SCR in this invention structure of auxiliary triggering.In application, these device sizes rationally are set the bolt-lock effect can take place in normal operation, and come the interim ESD electric current of releasing of in time opening at ESD to guarantee this ESD protective device.
Claims (1)
1. the bidirectional triode thyristor of a pmos fet auxiliary triggering comprises P type substrate, it is characterized in that: P type substrate is provided with dark N trap, the P trap and the 2nd P trap that are provided with the N trap and are positioned at N trap both sides in the dark N trap;
The one P trap is provided with a N+ injection region and a P+ injection region that isolates by the first shallow trench, and a P+ injection region is positioned at the inboard and across the intersection of a P trap and N trap; The 2nd P trap is provided with the 2nd N+ injection region and the 2nd P+ injection region that isolates by the second shallow trench, and second injects that the P+ injection region is positioned at the inboard and across the intersection of the 2nd P trap and N trap;
N trap surface between the one P+ injection region and the 2nd P+ injection region is covered with stacked grid oxygen and polysilicon gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 201010522594 CN102034857B (en) | 2010-10-28 | 2010-10-28 | Bidirectional triode thyristor auxiliarily triggered by POMS field effect transistor |
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| CN 201010522594 CN102034857B (en) | 2010-10-28 | 2010-10-28 | Bidirectional triode thyristor auxiliarily triggered by POMS field effect transistor |
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| CN102034857A CN102034857A (en) | 2011-04-27 |
| CN102034857B true CN102034857B (en) | 2011-12-14 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263102B (en) * | 2011-04-28 | 2012-12-19 | 浙江大学 | Backward diode-triggered thyristor for electrostatic protection |
| CN106920843B (en) * | 2015-12-24 | 2024-01-09 | 大唐恩智浦半导体有限公司 | Electrostatic protection circuit and silicon controlled rectifier thereof |
| CN106024903A (en) * | 2016-07-27 | 2016-10-12 | 上海集成电路研发中心有限公司 | PMOS device structure and manufacturing method thereof |
| CN107093596A (en) * | 2017-04-12 | 2017-08-25 | 华为技术有限公司 | A kind of SCR, chip and system for electrostatic protection |
| CN111384046A (en) * | 2020-04-27 | 2020-07-07 | 上海华力微电子有限公司 | Silicon controlled rectifier and manufacturing method thereof |
| CN111354724A (en) * | 2020-04-27 | 2020-06-30 | 上海华力微电子有限公司 | Silicon controlled rectifier and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7202114B2 (en) * | 2004-01-13 | 2007-04-10 | Intersil Americas Inc. | On-chip structure for electrostatic discharge (ESD) protection |
| CN101281899A (en) * | 2008-05-16 | 2008-10-08 | 浙江大学 | PMOS pipe built-in bidirectional thyristor electrostatic protection device |
| CN101771041A (en) * | 2010-01-19 | 2010-07-07 | 浙江大学 | Complementary type SCR (Silicon Controlled Rectifier) structure by auxiliary triggering of PMOS (P-channel Metal Oxide Semiconductor) field effect transistors |
| CN101789428A (en) * | 2010-03-10 | 2010-07-28 | 浙江大学 | Embedded PMOS auxiliary trigger SCR structure |
| CN101807598A (en) * | 2010-03-17 | 2010-08-18 | 浙江大学 | PNPNP type triac |
| CN101834181A (en) * | 2010-03-23 | 2010-09-15 | 浙江大学 | SCR (Silicon Controlled Rectifier) circuit with auxiliary triggering of NMOS (N-channel Metal Oxide Semiconductor) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004531047A (en) * | 2000-11-06 | 2004-10-07 | サーノフ コーポレイション | Silicon controlled rectifier electrostatic discharge protection device with compact internal dimensions and external on-chip triggering for fast triggering |
| US8618608B2 (en) * | 2008-12-31 | 2013-12-31 | United Microelectronics Corp. | Lateral silicon controlled rectifier structure |
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- 2010-10-28 CN CN 201010522594 patent/CN102034857B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7202114B2 (en) * | 2004-01-13 | 2007-04-10 | Intersil Americas Inc. | On-chip structure for electrostatic discharge (ESD) protection |
| CN101281899A (en) * | 2008-05-16 | 2008-10-08 | 浙江大学 | PMOS pipe built-in bidirectional thyristor electrostatic protection device |
| CN101771041A (en) * | 2010-01-19 | 2010-07-07 | 浙江大学 | Complementary type SCR (Silicon Controlled Rectifier) structure by auxiliary triggering of PMOS (P-channel Metal Oxide Semiconductor) field effect transistors |
| CN101789428A (en) * | 2010-03-10 | 2010-07-28 | 浙江大学 | Embedded PMOS auxiliary trigger SCR structure |
| CN101807598A (en) * | 2010-03-17 | 2010-08-18 | 浙江大学 | PNPNP type triac |
| CN101834181A (en) * | 2010-03-23 | 2010-09-15 | 浙江大学 | SCR (Silicon Controlled Rectifier) circuit with auxiliary triggering of NMOS (N-channel Metal Oxide Semiconductor) |
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