CN1297002C - Electrostatic discharge protection circuit - Google Patents
Electrostatic discharge protection circuit Download PDFInfo
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- CN1297002C CN1297002C CNB031153984A CN03115398A CN1297002C CN 1297002 C CN1297002 C CN 1297002C CN B031153984 A CNB031153984 A CN B031153984A CN 03115398 A CN03115398 A CN 03115398A CN 1297002 C CN1297002 C CN 1297002C
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- esd protection
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Abstract
The present invention provides an electrostatic discharging protective circuit which is suitable for a connecting pad of an output/input circuit capable of withstanding high voltage. The present invention comprises a first switch and a second switch, wherein the first switch is coupled with the first electric potential and is provided with a first control gate, and the second switch is coupled between the first switch and the connecting pad and is provided with a second control gate and a conduction critical voltage value. A delay circuit is coupled with the second control gate and provides the second electric potential in circuit operation. When the connecting pad has electrostatic discharge voltage, the delay circuit temporarily keeps the voltage electric potential of the second control gate below the third electric potential of the conduction critical voltage value.
Description
Technical field
The present invention is relevant for a kind of ESD protection circuit; specifically, go up the ESD protection circuit of switch gate voltage in the stacked switch by voltage control circuit control output/input circuit relevant for a kind of output/go in the circuit 5 volts of 3 volts/tolerances.
Background technology
Static discharge (Electrostatic Discharge, below be called for short with ESD) is prevalent in measurement, assembling, installation and the use of integrated circuit, and it may cause the damage of integrated circuit, and the function of remote-effects electronic system.Yet, form the reason of ESD stress, modal is following three kinds of models: (1) human body discharge mode (human bodymodel): No. 883 method 3015.6 (MIL-STD-883 of U.S. army's 105D military standard 105D, Method 3015.6) model that defined, the ESD stress that it is caused when representing human body institute static electrification to touch the pin of integrated circuit.(2) machine pattern (machinemodel): the ESD stress that machine institute static electrification is caused when touching IC bond, to have the method for measurement that industrial standard EIAJ-IC-121 method 20 is defined now.(3) charge element pattern (charge device model): the former integrated circuit that has had electric charge is in process subsequently, and therefore contact ground connection conductive materials forms an esd pulse path to integrated circuit.
The ESD protection circuit of generally mentioning, majority be meant be used for protecting the human body discharge mode (human body mode, HBM) or machine discharge mode (machine mode, static discharge MM).Basically, the static discharge of this type of HBM or MM, the electric charge of its static discharge are to come from integrated circuit (integrated circuit, external world IC) enter in the IC via certain pin position (pin) of IC, go out IC via another pin bit stream then.In order to take precautions against this type of ESD to the damage that IC caused, therefore, the ESD protection circuit all designs in the IC layout near joint sheet (bonding pad), uses the ESD of bypass discharging nearby electric current.Consult Fig. 1, Fig. 1 has shown traditional ESD protection circuit, and it is applied to the output of tolerating high voltage/go into circuit.The output that 3 volts/tolerance as shown in Figure 1 is 5 volts/go into circuit, the PMOS transistor Mp1 of back level output buffer 10 is arranged in the N type trap (not shown) of suspension joint (floating).In addition, the voltage quasi position exported when normal running of joint sheet 12 is 0 to 5V.5 volts the voltage of being exported for fear of joint sheet 12 produces too high stress for the grid of the NMOS of back level output buffer 10, and the NMOS in the level output buffer 10 of back partly is the framework that piles up with nmos pass transistor Mn1a and Mn1b and constituting.The grid bias of nmos pass transistor Mn1a is at VDD (3.3V), and the grid of nmos pass transistor Mn1b is subjected to the control of prime output buffer 14.So, when the signal in the external world during, can guarantee that the cross-pressure of the gate oxide of nmos pass transistor Mn1a and Mn1b can not surpass 3.3 volts, the reliability issues that is caused to avoid under the high voltage stress between 0 to 5 volt.
When the esd event that is just impacting betides joint sheet 12, output circuit among Fig. 1 mainly is by colonizing in NPN bipolarity junction transistor (the bipolar junctiontransistor under two nmos pass transistors that pile up (Mn1a and Mn1b), BJT), utilize returning of NPN BJT (snap-back) effect of speeding to discharge the ESD electric current.Yet, if the drain electrode of just using Mn1a triggers NPN BJT to the face that the connects collapse electric current of the substrate (bulk) at Mn1b place, the drain electrode of nmos pass transistor and the breakdown voltage between the substrate are suitable height after all, and its triggering speed may be crossed slow and cause ESD protective benefits deficiency.
In order to improve the electrostatic discharge capacity for the HMB/MM esd event, p type impurity 18 is mixed in drain electrode place of the nmos pass transistor Mn1a of conventional art joint sheet 12 near, and boron (B) is for example used and reduced the breakdown voltage that PN herein connects face.Therefore, when joint sheet 12 receives a large amount of electrostatic stresses suddenly, drain electrode place of nmos pass transistor Mn1a will be collapsed in advance and static discharge current is released into earth point, uses the injury of avoiding internal circuit to be subjected to electrostatic stress, and then causes the problem of reliability.
Yet the employed mode of above-mentioned conventional art must additionally increase a photoetching etching step to mix p type impurity 18.This additional light etching is carved step influences the very play of technology cost.Moreover the p type impurity 18 that is mixed can improve the parasitic capacitance of nmos pass transistor Mn1a, and then causes the delay of back level output buffer 10 internal circuits, has reduced the operating efficiency of circuit element.
Summary of the invention
In view of this; in order to address the above problem; main purpose of the present invention is to provide a kind of ESD protection circuit; output/go in the circuit 5 volts of 3 volts/tolerances; by a delay circuit when the electrostatic discharge event; go up the grid voltage of switch in electronegative potential in the stacked switch of control output/input circuit; make voltage collapse betide the last switch of stacked switch; and make static discharge current flow to earth point by substrate; so reduced the surface current density at the semiconductor-based end, and then improved the static discharge ability to bear of circuit.
For obtaining above-mentioned purpose, the present invention proposes a kind of ESD protection circuit,, be applicable to a joint sheet, comprising:
First switch is coupled to first current potential, has first control gate of the control signal of being coupled to;
Second switch is coupled between above-mentioned first switch and the joint sheet, has second control gate and a conducting critical voltage value; And
Delay circuit is coupled to above-mentioned second control gate, when circuit operation, provides second current potential, and when static discharge voltage appears in above-mentioned joint sheet, and the voltage potential of above-mentioned second control gate is temporarily remained in the 3rd current potential that is lower than above-mentioned conducting critical voltage value;
Described first switch and second switch are MOS transistor.
The present invention also provides a kind of ESD protection circuit, is applicable to a joint sheet, comprising:
First switch is coupled to one first current potential, has first control gate that is coupled to a control signal;
Second switch is coupled between above-mentioned first switch and the joint sheet, has second control gate, a parasitic capacitance and a conducting critical voltage value; And
One delay circuit has an electric capacity, is coupled between above-mentioned second control gate and second current potential, when circuit operation, provides second current potential, and when static discharge voltage appears in above-mentioned joint sheet, postpones the voltage potential of above-mentioned second control gate;
Described first switch and second switch are MOS transistor.
Description of drawings
For above-mentioned purpose, the feature and advantage that make the present invention can become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 has shown traditional ESD protection circuit.
Fig. 2 has shown according to the described ESD protection circuit of the embodiment of the invention.
Fig. 3 has shown according to the described ESD protection circuit of another embodiment of the present invention.
Embodiment
Consult Fig. 2, Fig. 2 shown according to the described ESD protection circuit of the embodiment of the invention, and it is applied to the output of tolerating high voltage/go into circuit.The output that as shown in Figure 23 volts/tolerance is 5 volts/go into circuit.The PMOS transistor Mp11 of back level output buffer 20 is arranged in the N type trap (not shown) of suspension joint (floating).In addition, the voltage potential exported when normal running of joint sheet 22 is 0 to 5V.5 volts the voltage of being exported for fear of joint sheet 22 produces too high stress for the grid of the nmos pass transistor of back level output buffer 20, and the NMOS in the level output buffer 20 of back partly is the framework that piles up with nmos pass transistor Mn11a and Mn11b and constituting.The grid of nmos pass transistor Mn11a is coupled to delay circuit 26.
Delay circuit 26 comprises resistor 2610 and capacitor 262.Resistor 2610 is coupled to power line V
DD(3.3V) and the grid of nmos pass transistor Mn11a, and capacitor is coupled between the grid and earth point of nmos pass transistor Mn11a.The grid of nmos pass transistor Mn11b is subjected to the control of prime output buffer 24.Therefore, when the signal of input joint sheet 22 during, can guarantee that the gate oxide cross-pressure of nmos pass transistor Mn11a and nmos pass transistor Mn11b can be above 3.3 volts, the reliability issues that is caused to avoid under the high voltage stress between 0 to 5 volt.
In addition, Fig. 2 has shown that according to the described ESD protection circuit of another embodiment of the present invention as shown in Figure 3, delay circuit 26 comprises PMOS transistor 2612 and capacitor 262.PMOS transistor 2612 is coupled to power line V
DD(3.3V) and the grid of nmos pass transistor Mn11a, and its grid is coupled to earth point, so PMOS transistor 2612 is conductings always, can be considered a resistance.In addition, capacitor is coupled between the grid and earth point of nmos pass transistor Mn11a.And the grid of nmos pass transistor Mn11b is subjected to the control of prime output buffer 24.Therefore, when the signal of input joint sheet 22 during, can guarantee that the gate oxide cross-pressure of nmos pass transistor Mn11a and nmos pass transistor Mn11b can be above 3.3 volts, the reliability issues that is caused to avoid under the high voltage stress between 0 to 5 volt.
When the circuit normal running, power line V
DDCan make normal running identical to electric capacity 262 chargings with known technology.And when doing electrostatic discharge testing, at this moment with all power grounds, and in a large amount of static discharge currents of joint sheet 22 inputs.When joint sheet 22 receives a large amount of static discharge currents suddenly, have quite high voltage and be coupled to the drain electrode of nmos pass transistor Mn11a and the parasitic capacitance between grid this moment, and this voltage is because the effect of coupling (coupling) can be coupled to capacitor 262.Yet, for avoiding nmos pass transistor Mn11a conducting immediately when the electrostatic discharge testing, cause a large amount of static discharge currents directly by the passage of nmos pass transistor Mn11a and nmos pass transistor Mn11b by causing damage, can slow down the speed that nmos pass transistor Mn11a gate terminal voltage rises by the setting of capacitor 262.Therefore, in the process of carrying out electrostatic discharge testing, nmos pass transistor Mn11a is because the influence of capacitor 262 remains on closing state.So the time static discharge voltage only can flow to the substrate that constitutes MOS transistor Mn11a and nmos pass transistor Mn11b by the mode of voltage collapse, and discharge by earth point, thus, effectively avoid static discharge current to concentrate on the surface of stacked NMOS transistors Mn11a and nmos pass transistor Mn11b, and make the bigger substrate of its volume of flowing through, make the ESD CURRENT DISTRIBUTION comparatively even, that is reduce the ESD electric current, so effectively strengthen the releasability of ESD electric current and the tolerance of ESD in the distribution density of substrate surface.
According to the embodiment of the invention, go up the transistorized grid voltage rate of climb in the stacked transistors by the output/input circuit that postpones 5 volts of 3 volts/tolerances and be gathered in the channel surface of stacked transistors to avoid the ESD electric current, improve electrostatic discharge capacity effectively.Moreover, because disclosed circuit structure is simple, compare the employed photoengraving lithography of conventional art, significantly reduce cost and the complexity of making, have the usability of industry.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention; anyly be familiar with present technique field person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, protection range therefore of the present invention defines and is as the criterion when looking accompanying Claim book scope.
Claims (18)
1. an ESD protection circuit is applicable to a joint sheet, comprising:
First switch is coupled to first current potential, has first control gate of the control signal of being coupled to;
Second switch is coupled between above-mentioned first switch and the joint sheet, has second control gate and a conducting critical voltage value; And
Delay circuit is coupled to above-mentioned second control gate, when circuit operation, provides second current potential, and when static discharge voltage appears in above-mentioned joint sheet, and the voltage potential of above-mentioned second control gate is temporarily remained in the 3rd current potential that is lower than above-mentioned conducting critical voltage value;
Described first switch and second switch are MOS transistor.
2. ESD protection circuit as claimed in claim 1 is characterized in that, above-mentioned delay circuit comprises:
Electric capacity is coupled between above-mentioned second control gate and first current potential; And
Resistance when electrostatic discharge testing, is coupled between above-mentioned first current potential and second control gate.
3. ESD protection circuit as claimed in claim 1 is characterized in that, above-mentioned delay circuit comprises:
Electric capacity is coupled between above-mentioned second control gate and first current potential; And
The P transistor npn npn when electrostatic discharge testing, is coupled between above-mentioned first current potential and second control gate, and has the 3rd control gate that is coupled to above-mentioned first current potential.
4. ESD protection circuit as claimed in claim 1 is characterized in that, also comprises a prime buffer circuit, in order to above-mentioned control signal to be provided.
5. as claim 2 or 3 described ESD protection circuits, it is characterized in that above-mentioned second switch has a parasitic capacitance.
6. ESD protection circuit as claimed in claim 5 is characterized in that, above-mentioned delay circuit is coupled to above-mentioned static discharge voltage above-mentioned electric capacity and produces above-mentioned the 3rd current potential by above-mentioned parasitic capacitance.
7. ESD protection circuit as claimed in claim 1 is characterized in that, above-mentioned first switch and second switch are nmos pass transistor.
8. ESD protection circuit as claimed in claim 1 is characterized in that, above-mentioned first current potential is an earthing potential.
9. ESD protection circuit as claimed in claim 1 is characterized in that, above-mentioned second current potential is the current potential of power line.
10. ESD protection circuit as claimed in claim 1 is characterized in that the potential value of the high potential signal that above-mentioned joint sheet is exported is higher than above-mentioned first current potential when normal running.
11. an ESD protection circuit is applicable to a joint sheet, comprising:
First switch is coupled to one first current potential, has first control gate that is coupled to a control signal;
Second switch is coupled between above-mentioned first switch and the joint sheet, has second control gate, a parasitic capacitance and a conducting critical voltage value; And
One delay circuit has an electric capacity, is coupled between above-mentioned second control gate and second current potential, when circuit operation, provides second current potential, and when static discharge voltage appears in above-mentioned joint sheet, postpones the voltage potential of above-mentioned second control gate;
Described first switch and second switch are MOS transistor.
12. ESD protection circuit as claimed in claim 11 is characterized in that, also comprises a prime buffer circuit, in order to above-mentioned control signal to be provided.
13. ESD protection circuit as claimed in claim 11 is characterized in that, above-mentioned first switch and second switch are nmos pass transistor.
14. ESD protection circuit as claimed in claim 11 is characterized in that, above-mentioned first current potential is an earthing potential.
15. ESD protection circuit as claimed in claim 11 is characterized in that, above-mentioned second current potential is the current potential of power line.
16. ESD protection circuit as claimed in claim 11 is characterized in that, the potential value of the high potential signal that above-mentioned joint sheet is exported when normal running is higher than above-mentioned first current potential.
17. ESD protection circuit as claimed in claim 11 is characterized in that, above-mentioned delay circuit more comprises the resistance that is coupled between above-mentioned second current potential and second control gate.
18. ESD protection circuit as claimed in claim 11; it is characterized in that; above-mentioned delay circuit also comprises a P transistor npn npn, and above-mentioned P transistor npn npn is coupled between above-mentioned second current potential and second control gate, and has the 3rd control gate that is coupled to above-mentioned first current potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031153984A CN1297002C (en) | 2003-02-14 | 2003-02-14 | Electrostatic discharge protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031153984A CN1297002C (en) | 2003-02-14 | 2003-02-14 | Electrostatic discharge protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1521845A CN1521845A (en) | 2004-08-18 |
| CN1297002C true CN1297002C (en) | 2007-01-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031153984A Expired - Lifetime CN1297002C (en) | 2003-02-14 | 2003-02-14 | Electrostatic discharge protection circuit |
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| Country | Link |
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| CN (1) | CN1297002C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102118024B (en) * | 2009-12-30 | 2014-07-02 | 上海天马微电子有限公司 | Static protection circuit, in particular static protection circuit of liquid crystal display panel and static protection circuit array of liquid crystal display panel |
| CN103022996B (en) * | 2011-09-21 | 2015-02-11 | 中芯国际集成电路制造(北京)有限公司 | Electronic static discharge protection circuit and electronic static discharge protection method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5521789A (en) * | 1994-03-15 | 1996-05-28 | National Semiconductor Corporation | BICMOS electrostatic discharge protection circuit |
| CN1381885A (en) * | 2001-04-13 | 2002-11-27 | 华邦电子股份有限公司 | I/O port with high voltage tolerance and electrostatic discharge protection circuit |
-
2003
- 2003-02-14 CN CNB031153984A patent/CN1297002C/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5521789A (en) * | 1994-03-15 | 1996-05-28 | National Semiconductor Corporation | BICMOS electrostatic discharge protection circuit |
| CN1381885A (en) * | 2001-04-13 | 2002-11-27 | 华邦电子股份有限公司 | I/O port with high voltage tolerance and electrostatic discharge protection circuit |
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| Publication number | Publication date |
|---|---|
| CN1521845A (en) | 2004-08-18 |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111129 |
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Effective date of registration: 20111129 Address after: 201203 No. 18 Zhangjiang Road, Shanghai Co-patentee after: Semiconductor Manufacturing International (Beijing) Corp. Patentee after: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Address before: 201203 No. 18 Zhangjiang Road, Shanghai Patentee before: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. |
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Granted publication date: 20070124 |