TWI431753B - Esd protection circuit with eos immunity - Google Patents
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Description
本發明係有關具有電子過壓(EOS,Electric Over-Stress)防護能力的靜電放電(ESD,Electro-Static Discharge)保護電路,尤指一種可防止電子過壓錯誤導通靜電放電保護電路故能兼顧電子過壓防護與靜電放電保護之靜電放電保護電路。The present invention relates to an ESD (Electro-Static Discharge) protection circuit having an EOS (Electric Over-Stress) protection capability, and more particularly to an electronic overvoltage prevention circuit that can prevent an electronic overvoltage from being turned on. Electrostatic discharge protection circuit for overvoltage protection and electrostatic discharge protection.
晶粒(die)、晶片(chip)及積體電路是現代資訊社會最重要的硬體基礎。為了和其他電路(像是電路板及/或其他晶片)相互交換資訊,晶片內會設置有輸出入介面;由於此輸出入介面會以接墊/針腳/焊球等導電結構和晶片外界的電子/電氣環境直接接觸,晶片外界發生的各種電子異常事件就會經由此輸出入介面而傳導至晶片中,導致晶片功能異常或損壞。Dies, chips, and integrated circuits are the most important hardware foundations of the modern information society. In order to exchange information with other circuits (such as circuit boards and/or other chips), an input/output interface is provided in the chip; since the input/output interface is a conductive structure such as a pad/pin/solder ball and an electron outside the wafer / The electrical environment is in direct contact, and various electronic anomalies occurring outside the wafer are transmitted to the wafer through the output interface, resulting in abnormal or damaged function of the wafer.
因此,本發明即是要為晶片(晶粒、積體電路)的輸出入介面提出一種具有電子過壓防護能力的靜電放電保護電路,以便保護晶片的內部電路,使其不受外界靜電放電與電子過壓等電子異常事件的影響。Therefore, the present invention is to provide an electrostatic discharge protection circuit with electronic overvoltage protection capability for the input/output interface of a wafer (die, integrated circuit), so as to protect the internal circuit of the wafer from external electrostatic discharge and The effects of electronic anomalies such as electronic overvoltages.
一般來說,在晶片輸出入介面可能遭遇的各種電子異常事件中,靜電放電(ESD,Electro-Static Discharge)是導因於靜電累積之電荷突然被傳輸至輸出入介面的導電結構(接墊/針腳/焊球等)。靜電放電的本質類似一個電荷源,會快速地(譬如約十億分之一秒至數十億分之一秒的等級)因電荷累積而在導電結構上建立高電壓;但只要能將其電流導流至晶片外而迅速地使電荷源逸散,就可防止電荷累積的高電壓破壞晶片的內部電路。因此,靜電放電保護電路會在偵測到靜電放電時提供電流路徑來疏導靜電放電的電流(電荷)。In general, in various electronic anomalies that may be encountered in the wafer input and output interface, Electro-Static Discharge (ESD) is a conductive structure in which the charge accumulated due to static electricity is suddenly transmitted to the input/output interface (pad/ Pins/solder balls, etc.). The essence of electrostatic discharge is similar to a charge source, which quickly establishes a high voltage on the conductive structure due to charge accumulation (for example, on the order of about one billionth of a second to several billionths of a second); Dividing to the outside of the wafer and quickly dissipating the charge source prevents the high voltage of charge accumulation from damaging the internal circuitry of the wafer. Therefore, the ESD protection circuit provides a current path to divert the current (charge) of the ESD when an ESD is detected.
除了上述的靜電放電,近年來,另一種被稱為電子過壓(EOS,Electrical Over-Stress)的電子異常事件也逐漸受到重視。一般來說,電子過壓是導因於晶片的導電結構錯誤地連接至不當的電壓;譬如說,在晶片被加工組裝(像是被固定、安裝、焊接於電路板)時,及/或是在測試過程中,都有可能因連接或操作不慎而使晶片之導電結構錯誤地短路或連接至過高的電壓。相較於靜電放電因電荷累積而快速造成高電壓的特性,電子過壓的本質比較類似於一個持續時間較久(譬如,超過百萬分之一秒的等級,或甚至達到一至數秒)的電壓源;若晶片中的靜電放電保護電路在遭遇電子過壓時導通電流路徑,此一電流路徑就會持續導通大電流,反而容易因電流過大而破壞靜電放電保護電路。針對上述問題,本發明就是要提出一種能兼顧電子過壓防護能力的靜電放電保護電路,不僅能在遭遇靜電放電時提供電荷逸散的電流路徑,也能在電子過壓時大幅增強電流路徑的等效電阻,避免電子過壓的高電壓與大電流破壞晶片的靜電放電保護電路以及內部電路。In addition to the above-described electrostatic discharge, in recent years, another electronic anomaly called EOS (Electrical Over-Stress) has also received increasing attention. In general, electronic overvoltage is caused by the erroneous connection of the conductive structure of the wafer to an improper voltage; for example, when the wafer is processed and assembled (such as being fixed, mounted, soldered to the board), and/or During the test, it is possible that the conductive structure of the wafer is erroneously short-circuited or connected to an excessive voltage due to inadvertent connection or operation. Compared to the fact that electrostatic discharges quickly cause high voltages due to charge accumulation, the nature of electronic overvoltage is similar to a voltage that lasts for a long time (for example, a level of more than one millionth of a second, or even one to several seconds). Source; if the ESD protection circuit in the chip conducts the current path when encountering an electronic overvoltage, the current path will continue to conduct a large current, and it is easy to damage the ESD protection circuit due to excessive current. In view of the above problems, the present invention is to propose an electrostatic discharge protection circuit capable of taking into consideration the electronic overvoltage protection capability, which not only provides a current path for the charge to escape when subjected to electrostatic discharge, but also greatly enhances the current path when the electronic overvoltage occurs. Equivalent resistance, avoiding high voltage and high current of electronic overvoltage destroying the electrostatic discharge protection circuit of the chip and internal circuit.
本發明的目的之一,是提供一種靜電放電保護電路,其包括有一第一連接電路,一第一過壓控制電路、一第二過壓控制電路、一靜電放電箝制電路,並搭配一電源箝制電路與一第三連接電路,以在一晶片的輸出入介面(輸出入電路)中實現本發明之技術精神。第一連接電路耦接於一接墊與一第一箝制節點之間;此第一連接電路可由一二極體(陽極與陰極分別耦接於接墊與第一箝制節點)、一p通道金氧半場效電晶體(閘極、源極與體極(bulk)耦接於第一箝制節點,汲極耦接於接墊)或一p-n-p雙載子接面電晶體(射極與基極耦接於第一箝制節點,集極耦接於接墊)形成;譬如說,此第一連接電路可在接墊與第一箝制節點間形成p-n接面(p-n junction)。An object of the present invention is to provide an electrostatic discharge protection circuit including a first connection circuit, a first overvoltage control circuit, a second overvoltage control circuit, an electrostatic discharge clamp circuit, and a power supply clamp The circuit and a third connecting circuit realize the technical spirit of the present invention in an input/output interface (input and output circuit) of a wafer. The first connecting circuit is coupled between a pad and a first clamping node; the first connecting circuit can be coupled to a diode (the anode and the cathode are respectively coupled to the pad and the first clamping node), and a p-channel gold Oxygen half-field effect transistor (gate, source and body are coupled to the first clamp node, the drain is coupled to the pad) or a pnp bi-carrier junction transistor (emitter and base coupling) Connected to the first clamping node, the collector is coupled to the pad); for example, the first connecting circuit can form a pn junction between the pad and the first clamping node.
第一過壓控制電路則耦接於第一箝制節點與一輸出入箝制節點之間,其可包含有至少一p-n接面元件(像是二極體),以在第一箝制節點與輸出入箝制節點間形成p-n接面;譬如說,第一過壓控制電路可由一或多個相互串連的二極體形成,各串連二極體間以陰極耦接至另一二極體之陽極,並有一二極體之陽極耦接於第一箝制節點、有一二極體之陰極耦接於輸出入箝制節點。The first overvoltage control circuit is coupled between the first clamp node and an input/output clamp node, and may include at least one pn junction component (such as a diode) for the first clamp node and the input and output Forming a pn junction between the clamped nodes; for example, the first overvoltage control circuit may be formed by one or more diodes connected in series with each other, and the cathodes of the series connected diodes are coupled to the anode of the other diode The anode of one of the diodes is coupled to the first clamp node, and the cathode of one of the diodes is coupled to the input and output clamp node.
類似地,第二過壓控制電路亦耦接於第一箝制節點與一輸出入箝制節點之間,其可包含有至少一p-n接面元件(像是二極體),以在輸出入箝制節點與第一箝制節點間形成p-n接面。譬如說,第二過壓控制電路可由一或多個相互串連的二極體形成,各串連二極體間以陰極耦接至另一二極體之陽極,並有一二極體之陽極耦接於輸出入箝制節點、有一二極體之陰極耦接於第一箝制節點。Similarly, the second overvoltage control circuit is also coupled between the first clamp node and an output clamp node, and may include at least one pn junction component (such as a diode) for inputting and outputting the clamp node. A pn junction is formed between the first clamp node and the first clamp node. For example, the second overvoltage control circuit may be formed by one or more diodes connected in series, each of which is coupled to the anode of the other diode by a cathode, and has a diode. The anode is coupled to the output clamp node, and the cathode of the diode is coupled to the first clamp node.
第三連接電路則耦接於一第一電源端與輸出入箝制節點之間,可由一二極體形成(陽極耦接於第一電源端,陰極耦接於輸出入箝制節點)。The third connecting circuit is coupled between a first power terminal and the input and output clamping node, and is formed by a diode (the anode is coupled to the first power terminal, and the cathode is coupled to the input and output clamp node).
在本發明的一實施例中,靜電放電箝制電路可包括有一靜電放電偵測電路與一放電電路。靜電放電偵測電路耦接於輸出入箝制節點與一第二電源端之間,用來偵測靜電放電是否發生,並根據偵測結果提供一觸發訊號。放電電路則耦接於靜電放電偵測電路、輸出入箝制節點與第二電源端之間,其可由一場氧化層元件(FOD,field oxide device,譬如說是一場氧化層電晶體)、一金氧半場效電晶體或一矽控整流元件(SCR,Silicon Control Rectifier)形成。當偵測結果反映靜電放電發生時,放電電路可被觸發導通而使靜電放電箝制電路運作於一觸發導通模式,並提供一電流路徑以將輸出入箝制節點導通至第二電源端。In an embodiment of the invention, the electrostatic discharge clamp circuit can include an electrostatic discharge detection circuit and a discharge circuit. The ESD detection circuit is coupled between the input and output clamp nodes and a second power supply terminal for detecting whether an electrostatic discharge occurs, and providing a trigger signal according to the detection result. The discharge circuit is coupled between the ESD detection circuit, the output clamp node and the second power terminal, and may be a field oxide device (FOD, field oxide device), a gold oxide A half field effect transistor or a SCR (Silicon Control Rectifier) is formed. When the detection result reflects the occurrence of electrostatic discharge, the discharge circuit can be triggered to conduct the electrostatic discharge clamp circuit in a trigger conduction mode, and provide a current path to conduct the output into the clamp node to the second power terminal.
相對地,由於放電電路的電路特性,即使當偵測結果未反映靜電放電,但若輸出入箝制節點與第二電源端間的電壓差大於一第一特徵電壓,放電電路還是會使靜電放電箝制電路運作於一逆向導通模式而將輸出入箝制節點導通至第二電源端;此第一特徵電壓可以是放電電路的崩潰電壓。然而,經由本發明上述的電路配置,當接墊承受一電子過壓時,第一過壓控制電路就可在第一箝制節點與輸出入箝制節點之間提供一第一跨壓,以使輸出入箝制節點的電壓小於第一特徵電壓,避免靜電放電箝制電路中的放電電路因電子過壓而導通(或是,等效地,使放電電路可在輸出入箝制節點與第二電源端間提供一極大的等效電阻)。這樣一來,靜電放電箝制電路/放電電路就不會因電子過壓而導通高電流,避免高電流破壞晶片的靜電放電保護機制。In contrast, due to the circuit characteristics of the discharge circuit, even if the detection result does not reflect the electrostatic discharge, if the voltage difference between the output clamp node and the second power terminal is greater than a first characteristic voltage, the discharge circuit still clamps the electrostatic discharge. The circuit operates in a reverse conduction mode to conduct the output into the clamp node to the second power supply terminal; the first characteristic voltage may be a breakdown voltage of the discharge circuit. However, with the above circuit configuration of the present invention, when the pad is subjected to an electronic overvoltage, the first overvoltage control circuit can provide a first voltage across the first clamp node and the output clamp node to make the output The voltage of the clamped node is less than the first characteristic voltage, so that the discharge circuit in the electrostatic discharge clamp circuit is prevented from being turned on by the electronic overvoltage (or, equivalently, the discharge circuit can be provided between the output clamp node and the second power supply terminal) A very large equivalent resistance). In this way, the ESD clamp circuit/discharge circuit does not conduct high current due to electronic overvoltage, and avoids high current damage to the electrostatic discharge protection mechanism of the wafer.
另一方面,前述的第一連接電路亦可運作於一順向導通模式與一逆向導通模式;當第一連接電路運作於順向導通模式時,第一連接電路可將接墊導通至第一箝制節點。當接墊上發生靜電放電時,第一連接電路就會運作於此順向導通模式,將接墊導通至第一箝制節點,並配合導通的靜電放電箝制電路來使靜電放電的電荷得以逸散。On the other hand, the first connecting circuit can also operate in a forward conduction mode and a reverse conduction mode; when the first connection circuit operates in the forward conduction mode, the first connection circuit can conduct the pad to the first Clamp the node. When an electrostatic discharge occurs on the pad, the first connection circuit operates in the forward conduction mode, and the pad is conducted to the first clamp node, and the electrostatic discharge clamp circuit is used to dissipate the electrostatic discharge charge.
相對地,因為第一連接電路的電路特性,當第一箝制節點與接墊間的電壓差大於一第二特徵電壓時,就會使第一連接電路運作於逆向導通模式而將第一箝制節點導通至接墊。因此,當第二電源端承受一電子過壓時,第二過壓控制電路便可在輸出入箝制節點與第一箝制節點間提供一第二跨壓,以使第一箝制節點與接墊間的電壓差小於第二特徵電壓,避免第一連接電路逆向導通電子過壓的大電流。In contrast, because of the circuit characteristics of the first connection circuit, when the voltage difference between the first clamp node and the pad is greater than a second characteristic voltage, the first connection circuit is operated in the reverse conduction mode and the first clamp node is Conduction to the pad. Therefore, when the second power terminal is subjected to an electronic overvoltage, the second overvoltage control circuit can provide a second voltage across the output clamp node and the first clamp node, so that the first clamp node and the pad are interposed. The voltage difference is less than the second characteristic voltage, and the first connecting circuit is prevented from reversely conducting a large current of the electronic overvoltage.
本發明靜電放電保護電路可選擇性另行設置一第二連接電路,耦接於接墊與第二電源端之間。當靜電放電發生於第二電源端與接墊之間時,第二連接電路可將第二電源端導通至接墊,以形成靜電放電的電流路徑,達到靜電放電保護的功能。The ESD protection circuit of the present invention can be selectively provided with a second connection circuit coupled between the pad and the second power terminal. When the electrostatic discharge occurs between the second power terminal and the pad, the second connecting circuit can conduct the second power terminal to the pad to form a current path of the electrostatic discharge to achieve the function of electrostatic discharge protection.
為進一步在電子過壓時保護晶片的內部電路,本發明可在接墊與待保護的內部電路之間設置一限流電路及一分壓電路。限流電路耦接於接墊與內部電路之間,其可為一第一電阻。分壓電路則耦接於限流電路與內部電路之間。當接墊承受電子過壓時,分壓電路可提供一第三跨壓至內部電路,此第三跨壓小於電子過壓之電壓,以保護內部電路不會因電子過壓的高電壓而被破壞。此分壓電路中可設有一第二電阻以及一n通道金氧半場效電晶體,此電晶體之閘極、源極與體極耦接於第二電源端,電晶體之汲極則耦接於第二電阻。In order to further protect the internal circuit of the wafer during electronic overvoltage, the present invention can provide a current limiting circuit and a voltage dividing circuit between the pad and the internal circuit to be protected. The current limiting circuit is coupled between the pad and the internal circuit, and may be a first resistor. The voltage dividing circuit is coupled between the current limiting circuit and the internal circuit. When the pad is subjected to electronic overvoltage, the voltage dividing circuit can provide a third voltage across the internal circuit, and the third voltage is less than the voltage of the electronic overvoltage to protect the internal circuit from the high voltage of the electronic overvoltage. destroyed. The voltage dividing circuit can be provided with a second resistor and an n-channel gold-oxygen half field effect transistor. The gate, the source and the body of the transistor are coupled to the second power terminal, and the drain of the transistor is coupled. Connected to the second resistor.
經由本發明所揭露的電路配置,本發明之靜電放電保護電路不僅具備應有的靜電放電保護功能,還能防護電子過壓,使靜電放電保護電路與晶片內部電路不會因電子過壓而被破壞。本發明亦可將靜電放電保護的設計考量與電子過壓防護的設計考量相互獨立,使電路設計/實施更為方便。譬如說,本發明可先依據靜電放電保護的需求先設計靜電放電箝制電路,再根據靜電放電箝制電路的特性(譬如前述的第一特徵電壓)與電子過壓防護的需求來設計第一過壓控制電路(譬如說,設計第一過壓控制電路所能提供的第一跨壓),以便在不影響靜電放電保護能力的前提下使本發明靜電放電保護電路能進一步兼顧電子過壓防護能力。Through the circuit configuration disclosed by the present invention, the electrostatic discharge protection circuit of the present invention not only has the electrostatic discharge protection function as it should, but also protects the electronic overvoltage, so that the electrostatic discharge protection circuit and the internal circuit of the chip are not damaged by the electronic overvoltage. damage. The invention can also separate the design considerations of the electrostatic discharge protection from the design considerations of the electronic overvoltage protection, and make the circuit design/implementation more convenient. For example, the present invention can first design an electrostatic discharge clamp circuit according to the requirements of electrostatic discharge protection, and then design a first overvoltage according to the characteristics of the electrostatic discharge clamp circuit (such as the first characteristic voltage mentioned above) and the requirement of electronic overvoltage protection. The control circuit (for example, designing the first voltage across the first overvoltage control circuit) is such that the electrostatic discharge protection circuit of the present invention can further take into account the electronic overvoltage protection capability without affecting the electrostatic discharge protection capability.
為了使 貴審查委員能更進一步瞭解本發明特徵及技術內容,請參閱以下有關本發明之詳細說明與附圖,然而所附圖式僅提供參考與說明,並非用來對本發明加以限制。The detailed description of the present invention and the accompanying drawings are to be understood by the accompanying claims
如前面討論過的,接墊Pd會因組裝加工測試過程中的不當處理而遭遇電子過壓事件。電子過壓的基本特性之一,就是持續較長時間的高電壓(可以是正或負的電壓)。這和靜電放電的電荷源本質大不相同,也因此,傳統的靜電放電保護電路會在遭受電子過壓時因長時間高電壓所持續導通的大電流而被破壞。As discussed earlier, the pads Pd encounter electronic overvoltage events due to improper handling during assembly processing. One of the basic characteristics of electronic overvoltage is the high voltage (which can be positive or negative) that lasts for a long time. This is intrinsically different from the charge source of the electrostatic discharge. Therefore, the conventional electrostatic discharge protection circuit is destroyed by a large current that is continuously turned on by a high voltage for a long time when subjected to an electronic overvoltage.
為了使靜電放電保護電路能具有電子過壓防護能力,本發明構思了新的靜電放電保護電路。請參考第1圖;第1圖示意的是本發明靜電放電保護電路一實施例20的電路架構。靜電放電保護電路20可實現於一晶片(晶粒、積體電路)的輸出入介面中;接墊Pd即用來使晶片的內部電路32可以和外界交換資料(譬如說是輸入/接收資料)。本發明靜電放電保護電路20中設有連接電路16、28及26(可分別視為第一、第二與第三連接電路)、過壓控制電路18(可視為第一過壓控制電路)及一靜電放電箝制電路22,並搭配一電源箝制電路(power clamp)24與一限流電路34。接墊Pd即是經由節點Nio與限流電路34而耦接至內部電路32。In order to enable the electrostatic discharge protection circuit to have electronic overvoltage protection capability, the present invention contemplates a new electrostatic discharge protection circuit. Please refer to FIG. 1; FIG. 1 is a circuit diagram showing a circuit structure of an embodiment 20 of the electrostatic discharge protection circuit of the present invention. The ESD protection circuit 20 can be implemented in an input/output interface of a chip (die, integrated circuit); the pad Pd is used to enable the internal circuit 32 of the chip to exchange data with the outside world (for example, input/receive data). . The electrostatic discharge protection circuit 20 of the present invention is provided with connection circuits 16, 28 and 26 (which can be regarded as first, second and third connection circuits, respectively), and an overvoltage control circuit 18 (which can be regarded as a first overvoltage control circuit) and An electrostatic discharge clamp circuit 22 is coupled to a power clamp 24 and a current limiting circuit 34. The pad Pd is coupled to the internal circuit 32 via the node Nio and the current limiting circuit 34.
靜電放電保護電路20可由兩個電源端VCC與GND連接工作電壓(電源端VCC與GND可分別視為第一與第二電源端)。連接電路16經由節點Nio而耦接於接墊Pd與節點CLMP1(此節點可視為一第一箝制節點)之間,過壓控制電路18耦接於節點CLMP1與另一節點IO_CLMP(可視為一輸出入箝制節點)之間,靜電放電箝制電路22則耦接於節點IO_CLMP與電源端GND之間。節點IO_CLMP經由連接電路26耦接至電源端VCC,而電源箝制電路24則耦接於電源端VCC與GND之間。另一連接電路28則耦接於節點Nio(接墊Pd)與電源端GND之間。The ESD protection circuit 20 can be connected to the working voltage by the two power terminals VCC and GND (the power terminals VCC and GND can be regarded as the first and second power terminals, respectively). The connection circuit 16 is coupled between the pad Pd and the node CLMP1 (this node can be regarded as a first clamp node) via the node Nio, and the overvoltage control circuit 18 is coupled to the node CLMP1 and another node IO_CLMP (which can be regarded as an output). The electrostatic discharge clamp circuit 22 is coupled between the node IO_CLMP and the power supply terminal GND. The node IO_CLMP is coupled to the power supply terminal VCC via the connection circuit 26, and the power supply clamp circuit 24 is coupled between the power supply terminals VCC and GND. The other connection circuit 28 is coupled between the node Nio (the pad Pd) and the power supply terminal GND.
在第1圖的實施例中,連接電路16可用一二極體Da(1)實現,其陽極與陰極分別耦接於節點Nio(接墊Pd)與節點CLMP1。連接電路28則可用另一二極體Da(2)實現。連接電路26也可以利用一二極體Da(3)實現。過壓控制電路18則可用一或多個串連的二極體Da(4)至Da(N)實現(其中N為一定值整數)。二極體Da(1)、Da(2)與Da(3)可以是相同或不同的二極體,二極體Da(4)至Da(N)可以是相同或不同的二極體,各二極體Da(4)至Da(N)也可以和二極體Da(1)至Da(3)相異或相同。限流電路34可用一電阻R1實現。電源箝制電路24則可以箝制電源端VCC與GND間的電壓。In the embodiment of FIG. 1, the connection circuit 16 can be implemented by a diode Da(1), and the anode and the cathode are respectively coupled to the node Nio (the pad Pd) and the node CLMP1. The connection circuit 28 can be implemented with another diode Da(2). The connection circuit 26 can also be implemented using a diode Da(3). The overvoltage control circuit 18 can be implemented with one or more series connected diodes Da(4) through Da(N) (where N is a certain integer). The diodes Da(1), Da(2) and Da(3) may be the same or different diodes, and the diodes Da(4) to Da(N) may be the same or different diodes, each The diodes Da(4) to Da(N) may also be different or identical to the diodes Da(1) to Da(3). The current limiting circuit 34 can be implemented with a resistor R1. The power clamp circuit 24 can clamp the voltage between the power supply terminals VCC and GND.
靜電放電保護電路20進行靜電放電保護的情形可描述如下。當靜電放電發生在接墊Pd與電源端GND間而使接墊Pd與電源端GND間呈現正電壓差時,連接電路16會順向導通而將接墊Pd導通至節點CLMP1,而過壓控制電路18亦會順向導通而將節點CLMP1導通至節點IO_CLMP,使接墊Pd上的靜電放電事件可反映至節點IO_CLMP。當靜電放電箝制電路22由節點IO_CLMP上偵測到靜電放電時,靜電放電箝制電路22可運作於一觸發導通模式而將節點IO_CLMP導通至電源端GND。這樣一來,就能在接墊Pd至電源端GND導通一電流路徑,使靜電放電的電荷可經由此路徑逸散,保護內部電路32不受傷害。限流電路34提供的電阻阻抗可協助防止靜電放電的電流流入至內部電路32。The case where the electrostatic discharge protection circuit 20 performs electrostatic discharge protection can be described as follows. When the electrostatic discharge occurs between the pad Pd and the power supply terminal GND to cause a positive voltage difference between the pad Pd and the power supply terminal GND, the connection circuit 16 will conduct the connection Pd to the node CLMP1, and the overvoltage control The circuit 18 also conducts the node CLMP1 to the node IO_CLMP, so that the electrostatic discharge event on the pad Pd can be reflected to the node IO_CLMP. When the electrostatic discharge clamp circuit 22 detects an electrostatic discharge from the node IO_CLMP, the electrostatic discharge clamp circuit 22 can operate in a trigger conduction mode to conduct the node IO_CLMP to the power supply terminal GND. In this way, a current path can be turned on from the pad Pd to the power supply terminal GND, so that the electrostatic discharge charge can escape through the path, and the internal circuit 32 is protected from damage. The resistive impedance provided by the current limiting circuit 34 assists in preventing current from electrostatic discharge from flowing into the internal circuit 32.
另一方面,若電源端GND與接墊Pd間發生靜電放電而使兩者間呈現正電壓差時,連接電路28會順向導通,在電源端GND與接墊Pd間形成電流路徑,達到靜電放電保護的目的。On the other hand, if an electrostatic discharge occurs between the power supply terminal GND and the pad Pd to cause a positive voltage difference therebetween, the connection circuit 28 is turned on, and a current path is formed between the power supply terminal GND and the pad Pd to achieve static electricity. The purpose of discharge protection.
由於靜電放電事件常會在極短時間內累積極高的電壓,故靜電放電箝制電路22的設計就是使其能在偵測到快速累積的高電壓時快速地被觸發導通。相對地,由於靜電放電箝制電路22的電路特性,即使當偵測結果未反映靜電放電,但若節點IO_CLMP與電源端GND間的電壓差大於一第一特徵電壓,靜電放電箝制電路22還是可能會運作於一逆向導通模式而將節點IO_CLMP導通至電源端GND;譬如說,此第一特徵電壓可以是靜電放電箝制電路22的崩潰電壓,其可使靜電放電箝制電路22在節點IO_CLMP與電源端GND之間崩潰導通。此種特性將不利於電子過壓的防護:因為,當電子過壓的電壓過高時,有可能使靜電放電箝制電路22導通;隨電子過壓持續,持續導通的大電流就會傷害或破壞靜電放電箝制電路22。Since an electrostatic discharge event often accumulates extremely high voltages in a very short time, the electrostatic discharge clamp circuit 22 is designed to be quickly turned on when a rapidly accumulating high voltage is detected. In contrast, due to the circuit characteristics of the electrostatic discharge clamp circuit 22, even if the detection result does not reflect the electrostatic discharge, if the voltage difference between the node IO_CLMP and the power supply terminal GND is greater than a first characteristic voltage, the electrostatic discharge clamp circuit 22 may still Operating in a reverse conduction mode, the node IO_CLMP is turned on to the power supply terminal GND; for example, the first characteristic voltage may be a breakdown voltage of the electrostatic discharge clamp circuit 22, which may cause the electrostatic discharge clamp circuit 22 to be at the node IO_CLMP and the power supply terminal GND. The crash between turns on. This kind of characteristic will be detrimental to the protection of electronic overvoltage: because when the voltage of the electronic overvoltage is too high, it is possible to make the electrostatic discharge clamp circuit 22 conduct; as the electronic overvoltage continues, the large current that continues to conduct will damage or destroy. Electrostatic discharge clamp circuit 22.
然而,經由本發明上述的電路配置,當接墊Pd與電源端GND間承受一正向電子過壓時,過壓控制電路18就可在節點CLMP1與節點IO_CLMP之間提供一第一跨壓,以使節點IO_CLMP的電壓小於第一特徵電壓,避免靜電放電箝制電路22因電子過壓而導通(或是,等效地,使靜電放電箝制電路可在節點IO_CLMP與電源端GND間提供一極大的等效電阻)。這樣一來,靜電放電箝制電路22就不會因電子過壓而導通大電流,避免長時間持續的高電流破壞晶片的靜電放電保護機制,達到電子過壓防護的目的。However, with the above circuit configuration of the present invention, when a positive electronic overvoltage is applied between the pad Pd and the power supply terminal GND, the overvoltage control circuit 18 can provide a first voltage across the node CLMP1 and the node IO_CLMP. In order to make the voltage of the node IO_CLMP smaller than the first characteristic voltage, the electrostatic discharge clamp circuit 22 is prevented from being turned on by the electronic overvoltage (or, equivalently, the electrostatic discharge clamp circuit can provide a great connection between the node IO_CLMP and the power supply terminal GND. Equivalent resistance). In this way, the electrostatic discharge clamp circuit 22 does not conduct a large current due to the electronic overvoltage, and avoids the long-lasting high current to destroy the electrostatic discharge protection mechanism of the wafer, thereby achieving the purpose of electronic overvoltage protection.
請參考第2圖。第2圖為本發明靜電放電保護電路又一實施例30的示意圖。類似於第1圖的實施例,第2圖中的靜電放電保護電路30中設置有一連接電路36(可視為第一連接電路,耦接於節點Nio(接墊Pd)與節點CLMP1間)及一靜電放電箝制電路22(耦接於節點IO_CLMP與電源端GND間),亦在接墊Pd與內部電路32間設置一限流電路34,並搭配連接電路42(即第三連接電路,耦接於節點IO_CLMP與電源端VCC間,可用一二極體D(1)實現)與電源箝制電路24(耦接於電源端VCC與GND之間)。Please refer to Figure 2. Fig. 2 is a schematic view showing still another embodiment 30 of the electrostatic discharge protection circuit of the present invention. Similar to the embodiment of FIG. 1, the ESD protection circuit 30 of FIG. 2 is provided with a connection circuit 36 (which can be regarded as a first connection circuit coupled between the node Nio (the pad Pd) and the node CLMP1) and a The ESD clamp circuit 22 (coupled between the node IO_CLMP and the power supply terminal GND) is also provided with a current limiting circuit 34 between the pad Pd and the internal circuit 32, and is coupled with the connection circuit 42 (ie, the third connection circuit is coupled to Between the node IO_CLMP and the power supply terminal VCC, a diode D (1) can be used) and the power supply clamping circuit 24 (coupled between the power supply terminals VCC and GND).
與第1圖實施例較為不同的是,靜電放電保護電路30在節點CLMP1與IO_CLMP間設有兩個過壓控制電路38A與38B(可分別視為第一及第二過壓控制電路),並取消了節點Nio(接墊Pd)與電源端GND間的連接電路。在第2圖的實施例中,過壓控制電路38A可由一或多個串連的二極體D(N+1)至D(N+M)實現(其中N與M為整數定值),各串連二極體間以陰極耦接至另一二極體之陽極,二極體D(N+1)之陽極耦接於節點CLMP1、二極體D(N+M)之陰極耦接於節點IO_CLMP。過壓控制電路38B可由一或多個相互串連的二極體D(2)至D(N)形成,各串連二極體間以陰極耦接至另一二極體之陽極,二極體D(N)之陽極耦接於節點IO_CLMP、二極體D(2)之陰極耦接於節點CLMP1。二極體D(2)至D(N)可以是相同或不同特性的二極體,二極體D(N+1)至D(N+M)可以是相同或不同的二極體,二極體D(1)與D(2)至D(N)、D(N+1)至D(N+M)亦可以是相同或不同的二極體。The difference from the embodiment of FIG. 1 is that the ESD protection circuit 30 is provided with two overvoltage control circuits 38A and 38B between the nodes CLMP1 and IO_CLMP (which can be regarded as the first and second overvoltage control circuits, respectively), and The connection circuit between the node Nio (pad Pd) and the power supply terminal GND is cancelled. In the embodiment of FIG. 2, the overvoltage control circuit 38A can be implemented by one or more series connected diodes D(N+1) through D(N+M) (where N and M are integer values), The tandem diodes are coupled to the anode of the other diode, and the anode of the diode D(N+1) is coupled to the cathode of the node CLMP1 and the diode D (N+M). IO_CLMP. The overvoltage control circuit 38B may be formed by one or more diodes D(2) to D(N) connected in series with each other, and the cathodes of the series connected diodes are coupled to the anode of the other diode, the second pole The anode of the body D(N) is coupled to the node IO_CLMP, and the cathode of the diode D(2) is coupled to the node CLMP1. The diodes D(2) to D(N) may be diodes of the same or different characteristics, and the diodes D(N+1) to D(N+M) may be the same or different diodes, The polar bodies D(1) and D(2) to D(N), D(N+1) to D(N+M) may also be the same or different diodes.
另一方面,在第2圖的實施例中,節點Nio(接墊Pd)與節點CLMP1間的連接電路36係以一p通道金氧半場效電晶體P1實現;電晶體P1之閘極、源極與體極耦接於節點CLMP1,而汲極則經由節點Nio耦接於接墊Pd。連接電路36可運作於順向導通模式而將接墊Pd導通至節點CLMP1,而當節點CLMP1與接墊Pd間的正電壓差超過一第二特徵電壓時,連接電路36也可運作於一逆向導通模式而將節點CLMP1導通至接墊Pd。譬如說,第二特徵電壓可以是電晶體P1崩潰導通時的崩潰電壓。On the other hand, in the embodiment of FIG. 2, the connection circuit 36 between the node Nio (the pad Pd) and the node CLMP1 is realized by a p-channel MOS field-effect transistor P1; the gate and source of the transistor P1. The pole and the body are coupled to the node CLMP1, and the drain is coupled to the pad Pd via the node Nio. The connection circuit 36 can operate in the forward conduction mode to conduct the pad Pd to the node CLMP1, and when the positive voltage difference between the node CLMP1 and the pad Pd exceeds a second characteristic voltage, the connection circuit 36 can also operate in a reverse direction. The conduction mode turns on the node CLMP1 to the pad Pd. For example, the second characteristic voltage may be a breakdown voltage when the transistor P1 is turned on.
靜電放電保護電路30進行靜電放電保護的情形可描述如下。當靜電放電發生在接墊Pd與電源端GND間而使接墊Pd與電源端GND間呈現正電壓差時,連接電路36與過壓控制電路38A會順向導通而將節點CLMP1導通至節點IO_CLMP,使接墊Pd上的靜電放電事件可反映至節點IO_CLMP。當靜電放電箝制電路22從節點IO_CLMP上偵測到靜電放電時,靜電放電箝制電路22就可運作於一觸發導通模式而將節點IO_CLMP導通至電源端GND,以便在接墊Pd至電源端GND導通一電流路徑。The case where the electrostatic discharge protection circuit 30 performs electrostatic discharge protection can be described as follows. When the electrostatic discharge occurs between the pad Pd and the power supply terminal GND to cause a positive voltage difference between the pad Pd and the power supply terminal GND, the connection circuit 36 and the overvoltage control circuit 38A will conduct the node CLMP1 to the node IO_CLMP. So that the electrostatic discharge event on the pad Pd can be reflected to the node IO_CLMP. When the electrostatic discharge clamp circuit 22 detects the electrostatic discharge from the node IO_CLMP, the electrostatic discharge clamp circuit 22 can operate in a trigger conduction mode to conduct the node IO_CLMP to the power supply terminal GND to be turned on at the pad Pd to the power supply terminal GND. A current path.
相對地,若電源端GND與接墊Pd間發生靜電放電而使兩者間呈現正電壓差時,靜電放電箝制電路22可等效於一個陽極耦接於電源端GND而陰極耦接於節點IO_CLMP的二極體,將電源端GND順向導通至節點IO_CLMP,而過壓控制電路38B亦會順向導通至節點CLMP_1。連接電路36中以二極體形式連接的電晶體P1可崩潰導通,將節點CLMP_1導通至接墊Pd,在電源端GND與接墊Pd間形成電流路徑,達到靜電放電保護的目的。由於靜電放電持續的時間極短,即使電晶體P1是崩潰導通,也不會傷害電晶體P1。在連接電路36中採用p通道金氧半場效電晶體,其實也是利用其寄生的p-n-p雙載子接面電晶體,以增進電源端GND至接墊Pd間的靜電放電保護能力。In contrast, if an electrostatic discharge occurs between the power supply terminal GND and the pad Pd to cause a positive voltage difference therebetween, the electrostatic discharge clamp circuit 22 can be equivalent to an anode coupled to the power supply terminal GND and the cathode coupled to the node IO_CLMP. The diode is connected to the node IO_CLMP by the power supply terminal GND, and the overvoltage control circuit 38B is also passed to the node CLMP_1. The transistor P1 connected in the form of a diode in the connection circuit 36 can be turned on, and the node CLMP_1 is turned on to the pad Pd, and a current path is formed between the power supply terminal GND and the pad Pd to achieve the purpose of electrostatic discharge protection. Since the electrostatic discharge lasts for a very short time, the transistor P1 is not damaged even if the transistor P1 is turned on and off. The p-channel gold-oxygen half-field effect transistor is used in the connection circuit 36, and the parasitic p-n-p double-carrier junction transistor is also used to improve the electrostatic discharge protection capability between the power supply terminal GND and the pad Pd.
至於靜電放電保護電路30進行電子過壓防護的情形則可描述如下。當接墊Pd與電源端GND間發生正向電子過壓而使兩者間有持續長時間的正電壓差時,連接電路36與過壓控制電路38A可能順向導通,若靜電放電箝制電路22因節點IO_CLMP反映接墊Pd的高電壓而逆向導通,連接電路36、過壓控制電路38A與靜電放電箝制電路22就會形成電流路徑而導通破壞性的大電流。然而,在本發明的配置下,過壓控制電路38A其實會在節點CLMP1與節點IO_CLMP之間提供一足夠大的第一跨壓,使節點IO_CLMP的電壓小於靜電放電箝制電路22的第一特徵電壓,避免靜電放電箝制電路22因電子過壓而導通,達到電子過壓防護的目的。As for the case where the electrostatic discharge protection circuit 30 performs electronic overvoltage protection, it can be described as follows. When a positive electronic overvoltage occurs between the pad Pd and the power supply terminal GND to cause a positive voltage difference between the two for a long time, the connection circuit 36 and the overvoltage control circuit 38A may be turned on, if the electrostatic discharge clamp circuit 22 Since the node IO_CLMP reflects the high voltage of the pad Pd and reversely conducts, the connection circuit 36, the overvoltage control circuit 38A, and the electrostatic discharge clamp circuit 22 form a current path to conduct a destructive large current. However, in the configuration of the present invention, the overvoltage control circuit 38A actually provides a sufficiently large first voltage across the node CLMP1 and the node IO_CLMP such that the voltage of the node IO_CLMP is less than the first characteristic voltage of the electrostatic discharge clamp circuit 22. The electrostatic discharge clamp circuit 22 is prevented from being turned on due to electronic overvoltage, and the purpose of electronic overvoltage protection is achieved.
另一方面,若接墊Pd與電源端GND間發生負向電子過壓而使電源端GND與接墊Pd間有持續長時間的正電壓差時,靜電放電箝制電路22與過壓控制電路38B可能順向將電源端GND導通至節點CLMP1,若節點CLMP1與接墊間Pd的電壓差超過連接電路36的第二特徵電壓,連接電路36就會逆向導通,在電源端GND與接墊Pd間導通電流路徑。不過,經由適當的電路設計,在上述電子過壓發生時,過壓控制電路38B其實會在節點IO_CLMP與節點CLMP1之間提供一足夠大的第二跨壓,使節點CLMP1至接墊Pd間的電壓差不會大於第二特徵電壓,防止連接電路36逆向導通。如此一來,就可避免負向電子過壓導通的大電流損壞靜電放電保護電路30。On the other hand, if a negative electron overvoltage occurs between the pad Pd and the power supply terminal GND, and there is a positive voltage difference between the power supply terminal GND and the pad Pd for a long time, the electrostatic discharge clamp circuit 22 and the overvoltage control circuit 38B The power supply terminal GND may be turned on to the node CLMP1 in the forward direction. If the voltage difference between the node CLMP1 and the pad Pd exceeds the second characteristic voltage of the connection circuit 36, the connection circuit 36 is reversely turned on, between the power supply terminal GND and the pad Pd. Turn on the current path. However, through proper circuit design, when the above electronic overvoltage occurs, the overvoltage control circuit 38B actually provides a sufficiently large second voltage across the node IO_CLMP and the node CLMP1, so that the node CLMP1 is connected to the pad Pd. The voltage difference is not greater than the second characteristic voltage, preventing the connection circuit 36 from being reversed. In this way, it is possible to prevent the large current flowing through the negative electron overvoltage from damaging the electrostatic discharge protection circuit 30.
由以上描述可知,本發明可利用系統化的電路設計來使靜電放電保護電路30能兼具電子過壓防護能力。譬如說,本發明可先依據靜電放電的需求設計靜電放電箝制電路22與連接電路36。依據設計,便可得知靜電放電箝制電路22的第一特徵電壓與連接電路36的第二特徵電壓。根據第一特徵電壓、第二特徵電壓與電子過壓防護的需求,便可決定各過壓控制電路38A與38B的電路配置。譬如說,若二極體D(N+1)至D(N+M)中的每一個二極體可在其陽極至陰極間提供跨壓Vpn,正向電子過壓的電壓最高會達到電壓OV+,而第一特徵電壓為Vc1,那麼,只要過壓控制電路38A中的二極體數量M足夠大而使M*Vpn>((OV+)-Vc1),靜電放電保護電路30就能有足夠的正向電子過壓防護能力,能夠在正向電子過壓發生時防止電流路徑導通。As can be seen from the above description, the present invention can utilize a systematic circuit design to enable the ESD protection circuit 30 to have both electronic overvoltage protection capabilities. For example, the present invention can first design the electrostatic discharge clamp circuit 22 and the connection circuit 36 in accordance with the requirements of electrostatic discharge. According to the design, the first characteristic voltage of the electrostatic discharge clamp circuit 22 and the second characteristic voltage of the connection circuit 36 can be known. The circuit configuration of each of the overvoltage control circuits 38A and 38B can be determined based on the requirements of the first characteristic voltage, the second characteristic voltage, and electronic overvoltage protection. For example, if each of the diodes D(N+1) to D(N+M) can provide a voltage across the anode VNP, the voltage of the forward electron overvoltage will reach the voltage. OV+, and the first characteristic voltage is Vc1, then the electrostatic discharge protection circuit 30 can be sufficient as long as the number M of diodes in the overvoltage control circuit 38A is sufficiently large to make M*Vpn>((OV+)-Vc1) The forward electronic overvoltage protection capability prevents the current path from turning on when a positive electronic overvoltage occurs.
同理,若負向電子過壓的電壓極值為|OV-|,連接電路38B中的每一個二極體可在其陽極至陰極間提供跨壓Vpn,且連接電路36的第二特徵電壓為Vc2,那麼,只要過壓控制電路38B中的二極體數量(N-1)足夠多而使(N-1)*Vpn>(|OV-|-Vc2),靜電放電保護電路30就能有足夠負向電子過壓防護能力,能夠在負向電子過壓發生時防止電流路徑導通。Similarly, if the voltage extreme value of the negative electron overvoltage is |OV-|, each of the diodes in the connection circuit 38B can provide the voltage across the Vpn between the anode and the cathode, and the second characteristic voltage of the connection circuit 36. For Vc2, then, as long as the number of diodes (N-1) in the overvoltage control circuit 38B is sufficiently large to make (N-1)*Vpn>(|OV-|-Vc2), the electrostatic discharge protection circuit 30 can There is sufficient negative electronic overvoltage protection to prevent current path conduction when negative electron overvoltage occurs.
延續第2圖的實施例,請參考第3圖;第3圖示意的是本發明靜電放電保護電路又一實施例40的電路架構。基本上,靜電放電保護電路40與第2圖之靜電放電保護電路30的電路型態與工作原理十分相似;主要差別之一,是靜電放電保護電路40改採一p-n-p雙載子接面電晶體B1來實現節點CLMP1與節點Nio(接墊Pd)間的連接電路46。電晶體B1的射極與基極耦接於節點CLMP1,集極耦接於接墊Pd。若靜電放電保護電路40形成在一個基底(substrate)較厚、可容許較深摻雜井或摻雜區的半導體結構中,就可利用垂直的n型井來形成垂直結構的p-n-p雙載子接面電晶體B1。若靜電放電保護電路40所在的半導體結構中較難實現垂直n型井,則可用側向(literal)結構來實現此電晶體B1。另外,也可用場氧化層(field oxide)電晶體來實現電晶體B1。類似於第2圖中的電路運作原理,第3圖中的連接電路46也有一個逆向導通的第二特徵電壓;根據電子過壓防護需求與連接電路46的第二特徵電壓,便可決定連接電路的電路。原則上,在第1圖至第3圖的實施例中,各連接電路16、36及46都可在節點Nio(接墊Pd)至節點CLMP1之間提供一p-n接面,而這些連接電路的第二特徵電壓就可以是此p-n接面的崩潰電壓。Referring to the embodiment of Fig. 2, please refer to Fig. 3; Fig. 3 is a circuit diagram showing still another embodiment 40 of the electrostatic discharge protection circuit of the present invention. Basically, the circuit type and working principle of the electrostatic discharge protection circuit 40 and the electrostatic discharge protection circuit 30 of FIG. 2 are very similar; one of the main differences is that the electrostatic discharge protection circuit 40 adopts a pnp double carrier junction transistor. B1 is used to implement a connection circuit 46 between the node CLMP1 and the node Nio (pad Pd). The emitter and the base of the transistor B1 are coupled to the node CLMP1, and the collector is coupled to the pad Pd. If the ESD protection circuit 40 is formed in a semiconductor structure having a thick substrate that can tolerate deeper doped wells or doped regions, a vertical n-type well can be used to form a vertical structure of the pnp bipolar sub-connection. Surface transistor B1. If the vertical n-well is difficult to implement in the semiconductor structure in which the ESD protection circuit 40 is located, the transistor B1 can be implemented with a lateral structure. Alternatively, the field oxide B1 can be realized by a field oxide transistor. Similar to the circuit operation principle in FIG. 2, the connection circuit 46 in FIG. 3 also has a second characteristic voltage that is reverse-conducted; the connection circuit can be determined according to the electronic overvoltage protection requirement and the second characteristic voltage of the connection circuit 46. Circuit. In principle, in the embodiments of FIGS. 1 to 3, each of the connection circuits 16, 36 and 46 can provide a pn junction between the node Nio (pad Pd) and the node CLMP1, and these connection circuits The second characteristic voltage can be the breakdown voltage of the pn junction.
延續第1圖至第3圖的實施例,請參考第4圖與第5圖;本發明中的靜電放電箝制電路22可用第4圖或第5圖中的實施例來實現。在第4圖的實施例中,靜電放電箝制電路22中包括有一靜電放電偵測電路52與一放電電路54。靜電放電偵測電路52耦接於節點IO_CLMP與電源端GND之間,用來偵測靜電放電是否發生,並根據偵測結果提供一觸發訊號Str。放電電路54,同樣耦接於節點IO_CLMP與電源端GND之間,並於一觸發端TR耦接於靜電放電偵測電路52,以接收觸發訊號Str。當靜電放電事件發生而使節點IO_CLMP的電壓快速升高時,靜電放電偵測電路52的偵測結果會反映靜電放電發生,並利用觸發訊號Str觸發放電電路54導通,而放電電路54就可使靜電放電箝制電路22運作於觸發導通模式,將節點IO_CLMP導通至電源端GND,形成靜電放電的電流路徑。Continuing with the embodiments of Figs. 1 to 3, please refer to Figs. 4 and 5; the electrostatic discharge clamp circuit 22 of the present invention can be realized by the embodiment of Fig. 4 or Fig. 5. In the embodiment of FIG. 4, the electrostatic discharge clamp circuit 22 includes an electrostatic discharge detecting circuit 52 and a discharge circuit 54. The ESD detection circuit 52 is coupled between the node IO_CLMP and the power supply terminal GND to detect whether an electrostatic discharge occurs, and provides a trigger signal Str according to the detection result. The discharge circuit 54 is also coupled between the node IO_CLMP and the power supply terminal GND, and is coupled to the electrostatic discharge detection circuit 52 at a trigger terminal TR to receive the trigger signal Str. When the electrostatic discharge event occurs and the voltage of the node IO_CLMP rises rapidly, the detection result of the electrostatic discharge detecting circuit 52 reflects the occurrence of the electrostatic discharge, and the trigger circuit Str is used to trigger the discharge circuit 54 to be turned on, and the discharge circuit 54 can The electrostatic discharge clamp circuit 22 operates in a trigger conduction mode, and turns on the node IO_CLMP to the power supply terminal GND to form a current path of the electrostatic discharge.
相對地,當靜電放電偵測電路52並未觸發放電電路54時,放電電路54可大致等效成一個陽極在電源端GND而陰極在節點IO_CLMP的二極體。當電源端GND之電壓高於節點IO_CLMP達一定程度時,放電電路54可將電源端GND順向導通至節點IO_CLMP。而當節點IO_CLMP之電壓高於電源端GND之電壓而使兩者間的電壓差超過放電電路54的特徵電壓時,放電電路54則可逆向導通,將節點IO_CLMP導通至電源端GND。其中,使放電電路54逆向導通的特徵電壓就可用來代表靜電放電箝制電路22的第一特徵電壓;譬如說,此特徵電壓可以是使放電電路54崩潰導通的崩潰電壓。In contrast, when the electrostatic discharge detecting circuit 52 does not trigger the discharging circuit 54, the discharging circuit 54 can be roughly equivalent to a diode having a cathode at the power supply terminal GND and a cathode at the node IO_CLMP. When the voltage of the power supply terminal GND is higher than the node IO_CLMP to a certain extent, the discharge circuit 54 can pass the power supply terminal GND to the node IO_CLMP. When the voltage of the node IO_CLMP is higher than the voltage of the power supply terminal GND such that the voltage difference between the two exceeds the characteristic voltage of the discharge circuit 54, the discharge circuit 54 can be reversely turned on to turn on the node IO_CLMP to the power supply terminal GND. The characteristic voltage that causes the discharge circuit 54 to reversely conduct can be used to represent the first characteristic voltage of the electrostatic discharge clamp circuit 22; for example, the characteristic voltage can be a breakdown voltage that causes the discharge circuit 54 to collapse.
在本發明的一實施例中,放電電路54可由一場氧化層元件(FOD,field oxide device,譬如說是一場氧化層電晶體)、一金氧半場效電晶體或一矽控整流元件(SCR,Silicon Control Rectifier)實現,而靜電放電偵測電路52則可用基底觸發的方式來傳送觸發訊號Str,也就是利用基底觸發來觸發放電電路54。In an embodiment of the invention, the discharge circuit 54 may be a field oxide device (FOD), a metal oxide half-effect transistor, or a controlled rectifier device (SCR, Silicon Control Rectifier 52 is implemented, and the ESD detection circuit 52 can transmit the trigger signal Str by means of a substrate trigger, that is, the substrate trigger is used to trigger the discharge circuit 54.
在第5圖的實施例中,靜電放電箝制電路22的架構中同樣包括一靜電放電偵測電路62及一放電電路64。靜電放電偵測電路62中設有一個p通道金氧半場效電晶體Pa1、兩個n通道金氧半場效電晶體Na1與Na3,以及一電阻Ra。電晶體Na3用來當作電容,與電阻Ra耦接於節點TRi,以在節點IO_CLMP與電源端GND之間形成一電阻-電容電路(RC circuit)。電晶體Pa1與Na1則形成一反相器,將節點TRi的訊號反相為觸發端TR的觸發訊號Str。放電電路64則可用一n通道金氧半場效電晶體Na2來實現。In the embodiment of FIG. 5, the electrostatic discharge clamp circuit 22 also includes an electrostatic discharge detection circuit 62 and a discharge circuit 64. The ESD detecting circuit 62 is provided with a p-channel MOS field effect transistor Pa1, two n-channel MOS field-effect transistors Na1 and Na3, and a resistor Ra. The transistor Na3 is used as a capacitor, and is coupled to the resistor Ra at the node TRi to form a resistor-capacitor circuit (RC circuit) between the node IO_CLMP and the power supply terminal GND. The transistors Pa1 and Na1 form an inverter, which inverts the signal of the node TRi to the trigger signal Str of the trigger terminal TR. The discharge circuit 64 can be implemented by an n-channel gold oxide half field effect transistor Na2.
當靜電放電事件發生而在節點IO_CLMP上建立快速升高的電壓時,由於節點TRi上的電容無法馬上充電,故節點TRi上的電壓無法追隨節點IO_CLMP上的電壓,使節點TRi上的電壓相對為一低電壓;連帶地,觸發訊號Str就會在觸發端TR上以高電壓(趨近節點IO_CLMP之電壓)來觸發放電電路64導通,在節點IO_CLMP與電源端GND間形成一個可供靜電放電的電流路徑。When an electrostatic discharge event occurs and a rapidly rising voltage is established on the node IO_CLMP, since the capacitance on the node TRi cannot be charged immediately, the voltage on the node TRi cannot follow the voltage on the node IO_CLMP, so that the voltage on the node TRi is relatively A low voltage; in conjunction, the trigger signal Str triggers the discharge circuit 64 to be turned on at the trigger terminal TR with a high voltage (a voltage approaching the node IO_CLMP), and an electrostatic discharge is formed between the node IO_CLMP and the power supply terminal GND. Current path.
相對地,當節點IO_CLMP的電壓只是緩慢上升(如電源開啟時)或已經維持穩態電壓(譬如說電源已經穩定為額定工作電壓,或是在經歷持續的電子過壓時)時,靜電放電偵測電路62中的電阻-電容電路有足夠的時間來將電容充電,使節點TRi的電壓趨近節點IO_CLMP的電壓,連帶使觸發端TR維持於低電壓(趨近電源端GND之電壓),不會觸發放電電路64。不過,類似於第4圖中的放電電路54,在未觸發的情形下,放電電路64還是可能順向導通或是逆向導通;而使放電電路64逆向導通(由節點IO_CLMP導通至電源端GND)的特徵電壓就可以代表靜電放電箝制電路22的第一特徵電壓。如前面在第2圖時已經詳細討論過的,只要根據第一特徵電壓與電子過壓需求適當地設計過壓控制電路18(第1圖)與38A(第2圖/第3圖),就可防止放電電路64在經歷正向電子過壓時導通大電流,兼顧靜電放電保護與電子過壓防護功能。In contrast, when the voltage of the node IO_CLMP only rises slowly (such as when the power is turned on) or the steady-state voltage has been maintained (for example, when the power supply has stabilized to the rated operating voltage, or when continuous electronic overvoltage is experienced), the electrostatic discharge detection The resistor-capacitor circuit in the measuring circuit 62 has enough time to charge the capacitor, so that the voltage of the node TRi approaches the voltage of the node IO_CLMP, and the trigger terminal TR is maintained at a low voltage (the voltage approaching the power supply terminal GND), The discharge circuit 64 is triggered. However, similar to the discharge circuit 54 in FIG. 4, in the case of no triggering, the discharge circuit 64 may still be forward-passed or reverse-conducted; and the discharge circuit 64 may be reverse-conducted (conducted from the node IO_CLMP to the power supply terminal GND) The characteristic voltage can represent the first characteristic voltage of the electrostatic discharge clamp circuit 22. As has been discussed in detail in FIG. 2, as long as the overvoltage control circuits 18 (Fig. 1) and 38A (Fig. 2/3) are appropriately designed according to the first characteristic voltage and the electronic overvoltage requirement, The discharge circuit 64 can be prevented from conducting a large current when subjected to a positive electronic overvoltage, taking into account the electrostatic discharge protection and the electronic overvoltage protection function.
請參考第6圖,其所示意的是本發明靜電放電保護電路的又一實施例60;此實施例主要用來示意本發明精神如何實現於一個具有多輸出入接墊之輸出入介面。在此實施例中,靜電放電保護電路60會為每一個接墊Pd(1)至Pd(I)分別設置一對應的連接電路Ka(1)至Ka(I)與一對應的限流電路Kb(1)至Kb(I),I可為定值整數。其中,第i個(i=1,...,I)接墊Pd(i)經由對應的限流電路Kb(i)(其可由電阻R(i)實現)耦接至內部電路32,使內部電路32可經由這些接墊來與外界交換資料訊號。Please refer to Fig. 6, which is a further embodiment 60 of the electrostatic discharge protection circuit of the present invention; this embodiment is mainly used to illustrate how the spirit of the present invention can be realized in an input/output interface having multiple input and output pads. In this embodiment, the ESD protection circuit 60 respectively provides a corresponding connection circuit Ka(1) to Ka(I) and a corresponding current limiting circuit Kb for each of the pads Pd(1) to Pd(I). (1) to Kb(I), I may be a fixed integer. The i-th (i=1, . . . , I) pad Pd(i) is coupled to the internal circuit 32 via a corresponding current limiting circuit Kb(i) (which may be implemented by the resistor R(i)). The internal circuit 32 can exchange data signals with the outside world via these pads.
為了實現靜電放電保護與電子過壓防護,第i個接墊Pd(i)另經由對應的連接電路Ka(i)而統一耦接至節點CLMP1,連接電路Ka(i)可用一電晶體P(i)實現,或是依照第1圖與第3圖中的連接電路16與46實現)。節點CLMP1與節點IO_CLMP之間可設有J個(J為一整數定值)過壓控制電路Kc(1)至Kc(J),以及J個過壓控制電路Kd(1)至Kd(J)。第j個過壓控制電路Kc(j)與Kd(j)可分別由一或多個二極體串連而成。而在節點IO_CLMP與電源端GND之間則可設有L個(L為一整數定值)靜電放電箝制電路Ke(1)至Ke(L),每個靜電放電箝制電路可用第4圖或/及第5圖中的實施例來實現。節點IO_CLMP另經由又一連接電路42(可由一二極體D(1)實現)耦接至電源端VCC,而電源端VCC與GND之間則由一電源箝制電路24來控制這兩電源端間的電壓差。In order to achieve electrostatic discharge protection and electronic overvoltage protection, the i-th pad Pd(i) is uniformly coupled to the node CLMP1 via a corresponding connection circuit Ka(i), and the connection circuit Ka(i) can be used with a transistor P ( i) implemented, or implemented in accordance with connection circuits 16 and 46 in Figures 1 and 3. J (J is an integer fixed value) overvoltage control circuits Kc(1) to Kc(J) and J overvoltage control circuits Kd(1) to Kd(J) may be provided between the node CLMP1 and the node IO_CLMP. . The jth overvoltage control circuits Kc(j) and Kd(j) may be respectively connected in series by one or more diodes. And between the node IO_CLMP and the power supply terminal GND, there may be provided L (L is an integer fixed value) electrostatic discharge clamp circuits Ke(1) to Ke(L), and each electrostatic discharge clamp circuit can be used in FIG. 4 or / And the embodiment in FIG. 5 is implemented. The node IO_CLMP is further coupled to the power supply terminal VCC via a further connection circuit 42 (which can be implemented by a diode D(1)), and a power supply clamping circuit 24 between the power supply terminals VCC and GND controls the two power supply terminals. The voltage difference.
在第6圖的實施例中,I個連接電路Ka(1)至Ka(I)可搭配相同或不同數目的J個過壓控制電路Kc(1)至Kc(J)、Kd(1)至Kd(J)以及相同或不同數目的L個靜電放電箝制電路Ke(1)至Ke(L)。也就是說,I、J與L可以互相相同或相異。甚至,過壓控制電路Kc(.)與Kd(.)的數目也可以不相同。第6圖之實施例代表本發明可將多個接墊中的I個接墊Pd(.)群組起來,統一在節點CLMP1與IO_CLMP上共用J個過壓控制電路Kc(.)/Kd(.)與L個靜電放電箝制電路Ke(.)。在決定實際的數目時,可考量靜電放電保護能力、電子過壓防護能力與布局面積等因素。譬如說,若設置較多的過壓控制電路Kc(.)與靜電放電箝制電路Ke(.),可提供阻抗更低、導通能力較佳的靜電放電路徑,增強靜電放電保護能力。In the embodiment of FIG. 6, one of the connection circuits Ka(1) to Ka(I) may be matched with the same or different number of J overvoltage control circuits Kc(1) to Kc(J), Kd(1) to Kd (J) and the same or different number of L electrostatic discharge clamp circuits Ke (1) to Ke (L). That is to say, I, J and L can be identical or different from each other. Even the number of overvoltage control circuits Kc(.) and Kd(.) may be different. The embodiment of Fig. 6 represents that the present invention can group one of the plurality of pads Pd(.), and uniformly share J overvoltage control circuits Kc(.)/Kd on the nodes CLMP1 and IO_CLMP ( .) with L electrostatic discharge clamp circuits Ke(.). When determining the actual number, factors such as electrostatic discharge protection capability, electronic overvoltage protection capability, and layout area can be considered. For example, if more overvoltage control circuit Kc(.) and electrostatic discharge clamp circuit Ke(.) are provided, an electrostatic discharge path with lower impedance and better conduction capability can be provided, and the electrostatic discharge protection capability can be enhanced.
請繼續參考第7圖。第7圖為本發明靜電放電保護電路又一實施例70的電路示意圖,以顯示本發明應用於多接墊輸出入介面的另一實施例。在第7圖中,J個接墊Pd(1)至Pd(J)分別經由對應的J個限流電路Kb(1)至Kb(J)耦接至內部電路32以實現多接墊輸出入介面。與第6圖不同的是,第7圖中的第j個(j=1,...J)接墊Pd(j)對應的連接電路Ka(j)是分別由一對應的節點CLMP1(j)耦接至對應的過壓控制電路Kc(j)與Kd(j),再統一由節點IO_CLMP耦接至L個靜電放電箝制電路Ke(1)至Ke(L)。由於每個節點CLMP1(1)至CLMP1(J)是相互絕緣獨立的,故每個接墊Pd(j)都搭配有一組專用的過壓控制電路Kc(j)與Kd(j)。不過,這J個接墊還是可以在節點IO_CLMP上共用L個靜電放電箝制電路Ke(1)至Ke(L);其中J和L的數目可以相同或不同。Please continue to refer to Figure 7. Figure 7 is a circuit diagram showing still another embodiment 70 of the electrostatic discharge protection circuit of the present invention to show another embodiment of the present invention applied to a multi-pad input/output interface. In FIG. 7, the J pads Pd(1) to Pd(J) are respectively coupled to the internal circuit 32 via the corresponding J current limiting circuits Kb(1) to Kb(J) to realize multi-pad input and output. interface. Different from FIG. 6, the connection circuit Ka(j) corresponding to the jth (j=1, . . . J) pad Pd(j) in FIG. 7 is respectively composed of a corresponding node CLMP1 (j). ) is coupled to the corresponding overvoltage control circuits Kc(j) and Kd(j), and is coupled by the node IO_CLMP to the L electrostatic discharge clamp circuits Ke(1) to Ke(L). Since each node CLMP1(1) to CLMP1(J) are insulated from each other, each pad Pd(j) is paired with a dedicated set of overvoltage control circuits Kc(j) and Kd(j). However, the J pads can still share L electrostatic discharge clamp circuits Ke(1) to Ke(L) on the node IO_CLMP; wherein the numbers of J and L can be the same or different.
請參考第8圖,其所示意的是本發明靜電放電保護電路的又一實施例80。延續第1圖至第3圖的實施例,為了進一步增強內部電路對電子過壓的抵抗力,除限流電路34之外,本發明還可在每個接墊Pd與內部電路32之間另行設置對應的分壓電路82。限流電路34可用一電阻R1實現,耦接於節點Nio(接墊Pd)與內部電路32之間。分壓電路82則在節點Ng耦接於限流電路34與內部電路32之間;當接墊Pd承受電子過壓時,分壓電路82可在節點Ng(與電源端GND之間)提供一第三跨壓Vg至內部電路32,而此跨壓Vg會小於電子過壓之電壓。也就是說,經由本發明限流電路34與分壓電路82之運作,當電子過壓發生時,電子過壓的電壓不會完全傳導至內部電路32,以保護內部電路32中的電路(像是一個接收訊號的閘極)不會受到電子過壓破壞。Referring to Figure 8, a further embodiment 80 of the electrostatic discharge protection circuit of the present invention is illustrated. Continuing the embodiments of FIGS. 1 to 3, in order to further enhance the resistance of the internal circuit to electronic overvoltage, the present invention may be additionally provided between each of the pads Pd and the internal circuit 32 in addition to the current limiting circuit 34. A corresponding voltage dividing circuit 82 is provided. The current limiting circuit 34 can be implemented by a resistor R1 coupled between the node Nio (the pad Pd) and the internal circuit 32. The voltage dividing circuit 82 is coupled between the current limiting circuit 34 and the internal circuit 32 at the node Ng; when the pad Pd is subjected to electronic overvoltage, the voltage dividing circuit 82 can be at the node Ng (between the power supply terminal GND) A third voltage across the Vg is provided to the internal circuit 32, and the voltage across the Vg is less than the voltage of the electronic overvoltage. That is, via the operation of the current limiting circuit 34 and the voltage dividing circuit 82 of the present invention, when an electronic overvoltage occurs, the voltage of the electronic overvoltage is not completely conducted to the internal circuit 32 to protect the circuit in the internal circuit 32 ( Like a gate that receives a signal, it is not damaged by electronic overvoltage.
如第8圖所示,在本發明的一實施例中,本發明分壓電路82可由一電阻R2與一n通道金氧半場效電晶體Ns實現。電晶體Ns之閘極、源極與體極耦接於電源端GND,形成一閘極接地(gate ground)連接,汲極則於節點N1耦接於電阻R2。當電子過壓(譬如說是正向電子過壓)發生時,電晶體Ns可在汲極崩潰的情形下導通,並在節點N1與電源端GND維持一跨壓VH_Ns。再加上電阻R2在節點Ng與N1間提供的跨壓,分壓電路82在節點Ng(與電壓端GND)之間提供的總跨壓Vg可計算為:Vg=(Vin-VH_Ns)*R2/(R1+R2)+VH_Ns=Vin*R2/(R1+R2)+VH_Ns*R1/(R1+R2)。其中Vin是接墊Pd上的電壓(譬如說,Vin可以等於電子過壓的電壓OV+)。只要跨壓Vg小於內部電路32可耐受的電壓上限,本發明分壓電路82就能保護內部電路32不受電子過壓傷害。譬如說,若內部電路32是以一金氧半場效電晶體元件的閘極來從節點Ng接收接墊Pd上的訊號,當(正向)電子過壓發生時,只要分壓電路82能使跨壓Vg小於該元件的閘極氧化層崩潰電壓,內部電路32就可受到保護。As shown in FIG. 8, in an embodiment of the present invention, the voltage dividing circuit 82 of the present invention can be implemented by a resistor R2 and an n-channel MOS field-effect transistor Ns. The gate, the source and the body of the transistor Ns are coupled to the power supply GND to form a gate ground connection, and the drain is coupled to the resistor R2 at the node N1. When an electronic overvoltage (for example, a positive electronic overvoltage) occurs, the transistor Ns can be turned on in the event of a collapse of the drain, and maintain a voltage VH_Ns at the node N1 and the power supply terminal GND. In addition to the voltage across the resistor R2 provided between the nodes Ng and N1, the total voltage Vg provided by the voltage dividing circuit 82 between the node Ng (with the voltage terminal GND) can be calculated as: Vg = (Vin - VH_Ns) * R2/(R1+R2)+VH_Ns=Vin*R2/(R1+R2)+VH_Ns*R1/(R1+R2). Vin is the voltage on the pad Pd (for example, Vin can be equal to the voltage OV+ of the electronic overvoltage). The voltage dividing circuit 82 of the present invention protects the internal circuit 32 from electronic overvoltage damage as long as the voltage across the Vg is less than the upper voltage limit that the internal circuit 32 can withstand. For example, if the internal circuit 32 receives the signal on the pad Pd from the node Ng by the gate of a MOS field device, when the (forward) electronic overvoltage occurs, the voltage dividing circuit 82 can The internal circuit 32 can be protected by making the voltage across the gate Vg less than the gate oxide breakdown voltage of the component.
電阻R1、R2之阻值/尺寸與電晶體Ns之尺寸可根據電子過壓防護的需求與布局面積來決定。譬如說,增加電阻R1寬度與電晶體Ns的尺寸可減少跨壓Vg;若有面積上的考量,則可適當縮減電阻R2的尺寸及/或電晶體Ns的尺寸,只要能使跨壓Vg小於內部電路32之閘極氧化層崩潰電壓即可。另外,在分壓電路82中,也可選擇不設置電阻R2,也就是使電晶體Ns在節點N1的汲極直接連接到節點Ng。第8圖中的實施例可與本發明於第1圖至第3圖、第6圖至第7圖的實施例併用。The resistance/size of the resistors R1 and R2 and the size of the transistor Ns can be determined according to the requirements of the electronic overvoltage protection and the layout area. For example, increasing the width of the resistor R1 and the size of the transistor Ns can reduce the voltage across the Vg; if there is an area consideration, the size of the resistor R2 and/or the size of the transistor Ns can be appropriately reduced as long as the cross-over voltage Vg is smaller than The gate oxide of the internal circuit 32 may collapse. Further, in the voltage dividing circuit 82, it is also possible to select not to provide the resistor R2, that is, to connect the transistor Ns directly to the node Ng at the gate of the node N1. The embodiment of Fig. 8 can be used in combination with the embodiment of the present invention in Figs. 1 to 3 and Figs. 6 to 7.
總結來說,相對於習知靜電放電保護電路容易被電子過壓破壞的缺點,本發明靜電放電保護電路在維持靜電放電保護能力之餘還能兼顧電子過壓防護,使靜電放電保護機制與內部電路都能免於電子過壓的破壞。就如前面討論過的,在本發明之電路配置下,靜電放電保護與電子過壓防護兩者的設計考量可以適當地區隔、獨立,可以兼顧靜電放電保護與電子過壓防護兩者,不必相互妥協。本發明精神可實施運用於各種晶片、晶粒及/或積體電路的訊號輸出入介面中。譬如說,應用於顯示器的時間控制晶片(業界常簡稱為T-con)不僅必備靜電放電保護能力,也需要較佳的電子過壓防護能力,正可利用本發明來兼顧這兩者。In summary, compared with the conventional electrostatic discharge protection circuit, which is easily damaged by electronic overvoltage, the electrostatic discharge protection circuit of the present invention can simultaneously protect the electronic overvoltage protection while maintaining the electrostatic discharge protection capability, and the electrostatic discharge protection mechanism and the internal The circuit is immune to damage from electronic overvoltage. As discussed above, in the circuit configuration of the present invention, the design considerations of both electrostatic discharge protection and electronic overvoltage protection can be appropriately separated and independent, and both electrostatic discharge protection and electronic overvoltage protection can be considered. compromise. The spirit of the present invention can be implemented in signal input and output interfaces for various wafers, dies, and/or integrated circuits. For example, time-controlled wafers (often referred to as T-con in the industry) applied to displays not only require electrostatic discharge protection but also better electronic overvoltage protection, and the present invention can be utilized to balance both.
綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。In the above, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and various modifications and refinements can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
本案圖式中所包含之各元件列示如下:The components included in the diagram of this case are listed as follows:
16、26、28、36、42、46、Ka(1)-Ka(I)/Ka(J)‧‧‧連接電路16, 26, 28, 36, 42, 46, Ka(1)-Ka(I)/Ka(J)‧‧‧ connected circuits
18、38A-38B、Kc(1)-Kc(J)、Kd(1)-Kd(J)‧‧‧過壓控制電路18, 38A-38B, Kc(1)-Kc(J), Kd(1)-Kd(J)‧‧‧Overvoltage control circuit
20、30、40、60、70、80‧‧‧靜電放電保護電路20, 30, 40, 60, 70, 80‧‧‧ Electrostatic discharge protection circuit
22、Ke(1)-Ke(L)‧‧‧靜電放電箝制電路22, Ke (1) - Ke (L) ‧ ‧ electrostatic discharge clamp circuit
24‧‧‧電源箝制電路24‧‧‧Power clamp circuit
32‧‧‧內部電路32‧‧‧Internal circuits
34、Kb(1)-Kb(I)/Kb(J)‧‧‧限流電路34, Kb (1) - Kb (I) / Kb (J) ‧ ‧ current limiting circuit
52、62‧‧‧靜電放電偵測電路52, 62‧‧‧ Electrostatic Discharge Detection Circuit
54、64‧‧‧放電電路54, 64‧‧‧discharge circuit
82‧‧‧分壓電路82‧‧‧voltage circuit
Pd、Pd(1)-Pd(I)/Pd(J)‧‧‧接墊Pd, Pd(1)-Pd(I)/Pd(J)‧‧‧ pads
P1、B1、Pa1、Na1-Na3、P(1)-P(I)/P(J)、Ns‧‧‧電晶體P1, B1, Pa1, Na1-Na3, P(1)-P(I)/P(J), Ns‧‧‧ crystal
Da(1)-Da(N)、D(1)-D(N)、D(N+1)-D(N+M)‧‧‧二極體Da(1)-Da(N), D(1)-D(N), D(N+1)-D(N+M)‧‧‧ diode
CLMP1、IO_CLMP、TRi、CLMP1(1)-CLMP1(J)、Ng、N1、 Nio‧‧‧節點CLMP1, IO_CLMP, TRi, CLMP1(1)-CLMP1(J), Ng, N1 Nio‧‧ node
Vg‧‧‧跨壓Vg‧‧‧cross pressure
R1-R2、Ra、R(1)-R(I)/R(J)‧‧‧電阻R1-R2, Ra, R(1)-R(I)/R(J)‧‧‧ resistance
Str‧‧‧觸發訊號Str‧‧‧ trigger signal
TR‧‧‧觸發端TR‧‧‧Trigger
VCC、GND‧‧‧電源端VCC, GND‧‧‧ power terminal
本案得藉由下列圖式及說明,俾得一更深入之了解:第1圖至第3圖分別示意本發明靜電放電保護電路的各種實施例。The present invention can be further understood by the following figures and descriptions: Figures 1 through 3 respectively illustrate various embodiments of the electrostatic discharge protection circuit of the present invention.
第4圖至第5圖分別示意第1圖至第3圖中靜電放電箝制電路的各種實施例。4 to 5 are diagrams showing various embodiments of the electrostatic discharge clamp circuit of Figs. 1 to 3, respectively.
第6圖至第7圖分別示意本發明實現於多接墊輸出入介面的各種實施例。Figures 6 through 7 illustrate various embodiments of the present invention implemented in a multi-pad input and output interface, respectively.
第8圖為本發明針對內部電路增強電子過壓防護能力的一種實施例。Figure 8 is an embodiment of the present invention for enhancing the electronic overvoltage protection capability of an internal circuit.
22...靜電放電箝制電路twenty two. . . Electrostatic discharge clamp circuit
24...電源箝制電路twenty four. . . Power clamp circuit
30...靜電放電保護電路30. . . Electrostatic discharge protection circuit
32...內部電路32. . . Internal circuit
34...限流電路34. . . Current limiting circuit
36、42...連接電路36, 42. . . Connecting circuit
38A-38B...過壓控制電路38A-38B. . . Overvoltage control circuit
Pd...接墊Pd. . . Pad
P1...電晶體P1. . . Transistor
R1...電阻R1. . . resistance
D(1)-D(N)、D(N+1)-D(N+M)...二極體D(1)-D(N), D(N+1)-D(N+M). . . Dipole
CLMP1、IO_CLMP、Nio...節點CLMP1, IO_CLMP, Nio. . . node
VCC、GND...電源端VCC, GND. . . Power terminal
Claims (17)
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TW98135978A TWI431753B (en) | 2009-10-23 | 2009-10-23 | Esd protection circuit with eos immunity |
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TW98135978A TWI431753B (en) | 2009-10-23 | 2009-10-23 | Esd protection circuit with eos immunity |
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TW201115712A TW201115712A (en) | 2011-05-01 |
TWI431753B true TWI431753B (en) | 2014-03-21 |
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US8817433B2 (en) * | 2011-07-28 | 2014-08-26 | Arm Limited | Electrostatic discharge protection device having an intermediate voltage supply for limiting voltage stress on components |
WO2013066338A1 (en) | 2011-11-03 | 2013-05-10 | Intel Corporation | Charge injection and drain-based electrical overstress (eos) protection apparatus and method |
JP6680102B2 (en) * | 2016-06-16 | 2020-04-15 | 富士電機株式会社 | Semiconductor integrated circuit device |
TWI713279B (en) | 2019-05-17 | 2020-12-11 | 明基電通股份有限公司 | Over current protection system |
TWI784502B (en) * | 2021-04-29 | 2022-11-21 | 華邦電子股份有限公司 | Electrostatic discharge protection circuit |
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