CN115621277A - PWELL isolated gated diode triggered SCR device for ESD protection - Google Patents
PWELL isolated gated diode triggered SCR device for ESD protection Download PDFInfo
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- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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Abstract
The invention discloses a PWELL isolated grid controlled diode triggering SCR device for ESD protection, which comprises: a technical scheme with small voltage hysteresis amplitude and strong ESD robustness is provided by adding a P + injection region and a second N well on a conventional SCR and utilizing a grid-controlled diode for auxiliary triggering. On one hand, the SCR device is provided with an auxiliary trigger path of a grid-controlled diode, so that the trigger voltage of the device can be reduced, and the current discharge capacity can be improved; on the other hand, with the enhancement of ESD stress, an SCR trigger path of the device between the surface and the substrate is started, so that the ESD current discharge capacity of the device is enhanced, the ESD robustness of the device is improved, the maintaining voltage of the device can be improved due to the longer base region width, and the deep hysteresis problem of an ESD protection device is improved.
Description
Technical Field
The invention belongs to the field of electrostatic discharge protection of integrated circuits, and particularly relates to a PWELL isolated gate-controlled diode-triggered SCR device for ESD protection.
Background
With the rapid development of the field of integrated circuits, the integration level of Integrated Circuit (IC) chips is increasing, the process flow of electronic products and related application materials are diversified, and the production links are gradually increased. This makes the feature size of the IC fabrication process increasingly smaller, which raises the performance and power consumption of the chip, and also makes the reliability of the IC chip challenging, and the design of electrostatic Discharge (ESD) protection for on-chip ICs faces more and more serious challenges.
Different types of electrostatic discharge (ESD) models, ESD protection methods, ESD protection device designs, and their related test technologies for ICs have all developed rapidly. Generally, an ESD protection device needs to satisfy three conditions of transparency, effectiveness and robustness, that is, the protection device should be in an off state when an integrated circuit normally works, and should be rapidly turned on to discharge an ESD current when an ESD pulse arrives, and the protection device itself needs to have a certain resistance to the ESD pulse. It can be concluded from the electrical characteristics that the trigger voltage of the ESD protection device is lower than the breakdown voltage of the protected device, the sustain voltage of the protection device is higher than the normal operating voltage of the chip, and for safety reasons, a safety margin of 10% -15% is usually required, and in addition, the secondary failure current of the protection device is high enough.
At present, ESD protection devices commonly used for an on-chip IC mainly comprise a diode, an MOS (metal oxide semiconductor) transistor and a Silicon Controlled Rectifier (SCR), and the ESD protection devices have advantages and disadvantages and need to be reasonably selected according to the needs of actual conditions. The diode has simple structure and less parasitic effect, is commonly used for ESD protection of low-voltage IC, but has larger leakage current of the device; the MOS tube has good process compatibility, is widely applied to ESD protection of on-chip ICs, particularly NMOS, and is more applied to ESD protection of each IO port in the ICs due to the fact that the comprehensive performance of the NMOS is compromised in the ESD protection. The biggest defects of the MOS device are represented by poor ESD robustness and large occupied chip area.
Compared with a diode device and a MOS device, the SCR device has enhanced ESD robustness under the condition of consuming the same chip area. However, the SCR structure has a deep hysteresis characteristic (high trigger voltage and low holding voltage) under the action of ESD stress, and thus latch-up is easily generated. Therefore, the conventional SCR structure generally cannot be directly used for ESD protection of an on-chip IC, and the conventional SCR structure is improved and designed based on layout optimization to meet the requirements of a circuit according to the working requirements of different circuits.
Disclosure of Invention
In order to solve the problem that a traditional low-trigger-voltage SCR is used as a low-holding voltage of an ESD protection device, the embodiment of the invention provides a PWELL-isolated grid-controlled diode trigger SCR device for ESD protection, which fully utilizes the characteristic of strong ESD robustness of an SCR structure, and increases the base region width of a triode in a parasitic SCR by embedding a grid-controlled diode, so that the device can form a grid-controlled diode auxiliary trigger path and an SCR trigger path positioned on the surface and a buried layer under the action of ESD pulses, and an ESD protection design scheme with low trigger, high holding voltage and strong ESD robustness is realized.
The PWELL isolated gate-controlled diode triggering SCR device for ESD protection comprises a P substrate, and is characterized by further comprising a first N well, a P well and a second N well which are arranged on the surface of the P substrate, a first N + injection region and a second P + injection region which are respectively embedded into the first N well and the P well, a first P + injection region which stretches across the first N well and the P well and is embedded into the first N well, a third P + injection region which stretches across the P well and the second N well and is embedded into the second N well, and a second N + injection region, a fourth P + injection region and a third N + injection region which are embedded into the second N well at intervals;
a first thin gate oxide layer and a first polycrystalline silicon gate layer covering the first thin gate oxide layer are arranged on the surface of the first N well and between the first N + injection region and the first P + injection region, and a second thin gate oxide layer and a second polycrystalline silicon gate covering the second thin gate oxide layer are arranged on the surface of the second N well and between the third P + injection region and the second N + injection region;
a gate control diode D2 is formed by the first N + injection region, the first N well, the first thin gate oxide layer, a first polycrystalline silicon gate layer covering the first thin gate oxide layer and the first P + injection region;
a gate-controlled diode D1 is formed by the third P + injection region, the second N well, the second thin gate oxide layer, the second polysilicon gate covering the second thin gate oxide layer and the second N + injection region;
the second N well and the third N + implantation region form a parasitic resistance Rn1, the fourth P + implantation region, the second N well, the P well and the P substrate form a parasitic PNP triode Q1, the fourth P + implantation region, the second N well and the third P + implantation region form a parasitic PNP triode Q2, the second P + implantation region, the P well and the third P + implantation region form a parasitic resistance Rp1, the second N well, the P well and the first N well form a parasitic NPN triode Q3, the P substrate 101 forms a parasitic resistance Rp2, and the first N + implantation region and the first N well form a parasitic resistance Rn2.
In an embodiment, on the surface of the P substrate, the left edge of the P substrate is connected to the left edge of the first N well, the right side of the first N well is connected to the left side of the P well, the right side of the P well is connected to the left side of the second N well, and the right side of the second N well is connected to the right edge of the P substrate.
In an embodiment, on the surface of the first N well, the left side of the first thin gate oxide layer and the first polysilicon gate layer covering the first thin gate oxide layer are connected to the right side of the first N + implantation region, and the right side of the first thin gate oxide layer and the first polysilicon gate layer covering the first thin gate oxide layer are connected to the left side of the first P + implantation region.
In an embodiment, on the surface of the second N well, the left side of the second thin gate oxide layer and the second polysilicon gate covering the second thin gate oxide layer are connected to the right side of the third P + implantation region, and the right side of the second thin gate oxide layer and the second polysilicon gate covering the second thin gate oxide layer are connected to the left side of the second N + implantation region.
In an embodiment, when the SCR device is used for ESD protection, the circuit connection of the SCR device includes: the first N + injection region is connected with a first metal, the first polysilicon gate is connected with a second metal, the first P + injection region is connected with a third metal, the second P + injection region is connected with a fourth metal, the third P + injection region is connected with a fifth metal, the second polysilicon gate is connected with a sixth metal, the second metal, the third metal, the fifth metal and the sixth metal are all connected with a tenth metal, the first metal and the fourth metal are all connected with a ninth metal, and a first electrode is led out from the ninth metal and used as a metal cathode of a device;
the fourth P + injection region is connected with a seventh metal, the third N + injection region is connected with an eighth metal, the seventh metal and the eighth metal are both connected with an eleventh metal, and a second electrode is led out from the eleventh metal and used as a metal anode of the device.
In an embodiment, when a forward ESD stress occurs at the metal anode 2 of the device, avalanche breakdown first occurs at the junction of the second N well and the third P + implant region, and the reverse gated diode D1 is immediately turned on; then, the ESD current reaches the metal cathode through the reverse gated diode D1 and the forward gated diode D2, and the ESD current in the second N well will be collected in the second N + injection region 109 that is floating;
furthermore, an electrostatic discharge current will apply a voltage to the gate of the gated diode through the third P + implant region that is bridged.
In an embodiment, the potential of the second N-well increases when ESD is present on the metal anode; at a certain moment, avalanche breakdown starts to occur at the junction of the second N well and the third P + injection region due to the high electric fields of the two regions, and electron-hole pairs are generated; then, a hole current flows into the P-well through the parasitic PNP transistor Q1 and the parasitic PNP transistor Q2, which increases the potential of the P-well; an emitter-base junction of the parasitic NPN triode Q3 is positively biased through the potential of the P trap and is conducted; the current of Q3 from the collector of Q1 to the cathode provides a forward bias for Q1; the voltage at the anode 213 no longer needs to provide a bias for the Q1.
In an embodiment, the length of the P well, the length of the first P + implantation region, the length of the third P + implantation region, and the distance between the second P + implantation region and the third P + implantation region are adjusted to achieve tuning of the holding voltage to meet different requirements.
Compared with the prior art, the invention has the beneficial effects that at least:
in the invention, the first N + injection region, the first thin gate oxide layer, the first polysilicon gate layer covering the first N + injection region, the first P + injection region, the third P + injection region, the second polysilicon gate, the second thin gate oxide layer covering the second polysilicon gate and the second N + injection region form two gate-controlled diodes, the third P + injection region has low trigger voltage due to high concentration, the first N well and the first N + injection region form a parasitic resistance Rn2, and a parasitic capacitor formed by the second thin gate oxide layer, the second polysilicon gate covering the second N well and the parasitic resistance Rn2 can form a resistance-capacitance coupling trigger network, so that the trigger voltage of the device is reduced, and the starting speed of the device is improved.
In the invention, the P substrate, the first N well, the P well, the second N well, the first N + injection region, the second P + injection region, the third P + injection region, the fourth P + injection region and the third N + injection region form an SCR path. The second N trap, the P trap and the first N trap form a parasitic NPN triode, the second P + injection region, the P trap and the third P + injection region form a parasitic resistor Rp1, the parasitic resistor Rn2, the parasitic resistor Rp1 and the P trap serving as a base region of the parasitic NPN triode improve the device holding voltage, and the SCR path can enhance the ESD robustness of the device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural cross-sectional view of an SCR device provided in an embodiment of the present invention;
fig. 2 is a circuit diagram of an SCR for ESD protection according to an embodiment of the present invention;
FIG. 3 is an equivalent circuit diagram of an auxiliary trigger path of an SCR under ESD stress according to an embodiment of the present invention;
fig. 4 is an equivalent circuit diagram of an SCR trigger path of an SCR device under ESD stress according to an embodiment of the present invention.
FIG. 5 is a diagram comparing an SCR device provided by an embodiment of the present invention with a conventional low trigger voltage SCR structure;
fig. 6 is a comparison graph of the testing results of the SCR device provided by the embodiment of the present invention in the forward direction electrostatic protection.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the detailed description and specific examples, while indicating the scope of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
Aiming at the deep hysteresis problem of the traditional SCR structure in ESD protection, a technical scheme with small voltage hysteresis amplitude and strong ESD robustness is provided by adding a P + injection region and a second N-Well on the conventional SCR and utilizing a grid-controlled diode for auxiliary triggering. On one hand, the device is provided with an auxiliary trigger path of a grid-controlled diode, so that the trigger voltage of the device can be reduced, and the current discharge capacity can be increased; on the other hand, with the enhancement of ESD stress, an SCR trigger path between the surface of the device and the substrate is started, so that the ESD current discharge capacity of the device is enhanced, the ESD robustness of the device is improved, the maintaining voltage of the device can be improved by adjusting the width of the base region of the longer parasitic triode, and the deep hysteresis problem of the ESD protection device is improved.
Fig. 1 shows a cross-sectional view of an internal structure of an SCR device according to an embodiment of the present invention, and the embodiment designs a PWELL-isolated gate-controlled diode-triggered SCR device for ESD protection, which includes an auxiliary trigger path of a gate-controlled diode and an SCR trigger path located on a surface and a substrate and having a base width of a parasitic triode adjusted, so as to reduce a trigger voltage of an ESD protection device, improve a holding voltage, reduce a voltage hysteresis amplitude after the ESD protection device is turned on, and enhance ESD robustness of the device, which specifically includes: the structure comprises a P substrate (P-sub) 101, a first N well (Nwell) 102, a P well (Pwell) 103, a second N well (Nwell) 104, a first N + injection region 105, a first P + injection region 106, a second P + injection region 107, a third P + injection region 108, a second N + injection region 109, a fourth P + injection region 110, a third N + injection region 111, a first thin gate oxide layer 112, a first polysilicon gate layer 113 and a second thin gate oxide layer 114 covering the first thin gate oxide layer, and a second polysilicon gate 115 covering the first thin gate oxide layer and the second thin gate oxide layer 114.
The first N well 102, the P well 103 and the second N well 104 are sequentially arranged on the surface area of the P substrate 101 from left to right, the left side edge of the P substrate 101 is connected with the left side edge of the first N well 102, the right side of the first N well 102 is connected with the left side of the P well 103, the right side of the P well 103 is connected with the left side of the second N well 104, and the right side of the second N well 104 is connected with the right side edge of the P substrate 101.
The first N + implantation region 105 and the second P + implantation region 107 are embedded into the first N well 102 and the P well 103, respectively, from the surface, and the second N + implantation region 109, the fourth P + implantation region 110, and the third N + implantation region 111 are embedded into the second N well 104 from the surface in a spaced manner. The first P + implant region 106 spans and embeds the first N-well 102 and the P-well 103. The third P + implant region 108 spans and is embedded in the P-well 103 and the second N-well 104.
The first thin gate oxide layer 112 and the first polysilicon gate layer 113 covering the first thin gate oxide layer are disposed on the surface of the first N well 102 and between the first N + injection region 105 and the first P + injection region 106, specifically, the left side of the first thin gate oxide layer 112 and the first polysilicon gate layer 113 covering the first thin gate oxide layer 112 is connected to the right side of the first N + injection region 105, and the right side of the first thin gate oxide layer 112 and the first polysilicon gate layer 113 covering the first thin gate oxide layer 112 is connected to the left side of the first P + injection region 106.
The second thin gate oxide layer 114 and the second polysilicon gate 115 covering the second thin gate oxide layer are disposed on the surface of the second N well 104 and between the third P + implantation region 108 and the second N + implantation region 109, specifically, the left side of the second thin gate oxide layer 114 and the second polysilicon gate 115 covering the second thin gate oxide layer 114 are connected to the right side of the third P + implantation region 108, and the right side of the second thin gate oxide layer 114 and the second polysilicon gate 115 covering the second thin gate oxide layer 114 are connected to the left side of the second N + implantation region 109.
The length of the first thin gate oxide layer 112 and the first polysilicon gate layer 113 covering the first thin gate oxide layer, the length of the second thin gate oxide layer 114 and the second polysilicon gate 115 covering the second thin gate oxide layer meet the minimum characteristic dimension of the preparation process, the length of the P-well 103 is designed according to requirements, the base region width of a parasitic NPN tube can be increased, and the holding voltage of the device is improved.
In an embodiment, when the SCR device is used for ESD protection, as shown in fig. 2, the circuit connection of the SCR device includes: the first N + injection region 105 is connected with a first metal 201, the first polysilicon gate 113 is connected with a second metal 202, the first P + injection region 106 is connected with a third metal 203, the second P + injection region 107 is connected with a fourth metal 204, the third P + injection region 108 is connected with a fifth metal 205, the second polysilicon gate 115 is connected with a sixth metal 206, the second metal 202, the third metal 203, the fifth metal 205 and the sixth metal 206 are all connected with a tenth metal 210, the first metal 201 and the fourth metal 204 are all connected with a ninth metal 209, and a first electrode 212 is led out from the ninth metal 209 and used as a metal cathode of a device.
The fourth P + injection region 110 is connected to a seventh metal 207, the third N + injection region 111 is connected to an eighth metal 208, both the seventh metal 207 and the eighth metal 208 are connected to an eleventh metal 211, and a second electrode 213 is led out from the eleventh metal 211 and used as a metal anode of the device. It is to be noted that the same material is selected for all metals.
Fig. 3 is an equivalent circuit diagram of an auxiliary trigger path of an SCR device under ESD stress according to an embodiment of the present invention. As shown in fig. 3, the first N + implantation region 105, the first N well 102, the first thin gate oxide layer 112, the first polysilicon gate layer 113 covering the first thin gate oxide layer, and the first P + implantation region 106 form a gated diode D2. The third P + implantation region 108, the second N well 104, the second thin gate oxide layer 114, and the second polysilicon gate 115 and the second N + implantation region 109 covering the third thin gate oxide layer form a gated diode D1. When a forward ESD stress occurs at the metal anode 213 of the device, avalanche breakdown occurs first at the junction of the second N well 104 and the third P + implantation region 108, and the reverse gated diode D1 is turned on immediately, because the third P + implantation region 108 has a higher concentration, and therefore has a lower trigger voltage, the parasitic resistance Rn1 is formed by the second N well 104 and the third N + implantation region 111. Then, the ESD current passes through the reverse-gated diode D1 and the forward-gated diode D2 to reach the metal cathode 212 of the device, and the ESD current in the second N well 104 will be collected in the second N + injection region 109 which is floating because the second N + injection region 109 which is floating has a higher doping concentration.
In addition, the electrostatic discharge current will apply a voltage to the gates of the gated diodes D1 and D2 through the bridged third P + implantation region 108, which will increase the current discharge capability of the gated diode D1 and accelerate the conduction of the gated diode D2. On the other hand, for the gated diode D1, a resistance-capacitance coupling trigger network is formed by a gate capacitor and a parasitic resistor formed by the second N + injection region 109 and the second N well 104, so that the trigger voltage of the device is reduced, and the turn-on speed of the device is increased. The increased gate voltage further enhances the gate coupling effect, thereby improving the current discharge capability of the gated diode D1. For the gated diode D2, the first polysilicon layer 113 reduces the current path length of the gated diode D2 and enables triggering at a lower voltage and faster response time under ESD stress. The gate voltage accelerates this process and, therefore, the gate voltage accelerates the conduction of the gate diode D2. Once the gated diode D2 is turned on, the auxiliary triggered diode path starts to discharge ESD current, and when the voltage drop generated by the current across the parasitic resistor Rn1 reaches 0.7V, the SCR path is triggered to discharge the main ESD current.
Fig. 4 is an equivalent circuit diagram of an SCR trigger path under ESD stress of an SCR device according to an embodiment of the present invention. As shown in fig. 4, the second N well 104 and the third N + implantation region 111 form a parasitic resistor Rn1, the fourth P + implantation region 110, the second N well 104, the P well 103 and the P substrate 101 form a parasitic PNP transistor Q1, the fourth P + implantation region 110, the second N well 104 and the third P + implantation region 108 form a parasitic PNP transistor Q2, the second P + implantation region 107, the P well 103 and the third P + implantation region 108 form a parasitic resistor Rp1, the second N well 104, the P well 103 and the first N well 102 form a parasitic NPN transistor Q3, the P substrate 101 forms a parasitic resistor Rp2, and the first N + implantation region 105 and the first N well 102 form a parasitic resistor Rn2.
When ESD occurs on the metal anode 213, the potential of the second N-well 104 increases. At some point, avalanche breakdown will begin to occur at the junction of the second N-well 104 and the third P + injection region 108 due to the high electric field of both regions, and electron-hole pairs will be generated. Then, a hole current flows into the P-well 103 through the parasitic PNP transistor Q1, the parasitic PNP transistor Q2, which increases the potential of the P-well 103. The emitter-base junction of the parasitic NPN transistor Q3 is forward biased by the potential of the P well 103 and is turned on. The current of the Q3 from the collector of the Q1 to the cathode provides a forward bias for the Q1. The voltage at the anode 213 no longer needs to provide a bias for the Q1. Therefore, no matter the ESD current discharged from the diode path for auxiliary triggering generates a voltage drop of 0.7V across the parasitic resistor Rn1, or the emitter-base junction of the parasitic NPN triode Q3 is forward biased by the potential of the P-well 103, the SCR path will be triggered to discharge the main ESD current, so that a lower triggering voltage and higher robustness are achieved.
In addition, since free carriers are injected from the emitter regions of the two PNP transistors Q1 and Q2, the holding voltage depends on the degree of space charge neutralization of the base regions of the NPN transistor Q3 and the PNP transistors Q1, Q2. Therefore, the lateral dimensions related to the base width of the transistor and the Rn2, rp1 are very important. The length of the P well 103, the length of the first P + implantation region 106, the length of the third P + implantation region 108, and the distance between the second P + implantation region 107 and the third P + implantation region 108 are adjusted to realize the tuning of the holding voltage to meet different requirements.
Fig. 5 is a comparison graph of the SCR device provided by the embodiment of the present invention and a conventional low trigger voltage SCR structure, and fig. 6 is a comparison graph of the test result of the SCR device provided by the embodiment of the present invention in forward electrostatic protection. As can be seen from fig. 6, when the structure is used for forward electrostatic pulse protection, the sustain Voltage (Voltage) of the conventional low trigger Voltage SCR structure is about 3V, and the sustain Voltage of the SCR device provided in this embodiment is about 6V, which is significantly higher than that of the conventional SCR structure; the trigger voltage of the conventional low trigger voltage SCR is about 10V, and the trigger voltage of the SCR device provided by the embodiment is about 10V, which is substantially the same as that of the conventional SCR structure; meanwhile, as can be seen from fig. 6, the failure current of the conventional low-trigger-voltage SCR device is about 2.6A, while the failure current of the SCR device provided in this embodiment is about 2.6A, which is substantially the same as the failure current of the SCR device provided in this embodiment compared to the conventional low-trigger-voltage SCR structure; that is, under the condition that the trigger voltage and the failure current are substantially unchanged, the holding voltage of the SCR device provided by the embodiment is significantly improved compared with the conventional low-trigger-voltage SCR structure.
In a word, the SCR device provided in the above embodiment reduces the trigger voltage of the device by using the gate controlled diode, and increases the turn-on speed of the device; in addition, the advantage that the SCR structure has stronger ESD robustness is combined, and the SCR holding voltage is improved through the design of the structure; under the action of ESD stress, the SCR device provided by the embodiment can not only form an auxiliary trigger path consisting of grid-controlled diodes so as to reduce the voltage hysteresis amplitude after the ESD protection device is started, but also form an SCR trigger path with high maintaining voltage so as to enhance the ESD robustness of the device.
The technical solutions and advantages of the present invention have been described in detail in the foregoing detailed description, and it should be understood that the above description is only the most preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, additions, and equivalents made within the scope of the principles of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. The gate-controlled diode-triggered SCR device comprises a P substrate, and is characterized by further comprising a first N well, a P well and a second N well which are arranged on the surface of the P substrate, a first N + injection region and a second P + injection region which are respectively embedded into the first N well and the P well, a first P + injection region which stretches across the first N well and the P well and is embedded into the first N well, a third P + injection region which stretches across the P well and the second N well and is embedded into the second N well, and a second N + injection region, a fourth P + injection region and a third N + injection region which are embedded into the second N well at intervals;
a first thin gate oxide layer and a first polycrystalline silicon gate layer covering the first thin gate oxide layer are arranged on the surface of the first N well and between the first N + injection region and the first P + injection region, and a second thin gate oxide layer and a second polycrystalline silicon gate covering the second thin gate oxide layer are arranged on the surface of the second N well and between the third P + injection region and the second N + injection region;
a gate control diode D2 is formed by the first N + injection region, the first N well, the first thin gate oxide layer, a first polycrystalline silicon gate layer covering the first thin gate oxide layer and the first P + injection region;
a gate-controlled diode D1 is formed by the third P + injection region, the second N well, the second thin gate oxide layer, the second polysilicon gate covering the second thin gate oxide layer and the second N + injection region;
the second N well and the third N + implantation region form a parasitic resistance Rn1, the fourth P + implantation region, the second N well, the P well and the P substrate form a parasitic PNP triode Q1, the fourth P + implantation region, the second N well and the third P + implantation region form a parasitic PNP triode Q2, the second P + implantation region, the P well and the third P + implantation region form a parasitic resistance Rp1, the second N well, the P well and the first N well form a parasitic NPN triode Q3, the P substrate forms a parasitic resistance Rp2, and the first N + implantation region and the first N well form a parasitic resistance Rn2.
2. The PWELL-isolated gated diode triggered SCR device for ESD protection of claim 1, wherein at the surface of the pbase, the left edge of the pbase is connected to the left edge of the first N-well, the right side of the first N-well is connected to the left side of the P-well, the right side of the P-well is connected to the left side of the second N-well, and the right side of the second N-well is connected to the right edge of the pbase.
3. The PWELL isolated gated diode triggered SCR device for ESD protection of claim 1, wherein the left side of the first thin gate oxide layer and the overlying first polysilicon gate layer is connected to the right side of the first N + implant region and the right side of the first thin gate oxide layer and the overlying first polysilicon gate layer is connected to the left side of the first P + implant region on the surface of the first N-well.
4. The PWELL-isolated gated diode triggered SCR device for ESD protection as claimed in claim 1, wherein the left side of the second thin gate oxide and the second polysilicon gate overlying it is connected to the right side of the third P + implant region and the right side of the second thin gate oxide and the second polysilicon gate overlying it is connected to the left side of the second N + implant region at the surface of the second N-well.
5. The PWELL isolated gated diode triggered SCR device for ESD protection as claimed in claim 1, wherein the circuit connection of the SCR device when the SCR device is used for ESD protection comprises: the first N + injection region is connected with a first metal, the first polysilicon gate is connected with a second metal, the first P + injection region is connected with a third metal, the second P + injection region is connected with a fourth metal, the third P + injection region is connected with a fifth metal, the second polysilicon gate is connected with a sixth metal, the second metal, the third metal, the fifth metal and the sixth metal are all connected with a tenth metal, the first metal and the fourth metal are all connected with a ninth metal, and a first electrode is led out from the ninth metal and used as a metal cathode of a device;
the fourth P + injection region is connected with a seventh metal, the third N + injection region is connected with an eighth metal, the seventh metal and the eighth metal are both connected with an eleventh metal, and a second electrode is led out from the eleventh metal and used as a metal anode of the device.
6. The PWELL-isolated gated diode triggered SCR device for ESD protection as recited in claim 1, wherein when forward ESD stress occurs at the metal anode 2 of the device, avalanche breakdown occurs first at the junction of the second N-well and the third P + implant region, and the reverse gated diode D1 is immediately turned on; then, the ESD current reaches the metal cathode through the reverse gated diode D1 and the forward gated diode D2, and the ESD current in the second N well will be collected in the second N + injection region 109 that is floating;
in addition, an electrostatic discharge current will apply a voltage to the gate of the gated diode through the third P + implant region that is bridged.
7. The PWELL-isolated gated diode triggered SCR device for ESD protection of claim 1, wherein the potential of the second N-well increases when ESD is present on the metal anode; at a certain moment, avalanche breakdown starts to occur at the junction of the second N well and the third P + injection region due to the high electric fields of the two regions, and electron-hole pairs are generated; then, a hole current flows into the P-well through the parasitic PNP transistor Q1 and the parasitic PNP transistor Q2, which increases the potential of the P-well; an emitter-base junction of the parasitic NPN triode Q3 is positively biased through the potential of the P trap and is conducted; the current of Q3 from the collector of Q1 to the cathode provides a forward bias for Q1; the voltage at the anode 213 no longer needs to provide a bias for the Q1.
8. The PWELL isolated gated diode triggered SCR device for ESD protection of claim 1, wherein tuning of a holding voltage to meet different requirements can be achieved by adjusting the length of the P-well, the first P + implant region, the third P + implant region length, and the distance of the second P + implant region from the third P + implant region.
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| CN202211312469.XA CN115621277A (en) | 2022-10-25 | 2022-10-25 | PWELL isolated gated diode triggered SCR device for ESD protection |
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| CN202211312469.XA CN115621277A (en) | 2022-10-25 | 2022-10-25 | PWELL isolated gated diode triggered SCR device for ESD protection |
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