CN104681543A - Encapsulating structure with clamping and ESD (Electro-Static Discharge) protection - Google Patents
Encapsulating structure with clamping and ESD (Electro-Static Discharge) protection Download PDFInfo
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- CN104681543A CN104681543A CN201310637544.4A CN201310637544A CN104681543A CN 104681543 A CN104681543 A CN 104681543A CN 201310637544 A CN201310637544 A CN 201310637544A CN 104681543 A CN104681543 A CN 104681543A
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- CN
- China
- Prior art keywords
- encapsulating structure
- esd protection
- esd
- chip
- clamp
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- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an encapsulating structure with clamping and ESD (Electro-Static Discharge) protection. The encapsulating structure is connected between a chip PAD and a circuit, can play a role in voltage clamping, and forms a current discharge channel for periodic low-energy pulse peak signals in signals accessing to the chip PAD. The encapsulating structure can play a role in ESD protection, and forms a current discharge channel for periodic low-energy pulse peak signals. The area of a chip is saved, and the production cost is reduced.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to the implementation method of esd protection circuit and voltage clamp.
Background technology
Along with the continuous reduction of CMOS IC gate oxide thickness and characteristic size, result in the continuous decline of MOS device for high pressure and big current ability to bear, and static discharge (electro-static discharge, the ESD) impact on CMOS IC reliability is more remarkable.According to statistics, the chip failure of 30 more than % is caused by ESD, and therefore the design of esd protection circuit and structure becomes one of importance of IC reliability design.Likely in device inside structure or external environment condition, certain electric charge has been accumulated in the middle of the production of integrated circuit (IC) chip, transport, assembling process, these electric charges can be made after connecting with low impedance path to be sparked by the pin of chip, flow into or flow out chip, its peak current is according to the difference of discharge mode, several amperes of even tens of amperes can be reached, be enough to that chip internal the is subjected to infringements such as dielectric punctures, the short circuit of PN junction scaling loss, metal connecting line fusing, the basic process of integrated circuit ESD phenomenon that Here it is.Meanwhile, static discharge has the feature of energy height and non-repeatability.
When integrated circuit (IC) chip is used for whole Circuits System, because the inductive load that may exist in system and switching over will produce the harassing and wrecking of corresponding transient voltage pulses spike, if there is multiple load short time inter-sync to switch or single load short time switching action, then can produce corresponding Clusters.The fluctuation of line voltage also can cause the leg signal being connected to chip to undergo mutation.The signal intensity that integrated circuit (IC) chip peripheral system causes has the low and repeated feature of energy.
Summary of the invention
The invention provides a kind of encapsulating structure having clamp and esd protection concurrently, it can not only play the effect of voltage clamp, to being linked into periodicity in chip pad signal, low-energy pulse spike formation current drain path; The effect of esd protection can also be played, current drain path is formed to aperiodicity, high-octane pulse spike.Save the area of chip, reduce production cost.
Accompanying drawing explanation
Fig. 1 is esd protection circuit typical case TLP characteristic curve.
Fig. 2 is the encapsulating structure that the present invention has clamp and esd protection concurrently.
Embodiment
Fig. 1 is esd protection circuit typical case TLP characteristic curve.When after the esd pulse applying a forward on the input signals, when voltage rise is to V
3before, the electric current flowing through esd protection circuit is all very little, and esd protection circuit is not triggered; When voltage rise is to V
3after, voltage can not rise again, and esd protection circuit is unlocked, and we claim V
3for cut-in voltage; Voltage drop subsequently, electric current increases, and reaches voltage V
1, we claim V
1for ME for maintenance, from (V
3, I
3) to (V
1, I
1) be called Zhou Hui district; Voltage rise subsequently, electric current also sharply rises, and arrives (V
2, I
2) front region is called esd protection district; At (V
2, I
2) put the secondary breakdown voltage point reaching esd protection circuit, esd protection voltage thermal failure subsequently.This structure is for aperiodicity, and the pulse signal that energy is high can form good leakage current path.
When integrated circuit (IC) chip is used for whole Circuits System, because the inductive load that may exist in system and switching over will produce the harassing and wrecking of corresponding transient voltage pulses spike, if there is multiple load short time inter-sync to switch or single load short time switching action, then can produce corresponding Clusters.The fluctuation of line voltage also can cause the leg signal being connected to chip to undergo mutation.The signal intensity that integrated circuit (IC) chip peripheral system causes has the low and repeated feature of energy.For this type of pulse signal, traditional esd protection circuit can not form to it path of releasing, and generally also needs to do a clamp circuit at chip internal.
Fig. 2 is the encapsulating structure that the present invention has clamp and esd protection concurrently.Unique distinction of the present invention is that it can not only play the effect of voltage clamp, forms current drain path to periodicity, low-energy pulse spike in signal; The effect of esd protection can also be played, current drain path is formed to aperiodicity, high-octane pulse spike.New construction of the present invention can just start leakage current path at lower voltage, and this low pressure process easy to use realizes protective effect.The obvious advantage of the present invention can reach by the structure of the lower chip area of lower cost the effect both achieving esd protection, achieves again the effect of voltage clamp.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (3)
1. have an encapsulating structure for clamp and esd protection concurrently, it is characterized in that, it is connected between chip PAD and internal circuit.
2. have an encapsulating structure for clamp and esd protection concurrently, it is characterized in that, it can play the effect of clamp and esd protection simultaneously.
3. have an encapsulating structure for clamp and esd protection concurrently, it is characterized in that, it can form current drain path to the pulse signal of low-yield, repeated pulse signal and high-energy, non-repeatability simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310637544.4A CN104681543A (en) | 2013-12-03 | 2013-12-03 | Encapsulating structure with clamping and ESD (Electro-Static Discharge) protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310637544.4A CN104681543A (en) | 2013-12-03 | 2013-12-03 | Encapsulating structure with clamping and ESD (Electro-Static Discharge) protection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104681543A true CN104681543A (en) | 2015-06-03 |
Family
ID=53316399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310637544.4A Pending CN104681543A (en) | 2013-12-03 | 2013-12-03 | Encapsulating structure with clamping and ESD (Electro-Static Discharge) protection |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104681543A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112769113A (en) * | 2020-12-22 | 2021-05-07 | 深圳市创芯微微电子有限公司 | Battery protection chip and protection circuit thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030076645A1 (en) * | 2001-10-19 | 2003-04-24 | Ming-Dou Ker | ESD protection circuit for mixed-voltage I/O ports using substrated triggering |
| CN1447427A (en) * | 2002-03-26 | 2003-10-08 | 华邦电子股份有限公司 | Electrostatic discharge protection circuit |
| CN102204087A (en) * | 2008-10-29 | 2011-09-28 | 高通股份有限公司 | Amplifier with improved ESD protection circuitry |
| CN102544001A (en) * | 2012-03-15 | 2012-07-04 | 电子科技大学 | SCR (Silicon Controlled Rectifier) structure for providing ESD ( Electro-Static discharge) protection for I/O (Input/Output) port of integrated circuit under all modes |
-
2013
- 2013-12-03 CN CN201310637544.4A patent/CN104681543A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030076645A1 (en) * | 2001-10-19 | 2003-04-24 | Ming-Dou Ker | ESD protection circuit for mixed-voltage I/O ports using substrated triggering |
| CN1447427A (en) * | 2002-03-26 | 2003-10-08 | 华邦电子股份有限公司 | Electrostatic discharge protection circuit |
| CN102204087A (en) * | 2008-10-29 | 2011-09-28 | 高通股份有限公司 | Amplifier with improved ESD protection circuitry |
| CN102544001A (en) * | 2012-03-15 | 2012-07-04 | 电子科技大学 | SCR (Silicon Controlled Rectifier) structure for providing ESD ( Electro-Static discharge) protection for I/O (Input/Output) port of integrated circuit under all modes |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112769113A (en) * | 2020-12-22 | 2021-05-07 | 深圳市创芯微微电子有限公司 | Battery protection chip and protection circuit thereof |
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|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150603 |