CN102142440A - Thyristor device - Google Patents
Thyristor device Download PDFInfo
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- CN102142440A CN102142440A CN 201010615666 CN201010615666A CN102142440A CN 102142440 A CN102142440 A CN 102142440A CN 201010615666 CN201010615666 CN 201010615666 CN 201010615666 A CN201010615666 A CN 201010615666A CN 102142440 A CN102142440 A CN 102142440A
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Abstract
The invention discloses a thyristor device, which comprises a P-type substrate, wherein a first N well and a second N well are arranged on the P-type substrate; the first N well is connected with an anode; the potential of the second N well suspends; and a third N+ injection region is bridged between the two N wells and the P-type substrate. A triggering voltage value is reduced by bridging the third N+ injection region between the first N well and the P-type substrate, and a maintaining voltage value is increased by adding the second N well which has the suspending potential into the P-type substrate, so that the aim of a low-triggering and high-maintaining voltage is achieved. Moreover, the thyristor device is simple in structure, high in layout efficiency of unit area, uniform in current, good in robustness, and stable and reliable.
Description
Technical field
The invention belongs to the electrostatic defending field of integrated circuit, be specifically related to a kind of silicon-controlled device.
Background technology
Natural Electrostatic Discharge phenomenon constitutes serious threat to the reliability of integrated circuit.In industrial quarters, the inefficacy 30% of integrated circuit (IC) products all is owing to suffer the static discharge phenomenon caused, and more and more littler process, and thinner gate oxide thickness all makes integrated circuit be subjected to the probability that static discharge destroys to be increased greatly.Therefore, the reliability of improving integrated circuit electrostatic discharge protection has very important effect to the rate of finished products that improves product.
The pattern of static discharge phenomenon is divided into four kinds usually: HBM (human body discharge mode), MM (machine discharge mode), CDM (assembly charging and discharging pattern) and electric field induction pattern (FIM).And the most common two kinds of static discharge patterns that also are the industrial quarters product must pass through are HBM and MM.When static discharge took place, electric charge flowed into and flows out from the another pin from a pin of chip usually, and the electric current that this moment, electrostatic charge produced is usually up to several amperes, and the voltage that produces at the electric charge input pin is up to several volts even tens volts.Can cause the damage of inside chip if bigger ESD electric current flows into inside chip, simultaneously, the high pressure that produces at input pin also can cause internal components generation grid oxygen punch-through, thereby causes circuit malfunction.Therefore, damaged by ESD, all will carry out effective ESD protection, the ESD electric current is released each pin of chip in order to prevent inside chip.
Under the normal operating conditions of integrated circuit, electrostatic discharge protection component is to be in closing state, can not influence the current potential on the input and output pin.And externally static pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, emits electrostatic induced current rapidly.
ESD protection design not only will be protected inside chip, also will guarantee not the operate as normal of chip is exerted an influence.The voltage power supply scope that requires the ESD device in actual design is between normal working voltage and inner core sheet grating oxygen puncture voltage, be keeping voltage and will being higher than normal working voltage of ESD device, and the cut-in voltage of ESD device will be lower than the grid oxygen puncture voltage of inside chip, as shown in Figure 1.If the cut-in voltage of ESD device is higher than inner core sheet grating oxygen puncture voltage, then can not play the effect of protection; If the voltage of keeping of ESD device is lower than normal working voltage, then latch-up can take place, shown in Fig. 1 dotted portion.
In the evolution of ESD protection, diode, GGNMOS (NMOS of grid ground connection), SCR devices such as (controllable silicons) are used as the ESD protective unit usually.
Controllable silicon commonly used has the N trap on the P type substrate as shown in Figure 2, and two injection regions are arranged in the N trap, is respectively N+ injection region and P+ injection region.Same, a N+ injection region and P+ injection region are not arranged yet doing on the P type substrate of N trap.Wherein the N+ injection region of N trap is arranged on away from N trap and the P type substrate end that has a common boundary, and the P+ injection region of N trap is arranged near the end of N trap with P type substrate boundary; The P+ injection region of P type substrate is arranged on away from an end that has a common boundary, and the N+ injection region of P type substrate is arranged near an end that has a common boundary.The shallow trench isolation of use between all injection regions (Shallow TrenchIsolation, STI).The N+ injection region and the P+ injection region of N trap connect electrical anode, and the N+ injection region and the P+ injection region of P trap connect electrical cathode.
Fig. 3 is and the corresponding circuit theory diagrams of this SCR structure.When the ESD signal appears in anode, bigger voltage can cause the PN junction avalanche breakdown of N trap and P type substrate, the dead resistance Rpsub that the avalanche current that produces flows through P type substrate produces pressure drop, when the cut-in voltage of this pressure drop greater than the parasitic NPN triode, the NPN parasitic triode is opened, because positive feedback is also opened the PNP parasitic triode, whole silicon-controlled device is switched on simultaneously, the ESD electric current that begins to release is clamped down on the controllable silicon both end voltage simultaneously than electronegative potential.Because the concentration of N trap and P type substrate is all very low, avalanche breakdown voltage is very high between can causing occurring in, and is higher than the inner grid oxygen puncture voltage that will protect chip.
On the other hand because the positive feedback effect of parasitic NPN triode and parasitic PNP triode, make after the controlled unlatching to keep voltage very low, often be lower than the circuit normal working voltage, latch-up takes place easily, influence the operate as normal of circuit.A kind of method of normal employing is to reach the purpose that voltage is kept in raising by increasing one of them parasitic triode base width.Concrete, for example increase among Fig. 2 in the P type substrate N+ injection region to the lateral separation of N trap.But the side effect that this method is brought is to have increased the chip area of whole silicon-controlled device and reduced silicon controlled ESD robustness.
Therefore, in the prior art, the controllable silicon trigger voltage is generally higher, can not effectively protect for 5V and following operating voltage; To keep voltage low excessively again usually for this silicon controlled simultaneously, and latch-up takes place easily, influences the operate as normal of chip.So need reduce trigger voltage to controllable silicon commonly used, raise and keep the improvement of voltage.
Summary of the invention
The invention provides a kind of silicon-controlled device, it is simple in structure, trigger voltage is low, keep the voltage height, and can in respective range, adjust trigger voltage and keep voltage to meet the requirement of physical circuit protection, be a kind of reliable electrostatic discharge protection component.
A kind of silicon-controlled device comprises P type substrate, is horizontally arranged with the N trap and floating the 2nd empty N trap of current potential that are connected with electrical anode on the described P type substrate, and a described N trap is not connected with the 2nd N trap;
Point to the direction of the 2nd N trap by a N trap, on a described N trap, the 2nd N trap and P type substrate, do not establish in the zone of N trap, along laterally being provided with a N+ injection region, a P+ injection region, the 3rd N+ injection region, the 2nd N+ injection region and the 2nd P+ injection region successively;
Wherein, a described N+ injection region and a P+ injection region are arranged in the N trap, the two ends of described the 3rd N+ injection region are crossed on respectively on a N trap and the 2nd N trap, and described the 2nd N+ injection region and the 2nd P+ injection region are arranged on the zone of not establishing the N trap on the P type substrate;
Electrical anode is all inserted in a described P+ injection region and a N+ injection region, and electrical cathode is all inserted in described the 2nd P+ injection region and the 2nd N+ injection region, and what electrode described the 3rd N+ injection region does not then take over;
Isolate by the first shallow trench between a described N+ injection region and the P+ injection region, isolate by the second shallow trench between a described P+ injection region and the 3rd N+ injection region, isolate by the 4th shallow trench between described the 3rd N+ injection region and the 2nd N+ injection region, isolate by the 3rd shallow trench between described the 2nd N+ injection region and the 2nd P+ injection region.
Floating the 2nd empty N trap of described current potential is meant that described the 2nd N trap does not link to each other with any electricity electrode.
Distance between a preferred described N trap and the 2nd N trap is 1～4 micron, satisfying under the condition of design rule, under the prerequisite of convenient processing, should select short horizontal base width, to guarantee the ESD robustness that device is basic and the function of low trigger voltage of the present invention and high maintenance voltage as far as possible.
Among the present invention, the two ends of described the 3rd N+ injection region lay respectively on a described N trap and described the 2nd N trap, because a described N trap is not connected with described the 2nd N trap, described the 3rd N+ injection region itself is across the zone (zone of not establishing the N trap on the P type substrate) between a described N trap and described the 2nd N trap, therefore, we can say the described N trap of described the 3rd N+ injection region cross-over connection simultaneously, described the 2nd N trap and described P type substrate.
Among the present invention,, utilize high concentration N+ injection region to increase between a N trap and the P type substrate electric field strength when puncturing, reducing puncture voltage, thereby realize the reduction of trigger voltage by cross-over connection the 3rd N+ injection region between a N trap and P type substrate; By floating the 2nd empty N trap of current potential is set in the P type substrate, increase the base length of embedded NPN triode in the controllable silicon in the vertical, realize keeping the increase of magnitude of voltage, thereby reach the purpose of a low triggering, high maintenance voltage.Simultaneously, owing to take to be different from the structure of conventional increase base width, simple increase lateral length become to be increased longitudinal length simultaneously and reaches the purpose that reduces chip area.Silicon-controlled device of the present invention is simple in structure, and electric current is even, and the device robustness is good, and is reliable and stable.
Silicon-controlled device of the present invention is compared common SCR structure and is relied on N trap/P trap PN junction avalanche breakdown can realize lower puncture voltage; Compare that common SCR is simple to be increased horizontal base width and improve and keep voltage and more save chip area.
Description of drawings
Fig. 1 is the voltage range schematic diagram that the ESD protective device need satisfy;
Fig. 2 is the profile of the controllable silicon SCR electrostatic discharge protection component of prior art;
Fig. 3 is the equivalent circuit theory figure of Fig. 2;
Fig. 4 is the profile of silicon-controlled device of the present invention;
Fig. 5 is the vertical view of Fig. 4.
Embodiment
Describe the present invention in detail below in conjunction with embodiment and accompanying drawing, but the present invention is not limited to this.
As shown in Figure 4 and Figure 5, a kind of silicon-controlled device comprises P type substrate 41, is horizontally arranged with the N trap 42 and floating empty the 2nd N trap 43, the one N traps 42 of current potential that are connected with electrical anode on the P type substrate 41 and is not connected with the 2nd N trap 43;
Point to the direction of the 2nd N trap 43 by a N trap 42, on a N trap 42, the 2nd N trap 43 and P type substrate 41, do not establish in the zone of N trap, along laterally being provided with a N+ injection region 44, a P+ injection region 45, the 3rd N+ injection region 49, the 2nd N+ injection region 46 and the 2nd P+ injection region 47 successively;
Wherein, the one a N+ injection region 44 and a P+ injection region 45 are arranged in the N trap 42, the two ends of the 3rd N+ injection region 49 are crossed on respectively on a N trap 42 and the 2nd N trap 43, and the 2nd N+ injection region 46 and the 2nd P+ injection region 47 are arranged on the zone of not establishing the N trap on the P type substrate 41;
Electrical anode is all inserted in the one a P+ injection region 45 and a N+ injection region 44, and electrical cathode is all inserted in the 2nd P+ injection region 47 and the 2nd N+ injection region 46, and what electrode 49 of the 3rd N+ injection regions do not take over;
Isolate (shallow trench isolation by the first shallow trench between the one a N+ injection region 44 and the P+ injection region 45, STI) 48a isolates, isolating 48b by the second shallow trench between the one P+ injection region 45 and the 3rd N+ injection region 49 isolates, isolate 48d by the 4th shallow trench between the 3rd N+ injection region 49 and the 2nd N+ injection region 46 and isolate, isolate 48c by the 3rd shallow trench between the 2nd N+ injection region 46 and the 2nd P+ injection region 47 and isolate.
Floating the 2nd empty N trap 43 of current potential is meant that the 2nd N trap 43 does not link to each other with any electricity electrode.
In the above-mentioned silicon-controlled device, the two ends of the 3rd N+ injection region 49 lay respectively on a N trap 42 and the 2nd N trap 43, because a N trap 42 is not connected with the 2nd N trap 43, therefore the 3rd N+ injection region 49 is own across the zone between a N trap 42 and the 2nd N trap 43 (zone of not establishing the N trap on the P type substrate), therefore, we can say the 3rd N+ injection region 49 cross-over connections simultaneously the one N trap 42, the 2nd N trap 43 and P type substrate 41.
In order to satisfy under the condition of design rule, conveniently processing should be selected short horizontal base width as far as possible, realizes the purpose of low triggering, high maintenance voltage, and the distance that can establish between a N trap 42 and the 2nd N trap 43 is 1～4 micron.
Above-mentioned P type substrate, N trap, N+ injection region, P+ injection region structure all adopt existing standard CMOS integrated circuit fabrication process to realize.
The one N+ injection region 44 is connected as electrical anode with a P+ injection region 45 usefulness metal wires.The 2nd N+ injection region 46 and the 2nd P+ injection region 47 are as electrical cathode.When the ESD signal appears in anode, bigger voltage can cause the PN junction avalanche breakdown of a N trap 42 and P type substrate 41, the dead resistance Rpsub that the avalanche current that produces flows through P type substrate 41 produces pressure drop, when the cut-in voltage of this pressure drop greater than the parasitic NPN triode, the NPN parasitic triode is opened, because positive feedback is also opened the PNP parasitic triode, whole silicon-controlled device is switched on simultaneously, the ESD electric current that begins to release is clamped down on the controllable silicon both end voltage simultaneously than electronegative potential.
In the above-mentioned silicon-controlled device, be provided with the 3rd N+ injection region 49 at a N trap 42 that connects anode and the intersection of P type substrate 41, therefore above-mentioned silicon-controlled device can be opened under low voltage.Because a N trap 42 is all very low with the concentration of P type substrate 41; the avalanche breakdown voltage that occurs between a N trap 42 and the P type substrate 41 is very high; be higher than the inner grid oxygen puncture voltage that will protect chip; and after the intersection of a N trap 42 and P type substrate 41 increases by the 3rd N+ injection region 49; the adding of high-dopant concentration the 3rd N+ injection region 49; increase the electric field strength when puncturing between a N trap 42 and the P type substrate 41, reduced puncture voltage, thereby realized the reduction of trigger voltage.
On the other hand, because the base of NPN pipe is provided with floating the 2nd empty N trap 43 of current potential on P type substrate 41, play block electrons and the effect that prolongs vertical base width, the base current path is shown in the curve of band arrow among Fig. 4, thus, not only utilized the lateral length of device, the vertical degree of depth that has also made full use of device comprehensively increases base width, thereby improve the area domain efficient of unit, also realized keeping simultaneously the increase of magnitude of voltage.
Claims (2)
1. a silicon-controlled device comprises P type substrate (41), it is characterized in that:
Be horizontally arranged with the N trap (42) and floating the 2nd empty N trap (43) of current potential that are connected with electrical anode on the described P type substrate (41), a described N trap (42) is not connected with the 2nd N trap (43);
Point to the direction of the 2nd N trap (43) by a N trap (42), on a described N trap (42), the 2nd N trap (43) and P type substrate (41), do not establish in the zone of N trap, along laterally being provided with a N+ injection region (44), a P+ injection region (45), the 3rd N+ injection region (49), the 2nd N+ injection region (46) and the 2nd P+ injection region (47) successively;
Wherein, a described N+ injection region (44) and a P+ injection region (45) are arranged in the N trap (42), the two ends of described the 3rd N+ injection region (49) are crossed on respectively on a N trap (42) and the 2nd N trap (43), and described the 2nd N+ injection region (46) and the 2nd P+ injection region (47) are arranged on the zone of not establishing the N trap on the P type substrate (41);
Electrical anode is all inserted in a described P+ injection region (45) and a N+ injection region (44), and electrical cathode is all inserted in described the 2nd P+ injection region (47) and the 2nd N+ injection region (46), and what electrode described the 3rd N+ injection region (49) does not then take over;
Isolating (48a) by the first shallow trench between a described N+ injection region (44) and the P+ injection region (45) isolates, isolating (48b) by the second shallow trench between a described P+ injection region (45) and the 3rd N+ injection region (49) isolates, isolate (48d) by the 4th shallow trench between described the 3rd N+ injection region (49) and the 2nd N+ injection region (46) and isolate, isolate (48c) by the 3rd shallow trench between described the 2nd N+ injection region (46) and the 2nd P+ injection region (47) and isolate.
2. silicon-controlled device as claimed in claim 1 is characterized in that: the distance between a described N trap (42) and the 2nd N trap (43) is 1～4 micron.
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| CN201010615666XA CN102142440B (en) | 2010-12-30 | 2010-12-30 | Thyristor device |
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| CN201010615666XA CN102142440B (en) | 2010-12-30 | 2010-12-30 | Thyristor device |
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| CN102142440B CN102142440B (en) | 2012-08-22 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108461491A (en) * | 2018-03-21 | 2018-08-28 | 湖南静芯微电子技术有限公司 | A kind of low triggering bidirectional thyristor electrostatic protection device of high maintenance voltage |
| CN108807372A (en) * | 2018-06-07 | 2018-11-13 | 湘潭大学 | A kind of low pressure triggering high maintenance voltage silicon controlled rectifier (SCR) Electro-static Driven Comb device |
| CN109841609A (en) * | 2017-11-24 | 2019-06-04 | 力智电子股份有限公司 | Transient Voltage Suppressor |
| CN109904215A (en) * | 2018-12-29 | 2019-06-18 | 北京大学 | A kind of DTSCR device |
| CN109935582A (en) * | 2019-02-25 | 2019-06-25 | 中国科学院微电子研究所 | Bidirectional triode thyristor ESD-protection structure and soi structure |
| CN109962098A (en) * | 2019-02-25 | 2019-07-02 | 中国科学院微电子研究所 | Bidirectional triode thyristor ESD-protection structure and soi structure |
| CN112018106A (en) * | 2020-09-28 | 2020-12-01 | 上海华虹宏力半导体制造有限公司 | High-voltage electrostatic protection structure |
| CN113299640A (en) * | 2021-04-27 | 2021-08-24 | 西安理工大学 | ESD protector based on SCR in SiGe technology |
| CN117316947A (en) * | 2023-11-27 | 2023-12-29 | 厦门科塔电子有限公司 | ESD protection device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1383207A (en) * | 2001-04-24 | 2002-12-04 | 华邦电子股份有限公司 | High-current triggered electrostatic discharge protector |
| TW582107B (en) * | 2000-03-30 | 2004-04-01 | Winbond Electronics Corp | SCR-type electrostatic discharge protection circuit |
| CN101174629A (en) * | 2006-10-30 | 2008-05-07 | 上海华虹Nec电子有限公司 | Controlled silicon structure used for CMOS electrostatic discharge protection |
| CN101286510A (en) * | 2007-04-11 | 2008-10-15 | 快捷半导体有限公司 | Un-assisted, low-trigger and high-holding voltage SCR |
| CN101442039A (en) * | 2007-11-22 | 2009-05-27 | 上海华虹Nec电子有限公司 | Method for reducing trigger voltage of silicon control rectifier |
-
2010
- 2010-12-30 CN CN201010615666XA patent/CN102142440B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW582107B (en) * | 2000-03-30 | 2004-04-01 | Winbond Electronics Corp | SCR-type electrostatic discharge protection circuit |
| CN1383207A (en) * | 2001-04-24 | 2002-12-04 | 华邦电子股份有限公司 | High-current triggered electrostatic discharge protector |
| CN101174629A (en) * | 2006-10-30 | 2008-05-07 | 上海华虹Nec电子有限公司 | Controlled silicon structure used for CMOS electrostatic discharge protection |
| CN101286510A (en) * | 2007-04-11 | 2008-10-15 | 快捷半导体有限公司 | Un-assisted, low-trigger and high-holding voltage SCR |
| CN101442039A (en) * | 2007-11-22 | 2009-05-27 | 上海华虹Nec电子有限公司 | Method for reducing trigger voltage of silicon control rectifier |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109841609A (en) * | 2017-11-24 | 2019-06-04 | 力智电子股份有限公司 | Transient Voltage Suppressor |
| CN108461491A (en) * | 2018-03-21 | 2018-08-28 | 湖南静芯微电子技术有限公司 | A kind of low triggering bidirectional thyristor electrostatic protection device of high maintenance voltage |
| CN108461491B (en) * | 2018-03-21 | 2023-09-29 | 湖南静芯微电子技术有限公司 | Low-trigger bidirectional silicon controlled electrostatic protection device with high maintenance voltage |
| CN108807372B (en) * | 2018-06-07 | 2019-12-17 | 湘潭大学 | Low-voltage trigger high-holding-voltage silicon controlled rectifier electrostatic discharge device |
| CN108807372A (en) * | 2018-06-07 | 2018-11-13 | 湘潭大学 | A kind of low pressure triggering high maintenance voltage silicon controlled rectifier (SCR) Electro-static Driven Comb device |
| CN109904215A (en) * | 2018-12-29 | 2019-06-18 | 北京大学 | A kind of DTSCR device |
| CN109962098A (en) * | 2019-02-25 | 2019-07-02 | 中国科学院微电子研究所 | Bidirectional triode thyristor ESD-protection structure and soi structure |
| CN109935582B (en) * | 2019-02-25 | 2021-04-06 | 中国科学院微电子研究所 | Bidirectional thyristor electrostatic discharge protection structure and SOI structure |
| CN109935582A (en) * | 2019-02-25 | 2019-06-25 | 中国科学院微电子研究所 | Bidirectional triode thyristor ESD-protection structure and soi structure |
| CN112018106A (en) * | 2020-09-28 | 2020-12-01 | 上海华虹宏力半导体制造有限公司 | High-voltage electrostatic protection structure |
| CN112018106B (en) * | 2020-09-28 | 2024-03-19 | 上海华虹宏力半导体制造有限公司 | High-voltage electrostatic protection structure |
| CN113299640A (en) * | 2021-04-27 | 2021-08-24 | 西安理工大学 | ESD protector based on SCR in SiGe technology |
| CN117316947A (en) * | 2023-11-27 | 2023-12-29 | 厦门科塔电子有限公司 | ESD protection device |
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