CN113299640A - ESD protector based on SCR in SiGe technology - Google Patents
ESD protector based on SCR in SiGe technology Download PDFInfo
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- CN113299640A CN113299640A CN202110461415.9A CN202110461415A CN113299640A CN 113299640 A CN113299640 A CN 113299640A CN 202110461415 A CN202110461415 A CN 202110461415A CN 113299640 A CN113299640 A CN 113299640A
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 51
- 230000001012 protector Effects 0.000 title claims abstract description 15
- 238000005516 engineering process Methods 0.000 title description 9
- 238000000034 method Methods 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims description 13
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 238000002347 injection Methods 0.000 abstract description 5
- 239000007924 injection Substances 0.000 abstract description 5
- 230000009024 positive feedback mechanism Effects 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 10
- 230000001681 protective effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thyristors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to an ESD protector based on SCR in SiGe process, which comprises a substrate, an n-well region, a p-well region, an isolation groove, an n-well contact n + region, a SiGe _ p + region, an n + region and a p-well contact p + region which are arranged from bottom to top in sequence, wherein an energy band at the interface of a SiGe _ p + layer and the n-well region has an obvious bulge, so that the injection of current carriers is blocked, the gain of a parasitic PNP tube is reduced, and the positive feedback mechanism in the SCR is weakened.
Description
Technical Field
The invention belongs to the technical field of microelectronics and solid electronics, and particularly relates to an ESD protector based on SCR in a SiGe process.
Background
Electrostatic discharge (ESD) is a common natural phenomenon, and in the field of integrated circuits, ESD is one of the main causes of failure and reliability reduction of electronic products. With the rapid development of semiconductor integrated circuits, the feature size of the device is continuously reduced, and the risk of electrostatic damage is increased, so how to effectively perform electrostatic protection becomes more and more important.
In recent years, SiGe (germanium silicon) heterojunction technology can provide a solution for high frequency devices and has better compatibility with common Si technology, so that SiGe heterojunction technology is widely applied in the field of radio frequency microwave, and meanwhile, the problem of electrostatic protection of chips under SiGe (germanium silicon) technology is also more and more focused. Silicon Controlled Rectifiers (SCR) are highly appreciated in the field of electrostatic protection due to their excellent current leakage per unit area, but when SCR (silicon controlled rectifiers) of the conventional structure are used as ESD (electrostatic protection) devices, internal parasitic NPN (NPN bipolar transistor) and PNP (PNP bipolar transistor) provide base current to each other to form a strong positive feedback effect when turned on, resulting in an obvious hysteresis (snapback) phenomenon after triggering, and thus its holding voltage is low, which easily causes latch-up (latch up) effect. In order to better satisfy the requirement of an ESD (electrostatic discharge protection) design window under a SiGe (germanium-silicon) process, a conventional SCR (silicon controlled rectifier) needs to be improved to increase a holding voltage and avoid a latch-up effect. Therefore, it is a significant problem to improve the conventional SCR (silicon controlled rectifier) device by using the band engineering technique under the SiGe (silicon germanium) process, and further develop its advantages in the electrostatic protection field.
Disclosure of Invention
To overcome the above-mentioned deficiencies of the prior art, it is an object of the present invention to provide an SCR-based ESD protector in SiGe technology, which can significantly improve the holding voltage of the SCR, thereby better meeting the ESD design window.
In order to achieve the purpose, the ESD protector based on SCR in the SiGe process comprises a substrate (1), an n-well region (2), a p-well region (3), an isolation groove (4), an n-well contact n + region (5), a SiGe _ p + region (6), an n + region (7) and a p-well contact p + region (8) which are sequentially arranged from bottom to top; the n well region (2) and the p well region (3) are arranged on the upper part of the substrate (1) in parallel; an isolation groove (4), an n-well contact n + region (5) and a SiGe _ p + region (6) are arranged on the upper portion of the n-well region (2) from left to right; an n + region (7) and a p-well contact p + region (8) are arranged on the upper part of the p-well region (3) from left to right.
The n well region (2) is composed of Si with the thickness of 0.8-0.95 μm, the doping type is As ions, and the doping concentration is 1 multiplied by 1017cm-3。
The p well region (3) is composed of Si with the thickness of 0.8-0.95 μm, the doping type is B ion, and the doping concentration is 1 multiplied by 1017cm-3。
The isolation groove (4) is made of SiO2The width is 0.6-1 μm, and the thickness is 0.2 μm.
The n-well contact n + region (5) and the n + region (7) are made of Si, the width is 1 mu m, the thickness is 0.05 mu m, the doping type is As ions, and the doping concentration is 1 multiplied by 1020cm-3。
The SiGe _ p + region (6) is a SiGe layer with the width of 1 μm and the thickness of 0.05 μm, the doping type is B ions, and the doping concentration is 1 multiplied by 1020cm-3。
The p-well contact p + region 8 is made of Si, the width is 1 mu m, the thickness is 0.05 mu m, the doping type is B ions, and the doping concentration is 1 multiplied by 1020cm-3。
The invention has the beneficial effects that:
the working mechanism of the traditional ESD protection device based on SCR is as follows: when ESD impacts, the initial voltage is small, reverse leakage current flowing through a reverse biased pn junction of a well region is small, an SCR is in a closed state, avalanche breakdown occurs to the reverse biased pn junction of the well region along with the increase of external voltage, carriers generate an avalanche multiplication effect, holes flow into a cathode through a p-well, electrons flow into an anode through an n-well, and therefore voltage drop generated in the well region enables parasitic PNP and NPN to be sequentially started to form a positive feedback effect, the positive feedback mechanism enhances the conductance modulation effect of the whole device, and the voltage is enabled to be delayed to a lower position, namely, the voltage is maintained. Therefore, the key point of improving the maintaining voltage is to inhibit the influence caused by the positive feedback effect, the p + region of the traditional SCR is replaced by a SiGe _ p + layer in the novel ESD protective device based on the SCR under the SiGe process, the characteristic of narrow SiGe forbidden band width is utilized, a potential barrier peak is formed on a junction interface, the carrier injection is inhibited, the gain of parasitic pnp is reduced, the conductance modulation effect is inhibited, and the effect of improving the maintaining voltage is achieved.
The invention reasonably utilizes the energy band engineering technology without increasing the process difficulty, and obviously improves the holding voltage of the traditional SCR device.
Drawings
Fig. 1 is a schematic structural diagram of a novel ESD protection device based on SCR under SiGe process according to the present invention.
Fig. 2 is a schematic diagram of a conventional SCR-based ESD protection device structure.
Fig. 3 is an energy band diagram of the interface of SiGe _ p + region of the novel ESD protection device based on SCR under SiGe process of the present invention.
Fig. 4 is a conventional SCR-based ESD protection device p + region boundary band diagram.
Fig. 5 is a distribution diagram of the current density at the sustain point of the novel ESD protection device based on SCR under SiGe process of the present invention.
Fig. 6 is a conventional SCR-based ESD protection device sustain point current density distribution graph.
Fig. 7 is a graph comparing quasi-static I-V characteristic simulation curves of the novel SCR-based ESD protection device under the SiGe process of the present invention and the conventional SCR-based ESD protection device.
In the figure: the device comprises a 1-substrate, a 2-n well region, a 3-p well region, a 4-isolation groove, a 5-n well contact n + region, a 6-SiGe _ p + region, a 7-n + region and an 8-p well contact p + region.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the ESD protector based on SCR in the SiGe process includes a substrate 1, an n-well region 2, a p-well region 3, an isolation trench 4, an n-well contact n + region 5, a SiGe _ p + region 6, an n + region 7, and a p-well contact p + region 8, which are sequentially disposed from bottom to top; the n well region 2 and the p well region 3 are arranged on the upper part of the substrate 1 in parallel; the upper part of the n-well region 2 is provided with an isolation groove 4, an n-well contact n + region 5 and a SiGe _ p + region 6 from left to right; an n + region 7 and a p-well contact p + region 8 are arranged on the upper portion of the p-well region 3 from left to right.
The n well region 2 is composed of Si with the thickness of 0.8-0.95 μm, the doping type is As ions, and the doping concentration is 1 multiplied by 1017cm-3。
The p-well region 3 is composed of Si with a thickness of 0.8-0.95 μm, the doping type is B ion, and the doping concentration is 1 × 1017cm-3。
The isolation groove 4 is made of SiO2The width is 0.6-1 μm, and the thickness is 0.2 μm.
The n-well contact n + region 5 and the n + region 7 are made of Si, the width of the Si is 1 mu m, the thickness of the Si is 0.05 mu m, and the doping type of the Si is As ionsDoping concentration of 1X 1020cm-3。
The SiGe _ p + region 6 is a SiGe layer with a width of 1 μm and a thickness of 0.05 μm, and has a doping type of B ions and a doping concentration of 1 × 1020cm-3。
The p-well contact p + region 8 is made of Si, the width is 1 mu m, the thickness is 0.05 mu m, the doping type is B ions, and the doping concentration is 1 multiplied by 1020cm-3。
The working principle of the invention is as follows:
the working mechanism of the novel ESD protective device based on the SCR under the SiGe process is consistent with that of the traditional ESD protective device based on the SCR, and the main difference is that a p + region is replaced by a SiGe _ p + layer, and parasitic NPN gain is reduced by utilizing an energy band engineering technology; in an ESD protector, in order to better meet a design window, the improvement of a maintaining voltage is a large key point, the maintaining voltage is a hysteresis voltage point, and the hysteresis of SCR is caused by that a positive feedback mechanism of parasitic NPN and PNP enhances a conductance modulation effect under large injection, so that the voltage is hysteresis to a lower point; the p + region is used as an emitting region of a parasitic PNP tube in the SCR, the PNP tube has larger injection efficiency due to higher doping concentration, so that the positive feedback mechanism in the SCR is greatly influenced. In order to embody the advantages of the invention, parameters such as doping distribution, contact area, size and the like of two devices are set to be completely consistent, and basic structures are respectively shown in fig. 1 and fig. 2.
The electrical characteristics of the two structures are compared based on the simulation of Sentaurus TCAD software, and the Ge component of the SiGe _ p + layer in the simulation is linearly distributed from top to bottom and is 20-0%. With reference to fig. 3 and 4, compared with the conventional ESD protection device based on the SCR, the energy band of the novel ESD protection device based on the SCR under the SiGe process of the present invention at the interface between the SiGe _ p + layer and the n well region has an obvious protrusion, which hinders the injection of carriers, thereby reducing the gain of the parasitic PNP transistor and weakening the positive feedback mechanism inside the SCR. With reference to fig. 5 and 6, compared with the conventional ESD protection device based on the SCR, the novel ESD protection device based on the SCR under the SiGe process of the present invention has a larger current density distribution range at the sustain point, which shows that the introduction of the SiGe _ p + layer significantly increases the current discharge capability of the device, and not only significantly improves the sustain voltage, but also has a higher sustain current. In combination with a comparison graph of quasi-static I-V characteristic simulation curves of the novel ESD protective device based on the SCR under the SiGe process and the conventional ESD protective device based on the SCR in the invention shown in FIG. 7, the novel ESD protective device based on the SCR has obvious beneficial effects, and the maintaining voltage is increased from 3.02V to 6.43V, which is increased by about 113%.
Claims (7)
- The ESD protector based on the SCR in the SiGe process is characterized by comprising a substrate (1), an n-well region (2), a p-well region (3), an isolation groove (4), an n-well contact n + region (5), a SiGe _ p + region (6), an n + region (7) and a p-well contact p + region (8) which are sequentially arranged from bottom to top; the n well region (2) and the p well region (3) are arranged on the upper part of the substrate (1) in parallel; an isolation groove (4), an n-well contact n + region (5) and a SiGe _ p + region (6) are arranged on the upper portion of the n-well region (2) from left to right; an n + region (7) and a p-well contact p + region (8) are arranged on the upper part of the p-well region (3) from left to right.
- 2. SCR-based ESD protector in SiGe process according to claim 1, wherein the n-well region (2) is composed of Si with thickness of 0.8-0.95 μm, doping type is As ion and doping concentration is 1 x 1017cm-3。
- 3. The ESD protector based on SCR in SiGe process as claimed in claim 1, wherein the p-well region (3) is composed of Si with thickness of 0.8-0.95 μm, doping type is B-ion, and doping concentration is 1 x 1017cm-3。
- 4. SCR-based ESD protector in SiGe process according to claim 1, wherein the isolation trench (4) is made of SiO2The width is 0.6-1 μm, and the thickness is 0.2 μm.
- 5. According to claim 1The ESD protector based on SCR in SiGe process is characterized in that the n-well contact n + region (5) and the n + region (7) are made of Si, the width is 1 mu m, the thickness is 0.05 mu m, the doping type is As ions, and the doping concentration is 1 x 1020cm-3。
- 6. The ESD protector based on SCR in SiGe process as claimed in claim 1, wherein the SiGe _ p + region (6) is a SiGe layer with 1 μm width and 0.05 μm thickness, and has a doping type of B ion and a doping concentration of 1 x 1020cm-3。
- 7. The ESD protector based on SCR in SiGe process as claimed in claim 1, wherein the p-well contact p + region 8 is made of Si, and has a width of 1 μm, a thickness of 0.05 μm, a doping type of B ions, and a doping concentration of 1 x 1020cm-3。
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110461415.9A CN113299640A (en) | 2021-04-27 | 2021-04-27 | ESD protector based on SCR in SiGe technology |
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| CN202110461415.9A CN113299640A (en) | 2021-04-27 | 2021-04-27 | ESD protector based on SCR in SiGe technology |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030047750A1 (en) * | 2001-09-11 | 2003-03-13 | Sarnoff Corporation | Electrostatic discharge protection silicon controlled rectifier (ESD-SCR) for silicon germanium technologies |
| US20070023866A1 (en) * | 2005-07-27 | 2007-02-01 | International Business Machines Corporation | Vertical silicon controlled rectifier electro-static discharge protection device in bi-cmos technology |
| CN101807598A (en) * | 2010-03-17 | 2010-08-18 | 浙江大学 | PNPNP type triac |
| CN102142440A (en) * | 2010-12-30 | 2011-08-03 | 浙江大学 | Thyristor device |
| US8377754B1 (en) * | 2011-10-10 | 2013-02-19 | International Business Machines Corporation | Stress enhanced junction engineering for latchup SCR |
| US20130208379A1 (en) * | 2012-02-09 | 2013-08-15 | United Microelectronics Corporation | Electrostatic discharge protection apparatus |
| US20130285112A1 (en) * | 2012-04-30 | 2013-10-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | High-trigger current scr |
-
2021
- 2021-04-27 CN CN202110461415.9A patent/CN113299640A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030047750A1 (en) * | 2001-09-11 | 2003-03-13 | Sarnoff Corporation | Electrostatic discharge protection silicon controlled rectifier (ESD-SCR) for silicon germanium technologies |
| US20070023866A1 (en) * | 2005-07-27 | 2007-02-01 | International Business Machines Corporation | Vertical silicon controlled rectifier electro-static discharge protection device in bi-cmos technology |
| CN101807598A (en) * | 2010-03-17 | 2010-08-18 | 浙江大学 | PNPNP type triac |
| CN102142440A (en) * | 2010-12-30 | 2011-08-03 | 浙江大学 | Thyristor device |
| US8377754B1 (en) * | 2011-10-10 | 2013-02-19 | International Business Machines Corporation | Stress enhanced junction engineering for latchup SCR |
| US20130208379A1 (en) * | 2012-02-09 | 2013-08-15 | United Microelectronics Corporation | Electrostatic discharge protection apparatus |
| US20130285112A1 (en) * | 2012-04-30 | 2013-10-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | High-trigger current scr |
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