CN112466937B - SOI process silicon controlled electrostatic discharge protection structure with adjustable maintenance voltage - Google Patents
SOI process silicon controlled electrostatic discharge protection structure with adjustable maintenance voltage Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 38
- 239000010703 silicon Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000008569 process Effects 0.000 title claims abstract description 16
- 238000012423 maintenance Methods 0.000 title claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000009413 insulation Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000009024 positive feedback mechanism Effects 0.000 description 4
- 238000007599 discharging Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention relates to the technical field of silicon controlled rectifier electrostatic protection, in particular to a silicon controlled rectifier electrostatic discharge protection structure of an SOI process with adjustable maintenance voltage. Comprising the following steps: the device comprises polysilicon, an N-type well region, a P-type well region, a silicon film layer, an oxygen-buried layer and a silicon substrate layer which are stacked; n-type well regions and P-type well regions are adjacently arranged in the silicon film layer along the left-right direction; the top of the N-type well region and the top of the P-type well region are contacted with the bottom of the polysilicon; the upper part of the N-type well region is sequentially provided with a first N-type heavily doped region, a first P-type heavily doped region and a super shallow trench isolation region from left to right; the upper part of the P-type well region is sequentially provided with a second N-type heavily doped region and a second P-type heavily doped region from left to right. According to the invention, the ultra-shallow trench isolation region is arranged above the N-type well region, and the equivalent resistance on the path from the positive electrode to the negative electrode in the SCR is increased by utilizing the insulating capability of the ultra-shallow trench isolation region, so that the purpose of improving the maintaining voltage of the SCR is realized, and the leakage risk of the SCR is effectively reduced.
Description
Technical Field
The invention relates to the technical field of silicon controlled rectifier electrostatic protection, in particular to a silicon controlled rectifier electrostatic discharge protection structure of an SOI process with adjustable maintenance voltage.
Background
Static electricity exists in the natural world at all times, and when static charges accumulated in the external environment of the chip or the inside of the chip flow into or flow out of the inside of the chip through pins of the chip, current (peak value can reach several amperes) or voltage generated instantaneously damages an integrated circuit, so that the function of the chip is disabled. The effective ESD (electro STATIC DISCHARGE ) enables the protection device to rapidly start and discharge ampere level current in an electrostatic event, and meanwhile, the voltage between the pinch port or the power supply/ground is below the breakdown voltage of the core circuit, so that the purpose of protecting the core circuit from electrostatic damage is achieved, and the ESD protection device must be in a closed state when the circuit works normally, so that the function of the circuit is not affected.
With the development of the semiconductor industry, SOI (Silicon-On-Insulator) technology is becoming mature, and SOI devices are widely used in various fields. Due to the inherent limitations of SOI technology itself, SOI electrostatic protection has been a significant part of the production applications of SOI devices. With the reduction of critical dimensions, the core circuit can work with smaller and smaller voltage until the process of 0.18 μm 3.3V, the NMOS device is also suitable for ESD protection design, but after the process of 0.18 μm 1.8V or 0.13 μm or even nanometer, the starting voltage characteristic of the NMOS device can not meet the requirement of the ESD protection design.
In order to obtain a sufficiently low turn-on voltage device, SCR (Silicon Controlled Rectifier, silicon controlled device) thyristors are currently used in large numbers for electrostatic protection of integrated circuits. The turn-on voltage of the SCR is determined by the breakdown voltage of the PN junction between the N-well and the P-well, and once one of the NPN or PNP tubes is turned on, the positive feedback mechanism of the NPN and PNP tubes can provide a latch-up maintaining current, so that the SCR operates at a lower maintaining voltage, and the latch-up effect induced by the positive feedback mechanism causes the SCR to have good antistatic ability, but also the maintaining voltage of the SCR is clamped at a lower voltage value. Therefore, the SCR is an ideal electrostatic protection device, but due to its own characteristics, the device still has imperfections such as high turn-on voltage, low sustain voltage, etc.
Therefore, how to reduce the leakage risk of SCR is a technical problem to be solved.
Disclosure of Invention
The invention aims to provide an SOI process silicon controlled electrostatic discharge protection structure with adjustable maintenance voltage so as to reduce the leakage risk of SCR.
In order to achieve the above object, an embodiment of the present invention provides an electrostatic discharge protection structure for a Silicon On Insulator (SOI) process with an adjustable holding voltage, comprising: the polysilicon, the silicon film layer, the oxygen buried layer and the silicon substrate layer are stacked;
An N-type well region and a P-type well region are arranged in the silicon film layer side by side;
The upper part of the N-type well region is provided with a first N-type heavy doping region, a first P-type heavy doping region and a super shallow trench isolation region in parallel so as to form a first blank doping region at one corner of the N-type well region, which is close to the P-type well region;
The upper part of the P-type well region is provided with a second N-type heavily doped region and a second P-type heavily doped region in parallel so as to form a second blank doped region in the P-type well region, which is close to one corner of the N-type well region;
The polysilicon covers the top end face of the first blank doping region and the top end face of the second blank doping region.
In one possible embodiment, the thickness of the N-type well region and the thickness of the P-type well region do not exceed the thickness of the silicon film layer.
In one possible embodiment, the first N-type heavily doped region and the first P-type heavily doped region are disposed adjacent to or spaced apart from each other.
In one possible embodiment, the ultra-shallow trench isolation region and the first P-type heavily doped region are disposed adjacent to or spaced apart from each other.
In one possible embodiment, the thickness of the ultra-shallow trench isolation region is less than the thickness of the silicon film layer.
In one possible embodiment, the doping concentration of the N-type well region and the doping concentration of the P-type well region are each 1e15/cm 3 to 1e18/cm 3.
In one possible embodiment, the doping concentration of the first N-type heavily doped region, the doping concentration of the second N-type heavily doped region, the doping concentration of the first P-type heavily doped region, and the doping concentration of the second P-type heavily doped region are each greater than 1e18/cm 3.
In one possible embodiment, the maintaining voltage of the electrostatic discharge protection structure of the SOI process has a positive correlation corresponding relation with the width of the ultra-shallow trench isolation region.
In one possible embodiment, the ultra-shallow trench isolation region has a width in the range of 0.1 μm to 5 μm.
In one possible embodiment, the adjustment range of the sustain voltage is 1V to 9V.
Compared with the prior art, the invention has the following advantages and beneficial effects:
According to the invention, polysilicon is manufactured on the N-type well region and the P-type well region, a certain voltage is applied to the polysilicon to provide enough trigger current to assist PN junction avalanche breakdown, so that the controllable silicon structure has lower starting voltage and rapid triggering latch-up effect, the purpose of discharging ESD current is realized, meanwhile, the ultra-shallow trench isolation region is arranged above the N-type well region, the insulation capacity of the ultra-shallow trench isolation region is utilized, the width of a conductive path is changed, the equivalent resistance on the conductive path is increased, the purpose of improving the maintaining voltage of SCR is realized, the leakage risk of SCR is effectively reduced based on the good insulation performance of the ultra-shallow trench isolation region, and in addition, the adjustment of the maintaining voltage of SCR is realized by adjusting the width of the ultra-shallow trench isolation region.
Drawings
In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the drawings that are required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present description, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an electrostatic discharge protection structure of a SOI process with adjustable holding voltage according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an equivalent circuit connection of a SCR ESD protection structure with adjustable holding voltage according to an embodiment of the present invention;
FIG. 3 is a graph showing a TLP test curve of a SCR ESD protection structure with different STI widths according to an embodiment of the present invention.
Reference numerals illustrate: 1 is polysilicon, 2 is an N-type well region, 21 is a first N-type heavily doped region, 22 is a first P-type heavily doped region, 23 is a super shallow trench isolation region, 3 is a P-type well region, 31 is a second N-type heavily doped region, 32 is a second P-type heavily doped region, 4 is a silicon film layer, 5 is an oxygen buried layer, and 6 is a silicon substrate layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and all other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the embodiments of the present invention.
The present embodiment provides a maintaining voltage adjustable electrostatic discharge protection structure for an SOI process scr, referring to fig. 1, fig. 1 is a schematic structural diagram of the structure, and specifically includes:
The semiconductor device comprises polysilicon 1, an N-type well region 2, a first N-type heavily doped region 21, a first P-type heavily doped region 22, a super shallow trench isolation region 23, a P-type well region 3, a second N-type heavily doped region 31 and a second P-type heavily doped region 32, a silicon film layer 4, a buried oxide layer 5 and a silicon substrate layer 6.
Specifically, the polysilicon 1, the silicon film layer 4, the oxygen buried layer 5 and the silicon substrate layer 6 are stacked from top to bottom.
The N-type well region 2 and the P-type well region 3 are arranged in the silicon film layer 4 side by side along the left-right direction, and the two well regions can be arranged adjacently in a contact manner or can be arranged at intervals in a non-contact manner. Specifically, the thickness of the N-type well region 2 and the thickness of the P-type well region 3 do not exceed the thickness of the silicon film layer 4, and the doping concentration range of the N-type well region 2 and the doping concentration range of the P-type well region 3 are 1e15/cm 3 to 1e18/cm 3.
The top of the N-type well region 2 and the top end face of the P-type well region 3 both contact the bottom of the polysilicon 1. The upper part of the N-type well region 2 is provided with a first N-type heavily doped region 21, a first P-type heavily doped region 22 and a super shallow trench isolation region 23 side by side from left to right so as to form a first blank doped region in the N-type well region 2, which is close to one corner of the P-type well region 3; the upper portion of the P-type well region 3 is provided with a second N-type heavily doped region 31 and a second P-type heavily doped region 32 in sequence from left to right, so as to form a second blank doped region in the P-type well region 3 near a corner of the N-type well region 2.
The top of the first N-type heavily doped region 21, the top of the first P-type heavily doped region 22 and the top of the ultra-shallow trench isolation region 23 are all flush with the top of the N-type well region 2, the top of the second N-type heavily doped region 31 and the top of the second P-type heavily doped region 32 are all flush with the top of the P-type well region 3, the polysilicon 1 is arranged on the top end surfaces of the N-type well region 2 and the P-type well region 3, the polysilicon 1 covers the top end surfaces of the first blank doped region and the top end surfaces of the second blank doped region, the bottom surfaces of the polysilicon 1 contact part of the top end surfaces of the N-type well region 2 and the P-type well region 3, but do not cover the top of the ultra-shallow trench isolation region 23, and the bottom of the polysilicon 1 specifically comprises a first sub-region and a second sub-region; the first sub-region contacts the top of the N-type well region 2; the second sub-region contacts the top of the P-type well region 3. The top of the first N-type heavily doped region 21, the top of the first P-type heavily doped region 22 and the top of the ultra-shallow trench isolation region 23 are not in contact with the bottom of the polysilicon 1, while the top of the second N-type heavily doped region 31 and the top of the second P-type heavily doped region 32 are not in contact with the bottom of the polysilicon 1. The doping concentration of the first N-type heavily doped region 21, the doping concentration of the second N-type heavily doped region 31, the doping concentration of the first P-type heavily doped region 22 and the doping concentration of the second P-type heavily doped region 32 are all greater than 1e18/cm 3.
In the above structure, the first N-type heavily doped region 21 and the first P-type heavily doped region 22 may be disposed adjacently in contact, or may be disposed at intervals without contact; the thickness of the ultra-shallow trench isolation region 23 is smaller than that of the silicon film layer 4; meanwhile, the ultra-shallow trench isolation region 23 and the first P-type heavily doped region 22 can be adjacently arranged in a contact manner or can be arranged in a non-contact manner at intervals.
In this embodiment, the polysilicon 1 is fabricated on the N-type well region 2 and the P-type well region 3, and a certain voltage is applied to the polysilicon 1 to provide a trigger current large enough, so that the thyristor structure has a lower turn-on voltage, and a latch-up effect is triggered rapidly, thereby achieving the purpose of discharging the ESD current. In this process, the electrode led out from the first P-type heavily doped region 22 corresponds to the positive electrode of the device, the electrode led out from the second N-type heavily doped region 31 corresponds to the negative electrode of the device, and the discharged current flows from the positive electrode to the negative electrode in the device, and finally the discharge of the ESD current is completed through the amplification action and the mutual positive feedback mechanism of the parasitic NPN-type triode and the PNP-type triode in the SCR structure.
Meanwhile, in this embodiment, the ultra shallow trench isolation region 23 (VSTI, very Shallow Trench Isolation) is disposed above the N-type well region 2, which belongs to an oxide and has a certain insulation capability, and the thickness of the ultra shallow trench isolation region 23 in this embodiment is smaller than that of the silicon film layer 4, which can change the width of the conductive path between the N-type well region 2 and the silicon film layer 4, increase the equivalent resistance (R1 in fig. 2) on the path from the positive electrode to the negative electrode of the device, improve the maintenance voltage of the SCR, and effectively reduce the leakage risk of the SCR.
The maintaining voltage of the SCR structure and the width of the ultra-shallow trench isolation region 23 have a positive correlation, and when the width of the ultra-shallow trench isolation region 23 is adjusted within the range of 0.1 μm to 5 μm, the adjusting range of the maintaining voltage is 1V to 9V.
Fig. 2 is a schematic diagram of equivalent circuit connection of the present embodiment, so as to explain the working principle of the structure of the present embodiment in detail. The starting voltage of the SCR structure depends on the avalanche breakdown voltage of a PN junction between the N-type well region 2 and the P-type well region 3, after the PN junction is subjected to avalanche breakdown, the avalanche breakdown generates a large number of electron hole pairs, electrons drift towards an anode and holes drift towards a cathode under the action of an electric field, once the voltage drop on the resistance RP of the P-type well region is larger than 0.7V, an NPN tube is opened, electron current is injected into the N-type well region 2 by a collector electrode of the NPN tube, the electron current flows through the resistance RN of the N-type well region to start a PNP tube, and the collector electrode of the PNP tube is connected with a base electrode of the NPN tube, so that the current amplified by the PNP tube returns to the NPN tube and is amplified by the NPN tube continuously, and the positive feedback is formed, so that the SCR structure enters a latch state, and the SCR structure is stably operated under a lower maintaining voltage Vh. The latch-up effect caused by the positive feedback mechanism enables the SCR to have good antistatic performance, meanwhile, the intrinsic maintaining voltage of the SCR structure is clamped at a lower voltage value, and specifically, the maintaining voltage Vh has the following calculation formula:
Vh＝V1+V2*(1+R1/RN)；
v1 is the voltage between the c pole and the e pole of the NPN tube, and V2 is the voltage between the b pole and the e pole of the PNP tube.
Fig. 3 shows TLP test curves of the esd protection structure of the present embodiment when different sti regions 23 are provided. It can be seen that the sustain voltage of the structure has a positive correlation with the width of the ultra-shallow trench isolation region 23, and when the width of the ultra-shallow trench isolation region 23 is increased from 0.3 μm to 5 μm, the sustain voltage of the structure can be controlled to be varied from 1V to 9V, so that the adjustment of the SCR sustain voltage can be realized by adjusting the width of the ultra-shallow trench isolation region 23.
Through simulation calculation, the silicon controlled rectifier structure for SOI ESD protection provided by the invention can be applied to circuit ESD protection designs of various processes, such as 0.13 mu m 1.8V/3.3V or 0.18 mu m 1.8V/3.3V/5V processes, and even some circuit ESD protection designs with higher working voltage.
The technical scheme provided by the embodiment of the invention has at least the following technical effects or advantages:
According to the embodiment of the invention, the polysilicon is manufactured on the N-type well region and the P-type well region, a certain voltage is applied to the polysilicon to provide enough trigger current and assist PN junction avalanche breakdown, so that the silicon controlled structure has lower starting voltage and rapid triggering latch-up effect, the purpose of discharging ESD current is realized, meanwhile, the ultra-shallow trench isolation region is arranged above the N-type well region, the insulation capacity of the ultra-shallow trench isolation region is utilized, the width of a conductive path is changed, the equivalent resistance (namely R1 in FIG. 2) on the conductive path is increased, the purpose of improving the maintaining voltage of the SCR is realized, the leakage risk of the SCR is effectively reduced based on the good insulation performance of the ultra-shallow trench isolation region, and in addition, the adjustment of the maintaining voltage of the SCR can be realized by adjusting the width of the ultra-shallow trench isolation region.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (9)
1. An electrostatic discharge protection structure of a silicon-on-insulator (SOI) process with adjustable maintenance voltage, which is characterized by comprising the following components: the polysilicon, the silicon film layer, the oxygen buried layer and the silicon substrate layer are stacked;
An N-type well region and a P-type well region are arranged in the silicon film layer side by side;
The upper part of the N-type well region is provided with a first N-type heavy doping region, a first P-type heavy doping region and a super shallow trench isolation region in parallel so as to form a first blank doping region at one corner of the N-type well region, which is close to the P-type well region;
The upper part of the P-type well region is provided with a second N-type heavily doped region and a second P-type heavily doped region in parallel so as to form a second blank doped region in the P-type well region, which is close to one corner of the N-type well region;
the polysilicon covers the top end face of the first blank doping region and the top end face of the second blank doping region;
The maintaining voltage of the SOI process silicon controlled electrostatic discharge protection structure and the width of the ultra shallow trench isolation region are in positive correlation corresponding relation;
the polysilicon is applied with a certain voltage, and a trigger current which is large enough is provided, so that the silicon controlled structure has a lower starting voltage.
2. The esd protection structure of claim 1, wherein the thickness of the N-well and the P-well do not exceed the thickness of the silicon film.
3. The esd protection structure of claim 1, wherein the first N-type heavily doped region and the first P-type heavily doped region are disposed adjacent to or spaced apart from each other.
4. The esd protection structure of claim 1, wherein the ultra-shallow trench isolation region and the first P-type heavily doped region are disposed adjacent to or spaced apart from each other.
5. The esd protection structure of claim 1, wherein the ultra-shallow trench isolation region has a thickness less than a thickness of the silicon film.
6. The esd protection structure of claim 1, wherein the doping concentration of the N-well and the doping concentration of the P-well are each 1e15/cm 3 to 1e18/cm 3.
7. The esd protection structure of claim 1, wherein the doping concentration of the first N-type heavily doped region, the doping concentration of the second N-type heavily doped region, the doping concentration of the first P-type heavily doped region, and the doping concentration of the second P-type heavily doped region are each greater than 1e18/cm 3.
8. The esd protection structure of claim 7, wherein the ultra-shallow trench isolation has a width in the range of 0.1 μm to 5 μm.
9. The esd protection structure of claim 8, wherein the adjustment range of the sustain voltage is 1V to 9V.
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| CN202011349209.0A CN112466937B (en) | 2020-11-26 | 2020-11-26 | SOI process silicon controlled electrostatic discharge protection structure with adjustable maintenance voltage |
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| CN202011349209.0A CN112466937B (en) | 2020-11-26 | 2020-11-26 | SOI process silicon controlled electrostatic discharge protection structure with adjustable maintenance voltage |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1913174A (en) * | 2005-08-09 | 2007-02-14 | 台湾积体电路制造股份有限公司 | Semiconductor device and high voltage p-type metal oxide semiconductor (HVPMOS) device |
| CN104766881A (en) * | 2014-01-08 | 2015-07-08 | 旺宏电子股份有限公司 | Semiconductor device |
| CN110277384A (en) * | 2018-03-13 | 2019-09-24 | 无锡华润上华科技有限公司 | Antistatic metal oxide semiconductor field effect tube structure |
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| US9263562B2 (en) * | 2014-02-11 | 2016-02-16 | United Microelectronics Corp. | Electrostatic discharge protection structure capable of preventing latch-up issue caused by unexpected noise |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1913174A (en) * | 2005-08-09 | 2007-02-14 | 台湾积体电路制造股份有限公司 | Semiconductor device and high voltage p-type metal oxide semiconductor (HVPMOS) device |
| CN104766881A (en) * | 2014-01-08 | 2015-07-08 | 旺宏电子股份有限公司 | Semiconductor device |
| CN110277384A (en) * | 2018-03-13 | 2019-09-24 | 无锡华润上华科技有限公司 | Antistatic metal oxide semiconductor field effect tube structure |
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