CN112466937A - Silicon controlled rectifier electrostatic discharge protection structure with adjustable holding voltage in SOI (silicon on insulator) process - Google Patents
Silicon controlled rectifier electrostatic discharge protection structure with adjustable holding voltage in SOI (silicon on insulator) process Download PDFInfo
- Publication number
- CN112466937A CN112466937A CN202011349209.0A CN202011349209A CN112466937A CN 112466937 A CN112466937 A CN 112466937A CN 202011349209 A CN202011349209 A CN 202011349209A CN 112466937 A CN112466937 A CN 112466937A
- Authority
- CN
- China
- Prior art keywords
- region
- type well
- well region
- heavily doped
- doped region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 52
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 52
- 239000010703 silicon Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000008569 process Effects 0.000 title claims abstract description 25
- 239000012212 insulator Substances 0.000 title abstract description 5
- 238000002955 isolation Methods 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 4
- 239000001301 oxygen Substances 0.000 claims abstract description 4
- 238000005516 engineering process Methods 0.000 claims description 5
- 238000009413 insulation Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000009024 positive feedback mechanism Effects 0.000 description 4
- 238000007599 discharging Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Thyristors (AREA)
Abstract
The invention relates to the technical field of silicon controlled rectifier electrostatic protection, in particular to a silicon controlled rectifier electrostatic discharge protection structure of an SOI (silicon on insulator) process with adjustable maintaining voltage. The method comprises the following steps: the polysilicon, the N-type well region, the P-type well region, the silicon film layer, the oxygen burying layer and the silicon substrate layer are stacked; an N-type well region and a P-type well region are adjacently arranged in the silicon film layer along the left-right direction; the top of the N-type well region and the top of the P-type well region are both contacted with the bottom of the polysilicon; the upper part of the N-type well region is sequentially provided with a first N-type heavily doped region, a first P-type heavily doped region and an ultra-shallow trench isolation region from left to right; and the upper part of the P-type well region is sequentially provided with a second N-type heavily doped region and a second P-type heavily doped region from left to right. According to the invention, the ultra-shallow trench isolation region is arranged above the N-type well region, and the insulation capability of the ultra-shallow trench isolation region is utilized, so that the equivalent resistance on a path from the positive electrode to the negative electrode in the SCR is increased, the purpose of improving the holding voltage of the SCR is realized, and the electric leakage risk of the SCR is effectively reduced.
Description
Technical Field
The invention relates to the technical field of silicon controlled rectifier electrostatic protection, in particular to a silicon controlled rectifier electrostatic discharge protection structure of an SOI (silicon on insulator) process with adjustable maintaining voltage.
Background
Static electricity exists in nature, and when static electricity accumulated in the external environment of a chip or the chip flows into or out of the chip through a pin of the chip, the instantaneously generated current (the peak value can reach several amperes) or voltage damages an integrated circuit, so that the function of the chip is invalid. Effective ESD (electrostatic Discharge) enables the protection device to be quickly turned on and Discharge ampere-level current in an electrostatic event, and simultaneously, the voltage between a pinch port or a power supply/ground is below the breakdown voltage of the core circuit, so as to achieve the purpose of protecting the core circuit from electrostatic damage.
With the development of the semiconductor industry, the SOI (Silicon-On-Insulator, Silicon technology) process is more and more mature, and SOI devices are widely applied in various fields. Due to the inherent limitations of SOI technology, SOI electrostatic protection has been a significant part of SOI device manufacturing applications. With the reduction of the critical dimension, the operating voltage of the core circuit is smaller and smaller, and the NMOS device is also suitable for ESD protection design until the 0.18 μm 3.3V process, but after the process enters the 0.18 μm 1.8V or 0.13 μm or even the nano-scale process, the turn-on voltage characteristic of the NMOS device cannot meet the ESD protection design requirement.
In order to obtain a device with a sufficiently low turn-on voltage, a Silicon Controlled Rectifier (SCR) structure is widely used to perform electrostatic protection on an integrated circuit. The starting voltage of the SCR is determined by the breakdown voltage of a PN junction between an N well and a P well, once one of the NPN or PNP tube is started, the positive feedback mechanism of the NPN and PNP tube can provide the latching maintaining current, so that the SCR works at a lower maintaining voltage, the latching effect caused by the positive feedback mechanism enables the SCR to have good antistatic capability, and the maintaining voltage of the SCR is clamped at a lower voltage value. Therefore, the SCR is an ideal electrostatic protection device, but due to its own characteristics, the device still has imperfect points such as high turn-on voltage, low holding voltage, and the like.
Therefore, how to reduce the leakage risk of the SCR is a technical problem that needs to be solved urgently at present.
Disclosure of Invention
The invention aims to provide an SOI technology silicon controlled rectifier electrostatic discharge protection structure with adjustable maintaining voltage so as to reduce the electric leakage risk of SCR.
In order to achieve the above object, an embodiment of the present invention provides an SOI technology silicon controlled electrostatic discharge protection structure with adjustable sustain voltage, including: the polysilicon, the silicon film layer, the oxygen burying layer and the silicon substrate layer are stacked;
an N-type well region and a P-type well region are arranged in the silicon film layer side by side;
a first N-type heavily doped region, a first P-type heavily doped region and an ultra-shallow trench isolation region are arranged at the upper part of the N-type well region side by side so as to form a first blank doped region at one corner of the N-type well region close to the P-type well region;
a second N-type heavily doped region and a second P-type heavily doped region are arranged at the upper part of the P-type well region side by side so as to form a second blank doped region at one corner of the P-type well region close to the N-type well region;
the polycrystalline silicon covers the top end face of the first blank doped region and the top end face of the second blank doped region.
In a possible embodiment, the thickness of the N-type well region and the thickness of the P-type well region do not exceed the thickness of the silicon film layer.
In a possible embodiment, the first heavily N-doped region and the first heavily P-doped region are disposed adjacently or spaced apart.
In a possible embodiment, the ultra-shallow trench isolation region and the first P-type heavily doped region are adjacently arranged or spaced.
In one possible embodiment, the thickness of the ultra-shallow trench isolation region is smaller than that of the silicon film layer.
In one possible embodiment, the doping concentration of the N-type well region and the doping concentration of the P-type well region are both 1e15/cm3To 1e18/cm3。
In a possible embodiment, the doping concentration of the first heavily doped N-type region, the doping concentration of the second heavily doped N-type region, the doping concentration of the first heavily doped P-type region and the doping concentration of the second heavily doped P-type region are all greater than 1e18/cm3。
In a possible embodiment, the maintaining voltage of the silicon controlled electrostatic discharge protection structure of the SOI process is in positive correlation correspondence with the width of the ultra-shallow trench isolation region.
In one possible embodiment, the width of the ultra-shallow trench isolation region ranges from 0.1 μm to 5 μm.
In one possible embodiment, the adjustment range of the sustain voltage is 1V to 9V.
Compared with the prior art, the invention has the following advantages and beneficial effects:
according to the invention, the polycrystalline silicon is manufactured on the N-type well region and the P-type well region, a certain voltage is applied to the polycrystalline silicon to provide a trigger current with a large enough value to assist PN junction avalanche breakdown, so that the silicon controlled structure has a lower starting voltage, a latch-up effect is rapidly triggered, and the purpose of discharging ESD current is realized.
Drawings
In order to more clearly illustrate the embodiments of the present specification or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present specification, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a silicon controlled electrostatic discharge protection structure of an SOI process with adjustable sustain voltage according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an equivalent circuit connection of a silicon controlled electrostatic discharge protection structure of an SOI process with adjustable sustain voltage according to an embodiment of the present invention;
fig. 3 is a TLP test curve of the scr esd protection structure provided by the embodiment of the invention when different widths of the ultra-shallow trench isolation regions are set.
Description of reference numerals: the silicon-based buried oxide film comprises a substrate, a substrate layer, a buried oxide layer and a substrate layer, wherein the substrate layer comprises 1 polysilicon, 2 an N-type well region, 21 a first N-type heavily doped region, 22 a first P-type heavily doped region, 23 an ultra-shallow trench isolation region, 3 a P-type well region, 31 a second N-type heavily doped region, 32 a second P-type heavily doped region, 4 a silicon film layer, 5 a buried oxide layer and 6 a silicon substrate layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by those skilled in the art based on the embodiments of the present invention belong to the scope of protection of the embodiments of the present invention.
The present embodiment provides a silicon controlled electrostatic discharge protection structure for an SOI process with adjustable sustain voltage, please refer to fig. 1, where fig. 1 is a schematic structural diagram of the structure, and specifically includes:
the buried oxide film comprises polycrystalline silicon 1, an N-type well region 2, a first N-type heavily doped region 21, a first P-type heavily doped region 22, an ultra-shallow trench isolation region 23, a P-type well region 3, a second N-type heavily doped region 31, a second P-type heavily doped region 32, a silicon film layer 4, a buried oxide layer 5 and a silicon substrate layer 6.
Specifically, the polycrystalline silicon 1, the silicon film layer 4, the oxygen burying layer 5 and the silicon substrate layer 6 are stacked from top to bottom.
The N type trap area 2 and the P type trap area 3 are arranged in the silicon film layer 4 side by side along the left and right directions, and the two trap areas can be arranged in an adjacent contact mode and can also be arranged in a spaced non-contact mode. Specifically, the thickness of the N-type well region 2 and the thickness of the P-type well region 3 do not exceed the thickness of the silicon film layer 4, and the doping concentration range of the N-type well region 2 and the doping concentration range of the P-type well region 3 are both 1e15/cm3To 1e18/cm3。
The top of the N-type well region 2 and the top end surface of the P-type well region 3 are both contacted with the bottom of the polysilicon 1. A first N-type heavily doped region 21, a first P-type heavily doped region 22 and an ultra-shallow trench isolation region 23 are arranged in parallel from left to right on the upper portion of the N-type well region 2, so that a first blank doped region is formed in one corner of the N-type well region 2 close to the P-type well region 3; a second N-type heavily doped region 31 and a second P-type heavily doped region 32 are sequentially arranged from left to right on the upper portion of the P-type well region 3, so that a second blank doped region is formed in one corner of the P-type well region 3 close to the N-type well region 2.
The top of the first N-type heavily doped region 21, the top of the first P-type heavily doped region 22 and the top of the ultra-shallow trench isolation region 23 are all flush with the top of the N-type well region 2, the top of the second N-type heavily doped region 31 and the top of the second P-type heavily doped region 32 are all flush with the top of the P-type well region 3, the polysilicon 1 is arranged on the top end surfaces of the N-type well region 2 and the P-type well region 3, the polysilicon 1 covers the top end surface of the first blank doped region and the top end surface of the second blank doped region, the bottom surface of the polysilicon 1 contacts the partial top end surfaces of the N-type well region 2 and the P-type well region 3, but does not cover the top of the ultra-shallow trench isolation region 23, and the bottom ofA sub-region; the first sub-region contacts the top of the N-type well region 2; the second sub-region contacts the top of the P-type well region 3. The top of the first heavily doped N-type region 21, the top of the first heavily doped P-type region 22 and the top of the ultra-shallow trench isolation region 23 are not in contact with the bottom of the polysilicon 1, and the top of the second heavily doped N-type region 31 and the top of the second heavily doped P-type region 32 are not in contact with the bottom of the polysilicon 1. The doping concentration of the first N type heavily doped region 21, the doping concentration of the second N type heavily doped region 31, the doping concentration of the first P type heavily doped region 22 and the doping concentration of the second P type heavily doped region 32 are all more than 1e18/cm3。
In the above structure, the first N-type heavily doped region 21 and the first P-type heavily doped region 22 may be disposed in adjacent contact, or may be disposed at intervals without contact; the thickness of the ultra-shallow trench isolation region 23 is less than that of the silicon film layer 4; meanwhile, the ultra-shallow trench isolation region 23 and the first P-type heavily doped region 22 may be disposed in adjacent contact, or may be disposed at intervals without contact.
In this embodiment, the polysilicon 1 is fabricated on the N-type well region 2 and the P-type well region 3, and a certain voltage is applied to the polysilicon 1 to provide a large enough trigger current, so that the silicon controlled rectifier structure has a low turn-on voltage, a latch effect is triggered quickly, and the purpose of discharging ESD current is achieved. In the process, the electrode led out from the first P-type heavily doped region 22 is equivalent to the anode of the device, the electrode led out from the second N-type heavily doped region 31 is equivalent to the cathode of the device, the released current flows from the anode to the cathode in the device, and the release of the ESD current is finally completed through the amplification action of the parasitic NPN-type triode and the parasitic PNP-type triode in the SCR structure and the mutual positive feedback mechanism.
Meanwhile, in the embodiment, the ultra-Shallow Trench Isolation region 23(VSTI, Very Shallow Trench Isolation) is arranged above the N-type well region 2, and belongs to an oxide and has a certain insulating capability, the thickness of the ultra-Shallow Trench Isolation region 23 in the embodiment is smaller than that of the silicon film layer 4, the width of a conductive path between the N-type well region 2 and the silicon film layer 4 can be changed, the equivalent resistance (R1 in fig. 2) on a path from the anode to the cathode of the device is increased, the holding voltage of the SCR is improved, and the leakage risk of the SCR is effectively reduced.
The holding voltage of the SCR structure is in a positive correlation with the width of the ultra-shallow trench isolation region 23, and when the width of the ultra-shallow trench isolation region 23 is adjusted within a range of 0.1 μm to 5 μm, the adjustment range of the holding voltage is 1V to 9V.
Fig. 2 is a schematic diagram of an equivalent circuit connection of the present embodiment to explain the working principle of the structure of the present embodiment in detail. The starting voltage of the SCR structure depends on the avalanche breakdown voltage of a PN junction between the N-type well region 2 and the P-type well region 3, after the PN junction is subjected to avalanche breakdown, the avalanche breakdown generates a large number of electron-hole pairs, electrons drift to the anode and holes drift to the cathode under the action of an electric field, once the voltage drop of a P-type well region resistor RP is larger than 0.7V, the NPN tube is opened, an electron current is injected into the N-type well region 2 by a collector electrode of the NPN tube, the electron current flows through the N-type well region resistor RN, the PNP tube is started, the collector electrode of the PNP tube is connected with a base electrode of the NPN tube, the current amplified by the PNP tube returns to the NPN tube and is continuously amplified by the NPN tube, and the cycle is repeated, so that positive feedback is formed, the SCR structure enters a latch state, and the SCR structure stably works. The latch-up effect caused by the positive feedback mechanism enables the SCR to have good antistatic performance, and meanwhile, the intrinsic maintaining voltage of the SCR structure is clamped at a lower voltage value, and specifically, the maintaining voltage Vh is calculated according to the following formula:
Vh＝V1+V2*(1+R1/RN)；
wherein, V1 is the voltage between the c pole and the e pole of the NPN tube, and V2 is the voltage between the b pole and the e pole of the PNP tube.
Fig. 3 shows a TLP test curve of the scr esd protection structure provided in this embodiment when different widths of the ultra-shallow trench isolation region 23 are set. It can be seen that the maintaining voltage of the structure is in a positive correlation corresponding relationship with the width of the ultra-shallow trench isolation region 23, and when the width of the ultra-shallow trench isolation region 23 is increased from 0.3 μm to 5 μm, the maintaining voltage of the structure can be controlled to be 1V to 9V, so that the SCR maintaining voltage can be adjusted by adjusting the width of the ultra-shallow trench isolation region 23.
Through simulation calculation, the silicon controlled rectifier structure for SOI ESD protection provided by the invention can be applied to circuit ESD protection designs of various processes, such as circuits of 0.13 μm 1.8V/3.3V or 0.18 μm 1.8V/3.3V/5V processes, and even some circuit ESD protection designs with higher working voltage.
The technical scheme provided by the embodiment of the invention at least has the following technical effects or advantages:
according to the embodiment of the invention, the polycrystalline silicon is manufactured on the N-type well region and the P-type well region, a certain voltage is applied to the polycrystalline silicon to provide a trigger current with a large enough value to assist PN junction avalanche breakdown, so that the silicon controlled structure has a lower starting voltage to quickly trigger latch-up effect and realize the purpose of discharging ESD current, meanwhile, the ultra-shallow trench isolation region is arranged above the N-type well region, the width of a conducting path is changed by utilizing the insulating capability of the ultra-shallow trench isolation region, the equivalent resistance (namely R1 in figure 2) on the conducting path is increased, the purpose of improving the maintaining voltage of the SCR is realized, the leakage risk of the SCR is effectively reduced based on the good insulating performance of the ultra-shallow trench isolation region, and in addition, the adjustment of the maintaining voltage of the SCR can be realized by adjusting the width of.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. An SOI technology silicon controlled rectifier electrostatic discharge protection structure with adjustable maintaining voltage is characterized by comprising the following components: the polysilicon, the silicon film layer, the oxygen burying layer and the silicon substrate layer are stacked;
an N-type well region and a P-type well region are arranged in the silicon film layer side by side;
a first N-type heavily doped region, a first P-type heavily doped region and an ultra-shallow trench isolation region are arranged at the upper part of the N-type well region side by side so as to form a first blank doped region at one corner of the N-type well region close to the P-type well region;
a second N-type heavily doped region and a second P-type heavily doped region are arranged at the upper part of the P-type well region side by side so as to form a second blank doped region at one corner of the P-type well region close to the N-type well region;
the polycrystalline silicon covers the top end face of the first blank doped region and the top end face of the second blank doped region.
2. The SOI process thyristor electrostatic discharge protection structure of claim 1, wherein the thickness of the N-type well region and the thickness of the P-type well region do not exceed the thickness of the silicon film layer.
3. The SOI process silicon controlled electrostatic discharge protection structure of claim 1, wherein the first N type heavily doped region and the first P type heavily doped region are disposed adjacently or at an interval.
4. The SOI process thyristor electrostatic discharge protection structure of claim 1, wherein the ultra-shallow trench isolation region and the first P-type heavily doped region are disposed adjacent to each other or spaced apart from each other.
5. The SOI process thyristor electrostatic discharge protection structure of claim 1 wherein the thickness of the ultra-shallow trench isolation region is less than the thickness of the silicon film layer.
6. The SOI process SCR ESD protection structure of claim 1, wherein the N-well and P-well are both doped at 1e15/cm3To 1e18/cm3。
7. According to claim1 the silicon controlled electrostatic discharge protection structure of the SOI process is characterized in that the doping concentration of the first N type heavily doped region, the doping concentration of the second N type heavily doped region, the doping concentration of the first P type heavily doped region and the doping concentration of the second P type heavily doped region are all more than 1e18/cm3。
8. The silicon controlled electrostatic discharge protection structure of SOI process as claimed in claim 1, wherein the sustain voltage of the silicon controlled electrostatic discharge protection structure of SOI process is in positive correlation with the width of the ultra-shallow trench isolation region.
9. The SOI process thyristor electrostatic discharge protection structure of claim 8, wherein the width of the ultra-shallow trench isolation region ranges from 0.1 μm to 5 μm.
10. The SOI process scr esd protection structure of claim 9, wherein the adjustment range of the sustain voltage is 1V to 9V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011349209.0A CN112466937B (en) | 2020-11-26 | 2020-11-26 | SOI process silicon controlled electrostatic discharge protection structure with adjustable maintenance voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011349209.0A CN112466937B (en) | 2020-11-26 | 2020-11-26 | SOI process silicon controlled electrostatic discharge protection structure with adjustable maintenance voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112466937A true CN112466937A (en) | 2021-03-09 |
| CN112466937B CN112466937B (en) | 2024-04-23 |
Family
ID=74808689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011349209.0A Active CN112466937B (en) | 2020-11-26 | 2020-11-26 | SOI process silicon controlled electrostatic discharge protection structure with adjustable maintenance voltage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112466937B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1913174A (en) * | 2005-08-09 | 2007-02-14 | 台湾积体电路制造股份有限公司 | Semiconductor device and high voltage p-type metal oxide semiconductor (HVPMOS) device |
| CN104766881A (en) * | 2014-01-08 | 2015-07-08 | 旺宏电子股份有限公司 | Semiconductor device |
| US20150228771A1 (en) * | 2014-02-11 | 2015-08-13 | United Microelectronics Corp. | Electrostatic discharge protection structure capable of preventing latch-up issue caused by unexpected noise |
| CN110277384A (en) * | 2018-03-13 | 2019-09-24 | 无锡华润上华科技有限公司 | Antistatic metal oxide semiconductor field effect tube structure |
-
2020
- 2020-11-26 CN CN202011349209.0A patent/CN112466937B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1913174A (en) * | 2005-08-09 | 2007-02-14 | 台湾积体电路制造股份有限公司 | Semiconductor device and high voltage p-type metal oxide semiconductor (HVPMOS) device |
| CN104766881A (en) * | 2014-01-08 | 2015-07-08 | 旺宏电子股份有限公司 | Semiconductor device |
| US20150228771A1 (en) * | 2014-02-11 | 2015-08-13 | United Microelectronics Corp. | Electrostatic discharge protection structure capable of preventing latch-up issue caused by unexpected noise |
| CN110277384A (en) * | 2018-03-13 | 2019-09-24 | 无锡华润上华科技有限公司 | Antistatic metal oxide semiconductor field effect tube structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112466937B (en) | 2024-04-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101454537B1 (en) | Esd devices comprising semiconductor fins | |
| US6830966B2 (en) | Fully silicided NMOS device for electrostatic discharge protection | |
| CN111524884B (en) | Improved LDMOS-SCR device for high-voltage ESD protection | |
| US8598625B2 (en) | ESD protection device with tunable design windows | |
| US8896024B1 (en) | Electrostatic discharge protection structure and electrostatic discharge protection circuit | |
| CN109244068B (en) | LIGBT type high-voltage ESD protection device | |
| US20230207556A1 (en) | Electrostatic protection device including scr and manufacturing method thereof | |
| CN215815877U (en) | High-maintenance high-failure bidirectional thyristor electrostatic protection device | |
| CN112466937B (en) | SOI process silicon controlled electrostatic discharge protection structure with adjustable maintenance voltage | |
| CN112151532B (en) | Semiconductor device for electrostatic protection | |
| US9240401B2 (en) | Semiconductor device and method of manufacturing a semiconductor device | |
| CN112466939A (en) | Silicon controlled rectifier device with electrostatic discharge protection function | |
| CN112466940B (en) | Silicon controlled rectifier device | |
| CN112466938B (en) | Silicon controlled device applied to deep submicron-level circuit electrostatic protection | |
| CN116093151B (en) | Bipolar transistor structure and manufacturing method thereof | |
| CN115911117B (en) | Bipolar transistor structure and manufacturing method thereof | |
| WO2024093701A1 (en) | Electrostatic discharge protection device | |
| US11837600B2 (en) | Electrostatic discharge protection apparatus and its operating method | |
| CN112490216B (en) | WAT test structure and method for characterizing PN junction depletion region | |
| CN211858652U (en) | Silicon controlled electrostatic discharge device and integrated circuit | |
| JP2014038922A (en) | Semiconductor device | |
| CN111403470A (en) | Thyristor device based on SOI (silicon on insulator) process and electrostatic protection circuit | |
| CN114121940A (en) | ESD protection structure with adjustable trigger voltage and manufacturing method thereof | |
| CN117878115A (en) | Structure, manufacturing method and electronic equipment of DCSCR device | |
| CN115621318A (en) | GGNMOS transistor structure, ESD protection device and circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |