CN113871382B - A DCSCR device with optimized ESD protection performance - Google Patents
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Abstract
Description
技术领域technical field
本发明属于静电释放（ESD：Electro-Static Discharge）保护器件的设计领域，尤其指二极管直连触发的可控硅整流器（Direct-Connected Silicon-ControlledRectifier简称DCSCR），具体提供一种优化ESD防护性能的DCSCR器件。The invention belongs to the design field of electrostatic discharge (ESD: Electro-Static Discharge) protection devices, especially refers to a silicon-controlled rectifier (Direct-Connected Silicon-Controlled Rectifier referred to as DCSCR) triggered by a diode direct connection, and specifically provides an optimized ESD protection performance DCSCR device.
背景技术Background technique
静电放电（Electro-Static discharge，简称ESD）现象是指具有不同电势的物体相互靠近或接触时发生的电荷转移现象，由于放电时间极短，放电过程中会产生很大的电流；对于集成电路而言，现代IC更容易受到静电放电（ESD）引起的损坏，这种大电流会损伤甚至烧毁内部器件，导致芯片失效；芯片生产运输使用的各个环节都有可能出现静电放电现象，因此芯片的ESD防护措施对于其可靠性是不可或缺的。Electro-Static discharge (ESD for short) phenomenon refers to the charge transfer phenomenon that occurs when objects with different potentials approach or touch each other. Due to the extremely short discharge time, a large current will be generated during the discharge process; for integrated circuits In other words, modern ICs are more susceptible to damage caused by electrostatic discharge (ESD). This high current will damage or even burn internal devices, resulting in chip failure; electrostatic discharge may occur in all aspects of chip production, transportation and use, so the ESD of the chip Safeguards are integral to their reliability.
全芯片ESD保护网络通常可以分为如下三种情况，各有优缺点。针对引脚数量少的模拟电路，可以选用本地ESD保护网络，不需要借助总线，每个引脚均可独立实现保护；基于电源轨的ESD保护具有占用面积小，工艺移植性强的优点，但是增加了芯片设计和验证的复杂度；基于PAD的ESD保护网络主要面向多种类型端口的芯片。基于电源轨的ESD保护网络在工程上广泛使用，其利用二极管作为I/O口的上下端保护器件，Power Clamp作为电源到地的ESD保护电路。二极管结构简单，易于使用，广泛应用于ESD保护结构中，特别针对数字信号、高速信号端口。除了满足保护窗口以外，寄生电容是ESD保护结构的重要考虑因素。串联二极管的寄生电容随着串联数量增加而成比例减小。串联数量越多，也会导致其开启电压越高，导通电阻越大，会影响ESD保护性能。Full-chip ESD protection networks can generally be divided into the following three situations, each with its own advantages and disadvantages. For analog circuits with a small number of pins, a local ESD protection network can be selected, without the need for a bus, and each pin can be independently protected; ESD protection based on power rails has the advantages of small footprint and strong process portability, but Increased the complexity of chip design and verification; the PAD-based ESD protection network is mainly for chips with multiple types of ports. The ESD protection network based on the power rail is widely used in engineering, which uses diodes as the upper and lower protection devices of the I/O port, and Power Clamp as the ESD protection circuit from the power supply to the ground. Diodes are simple in structure and easy to use, and are widely used in ESD protection structures, especially for digital signals and high-speed signal ports. In addition to meeting the protection window, parasitic capacitance is an important consideration for ESD protection structures. The parasitic capacitance of series diodes decreases proportionally with the number of series connected diodes. The greater the number of series connections, the higher the turn-on voltage and the greater the on-resistance, which will affect the ESD protection performance.
DCSCR（Diode-ConnectedSilicon-ControlledRectifier）是一种利用二极管串触发的SCR器件，其具有电阻小、鲁棒性高等诸多优势，同时DCSCR还可以通过器件堆叠来调整触发电压以满足不同设计窗口需求，广泛应用于先进工艺下的ESD防护中。DCSCR器件等效为两个串联的二极管，可以代替二极管使用在ESD防护网络中。DCSCR的触发电压仅约为1.4V，这已经是SCR类型的器件在硅工艺上所能实现的最低开启电压，非常适用于最先进的低压ESD窗口（如14nmFinFET工艺下的0.8V电路）；而对于传统平面CMOS工艺中相对较高的工作电压，DCSCR可以采用堆叠的方式来灵活地满足，还可以在基于电源轨的全芯片ESD防护架构中替代I/O端口的二极管器件，以实现更优的寄生电容特性；另一方面，DCSCR中，由于SCR结构寄生的两个晶体管的发射结都恰好处于辅助触发路径上，其充电时间（即Tcharge）均很快，这使得DCSCR具有导通速度快的优势。DCSCR (Diode-ConnectedSilicon-ControlledRectifier) is an SCR device triggered by a diode string, which has many advantages such as small resistance and high robustness. At the same time, DCSCR can also adjust the trigger voltage through device stacking to meet the needs of different design windows. It is used in ESD protection under advanced technology. The DCSCR device is equivalent to two diodes connected in series, which can be used instead of the diode in the ESD protection network. The trigger voltage of DCSCR is only about 1.4V, which is already the lowest turn-on voltage of SCR type devices on silicon technology, which is very suitable for the most advanced low-voltage ESD window (such as 0.8V circuit under 14nm FinFET technology); and For the relatively high operating voltage in the traditional planar CMOS process, DCSCR can be flexibly satisfied by stacking, and can also replace the diode device of the I/O port in the full-chip ESD protection architecture based on the power rail to achieve better performance. On the other hand, in DCSCR, since the emitter junctions of the two transistors parasitic in the SCR structure are just on the auxiliary trigger path, the charging time (ie Tcharge) is very fast, which makes DCSCR have a fast turn-on speed The advantages.
随着半导体工艺的进步发展，半导体工艺进入纳米领域，器件的栅氧击穿电压、源漏击穿电压进一步降低，这要求ESD防护器件要有更低的窗口，更强的灵敏性；并且采用先进工艺的集成电路往往工作在极高的频率下，这要求ESD防护器件要有更低的电容；先进工艺的集成电路也同时要求版图的精简紧凑，这要求ESD防护器件要有小面积；总的来说，先进工艺下的集成电路对ESD防护要求低触发电压、高灵敏度、低寄生电容、小面积。因此，高性能的ESD防护器件就尤为重要。With the progress and development of semiconductor technology, semiconductor technology has entered the nanometer field, and the gate oxide breakdown voltage and source-drain breakdown voltage of the device are further reduced, which requires ESD protection devices to have a lower window and stronger sensitivity; and adopt Integrated circuits of advanced technology often work at extremely high frequencies, which requires ESD protection devices to have lower capacitance; integrated circuits of advanced technology also require a compact and compact layout, which requires ESD protection devices to have a small area; Generally speaking, integrated circuits under advanced technology require low trigger voltage, high sensitivity, low parasitic capacitance, and small area for ESD protection. Therefore, high-performance ESD protection devices are particularly important.
发明内容Contents of the invention
本发明的目的在于提供优化ESD防护性能的DCSCR器件，通过对传统DCSCR器件的结构改进，在不减小DCSCR器件的ESD防护能力的前提下，实现了小面积、低导通阻抗、低寄生电容以及高开启速度，适用于纳米级工艺下的低压ESD防护。The purpose of the present invention is to provide a DCSCR device with optimized ESD protection performance. By improving the structure of the traditional DCSCR device, it realizes small area, low conduction resistance and low parasitic capacitance without reducing the ESD protection capability of the DCSCR device. And high turn-on speed, suitable for low-voltage ESD protection under nano-scale technology.
为实现上述目的，本发明采用的技术方案一如下：In order to achieve the above object, the technical solution one adopted in the present invention is as follows:
一种优化ESD防护性能的DCSCR器件，包括：A DCSCR device with optimized ESD protection performance, comprising:
P型硅衬底（110），P型硅衬底（110）上形成的N型阱区（130）、P型阱区（140）以及N型深阱区（120）；所述P型阱区（140）设置于N型阱区（130）中、且下方通过N型深阱区（120）与P型硅衬底（110）相隔离；P-type silicon substrate (110), N-type well region (130), P-type well region (140) and N-type deep well region (120) formed on P-type silicon substrate (110); the P-type well The region (140) is arranged in the N-type well region (130), and is isolated from the P-type silicon substrate (110) by the N-type deep well region (120) below;
所述N型阱区（130）内依次设置有第二N型重掺杂区（132）、第一P型重掺杂区（131）与第三N型重掺杂区（133），所述P型阱区（140）内依次设置有第二P型重掺杂区（142）、第一N型重掺杂区（141）与第三P型重掺杂区（143）；第一P型重掺杂区（131）与阳极（Anode）相连，第一N型重掺杂区（141）与阴极（Cathode）相连；The N-type well region (130) is sequentially provided with a second N-type heavily doped region (132), a first P-type heavily doped region (131) and a third N-type heavily doped region (133), so The P-type well region (140) is sequentially provided with a second P-type heavily doped region (142), a first N-type heavily doped region (141) and a third P-type heavily doped region (143); the first The P-type heavily doped region (131) is connected to the anode (Anode), and the first N-type heavily doped region (141) is connected to the cathode (Cathode);
所述第二N型重掺杂区（132）、第一P型重掺杂区（131）与第三N型重掺杂区（133）沿垂直方向（Y轴）依次排布，第二N型重掺杂区（132）与第一P型重掺杂区（131）之间、第三N型重掺杂区（133）与第一P型重掺杂区（131）之间分别设有浅沟槽隔离；所述第二P型重掺杂区（142）、第一N型重掺杂区（141）与第三P型重掺杂区（143）沿垂直方向（Y轴）依次排布，第二P型重掺杂区（142）与第一N型重掺杂区（141）之间、第三P型重掺杂区（143）与第一N型重掺杂区（141）之间分别设有浅沟槽隔离；第一P型重掺杂区（131）与第一N型重掺杂区（141）沿水平方向（X轴）并列排布，第二N型重掺杂区（132）与第二P型重掺杂区（142）沿水平方向（X轴）并列排布、且二者通过金属直接连接，第三N型重掺杂区（133）与第三P型重掺杂区（143）沿水平方向（X轴）并列排布、且二者通过金属直接连接；第二N型重掺杂区（132）与第二P型重掺杂区（142）之间、第三N型重掺杂区（133）与第三P型重掺杂区（143）之间分别设有浅沟槽隔离。The second N-type heavily doped region (132), the first P-type heavily doped region (131) and the third N-type heavily doped region (133) are arranged in sequence along the vertical direction (Y axis), and the second Between the N-type heavily doped region (132) and the first P-type heavily doped region (131), between the third N-type heavily doped region (133) and the first P-type heavily doped region (131), respectively Shallow trench isolation is provided; the second P-type heavily doped region (142), the first N-type heavily doped region (141) and the third P-type heavily doped region (143) are arranged along the vertical direction (Y-axis ) are arranged in sequence, between the second P-type heavily doped region (142) and the first N-type heavily doped region (141), between the third P-type heavily doped region (143) and the first N-type heavily doped region The regions (141) are respectively provided with shallow trench isolation; the first P-type heavily doped region (131) and the first N-type heavily doped region (141) are arranged side by side along the horizontal direction (X axis), and the second The N-type heavily doped region (132) and the second P-type heavily doped region (142) are arranged side by side along the horizontal direction (X-axis), and the two are directly connected by metal, and the third N-type heavily doped region (133 ) and the third P-type heavily doped region (143) are arranged side by side along the horizontal direction (X-axis), and the two are directly connected by metal; the second N-type heavily doped region (132) is connected to the second P-type heavily doped Shallow trench isolation is respectively provided between the impurity regions (142), and between the third N-type heavily doped region (133) and the third P-type heavily doped region (143).
进一步的，所述第二N型重掺杂区（132）与第一P型重掺杂区（131）之间、所述第三N型重掺杂区（133）与第一P型重掺杂区（131）之间、所述第二P型重掺杂区（142）与第一N型重掺杂区（141）之间、以及所述第三P型重掺杂区（143）与第一N型重掺杂区（141）之间的浅沟槽隔离分别替换为多晶硅栅。Further, between the second N-type heavily doped region (132) and the first P-type heavily doped region (131), between the third N-type heavily doped region (133) and the first P-type heavily doped region Between the doped regions (131), between the second P-type heavily doped region (142) and the first N-type heavily doped region (141), and the third P-type heavily doped region (143 ) and the first N-type heavily doped region ( 141 ) are respectively replaced with polysilicon gates.
本发明的有益效果在于：The beneficial effects of the present invention are:
本发明提供了一种用于低压ESD保护的改进型DCSCR器件，通过对传统DCSCR器件的结构改进，通过将N型阱区内的N型重掺杂区设置到P型重掺杂区的上下方（垂直方向（Y轴）依次排布），将P型阱内的P型重掺杂区设置到N型重掺杂区的上下方，大大减小了二极管的宽度，有效缩小了二极管的面积；并且，通过将DCSCR的触发二极管在原有位置中嵌入到SCR触发路径有源区的上下方，缩短了SCR的导通路径，减小了导通电阻、寄生电容，提升了开启速度；综上，本发明在不降低ESD防护能力的前提下，实现了器件面积的减小与器件性能的提升。The invention provides an improved DCSCR device for low-voltage ESD protection, by improving the structure of the traditional DCSCR device, by setting the N-type heavily doped region in the N-type well region above and below the P-type heavily doped region Square (arranged in sequence in the vertical direction (Y axis)), the P-type heavily doped region in the P-type well is set above and below the N-type heavily doped region, which greatly reduces the width of the diode and effectively reduces the size of the diode. area; and, by embedding the trigger diode of DCSCR in the original position above and below the active area of the SCR trigger path, the conduction path of the SCR is shortened, the conduction resistance and parasitic capacitance are reduced, and the turn-on speed is improved; comprehensively Above all, the present invention realizes the reduction of the device area and the improvement of the device performance under the premise of not reducing the ESD protection capability.
附图说明Description of drawings
图1为传统DCSCR器件的截面结构示意图。Fig. 1 is a schematic cross-sectional structure diagram of a traditional DCSCR device.
图2为传统DCSCR器件的俯视结构示意图。FIG. 2 is a schematic top view of a conventional DCSCR device.
图3为本发明实施例1提供的优化ESD防护性能的DCSCR器件的结构示意图。FIG. 3 is a schematic structural diagram of a DCSCR device with optimized ESD protection performance provided by Embodiment 1 of the present invention.
图4为本发明实施例2提供的优化ESD防护性能的DCSCR器件的结构示意图。FIG. 4 is a schematic structural diagram of a DCSCR device with optimized ESD protection performance provided by Embodiment 2 of the present invention.
具体实施方式Detailed ways
下面结合附图和具体实施方式对本发明进行详细说明。The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.
实施例1Example 1
本实施例提供一种优化ESD防护性能的DCSCR器件，其结构如图3所示，包括：This embodiment provides a DCSCR device with optimized ESD protection performance, the structure of which is shown in Figure 3, including:
P型硅衬底（110），P型硅衬底（110）上形成的N型阱区（130）、P型阱区（140）以及N型深阱区（120）；所述P型阱区（140）设置于N型阱区（130）中、且下方通过N型深阱区（120）与P型硅衬底（110）相隔离，即N型阱区（130）与N型深阱区（120）将P型阱区（140）包围；P-type silicon substrate (110), N-type well region (130), P-type well region (140) and N-type deep well region (120) formed on P-type silicon substrate (110); the P-type well The region (140) is set in the N-type well region (130), and is isolated from the P-type silicon substrate (110) below by the N-type deep well region (120), that is, the N-type well region (130) and the N-type deep The well region (120) surrounds the P-type well region (140);
所述N型阱区（130）内依次设置有第二N型重掺杂区（132）、第一P型重掺杂区（131）与第三N型重掺杂区（133）；其中， 第二N型重掺杂区（132）与第一P型重掺杂区（131）之间设有浅沟槽隔离，第三N型重掺杂区（133）与第一P型重掺杂区（131）之间设有浅沟槽隔离；所述第一P型重掺杂区（131）与阳极（Anode）相连；The N-type well region (130) is sequentially provided with a second N-type heavily doped region (132), a first P-type heavily doped region (131) and a third N-type heavily doped region (133); wherein , a shallow trench isolation is provided between the second N-type heavily doped region (132) and the first P-type heavily doped region (131), and the third N-type heavily doped region (133) is connected to the first P-type heavily doped region Shallow trench isolation is provided between the doped regions (131); the first P-type heavily doped region (131) is connected to an anode (Anode);
所述P型阱区（140）内依次设置有第二P型重掺杂区（142）、第一N型重掺杂区（141）与第三P型重掺杂区（143）；其中，第二P型重掺杂区（142）与第一N型重掺杂区（141）之间设有浅沟槽隔离，第三P型重掺杂区（143）与第一N型重掺杂区（141）之间设有浅沟槽隔离；所述第一N型重掺杂区（141）与阴极（Cathode）相连；The P-type well region (140) is sequentially provided with a second P-type heavily doped region (142), a first N-type heavily doped region (141) and a third P-type heavily doped region (143); wherein , there is a shallow trench isolation between the second P-type heavily doped region (142) and the first N-type heavily doped region (141), and the third P-type heavily doped region (143) is connected to the first N-type heavily doped region Shallow trench isolation is provided between the doped regions (141); the first N-type heavily doped region (141) is connected to a cathode (Cathode);
所述第二N型重掺杂区（132）、第一P型重掺杂区（131）与第三N型重掺杂区（133）沿垂直方向（Y轴）依次排布，所述第二P型重掺杂区（142）、第一N型重掺杂区（141）与第三P型重掺杂区（143）沿垂直方向（Y轴）依次排布，第一P型重掺杂区（131）与第一N型重掺杂区（141）沿水平方向（X轴）并列排布，第二N型重掺杂区（132）与第二P型重掺杂区（142）沿水平方向（X轴）并列排布、且二者通过金属直接连接，第三N型重掺杂区（133）与第三P型重掺杂区（143）沿水平方向（X轴）并列排布、且二者通过金属直接连接；第一P型重掺杂区（131）与第一N型重掺杂区（141）之间设有浅沟槽隔离，第二N型重掺杂区（132）与第二P型重掺杂区（142）之间设有浅沟槽隔离，第三N型重掺杂区（133）与第三P型重掺杂区（143）二者之间设有浅沟槽隔离。The second N-type heavily doped region (132), the first P-type heavily doped region (131) and the third N-type heavily doped region (133) are arranged in sequence along the vertical direction (Y axis), and the The second P-type heavily doped region (142), the first N-type heavily doped region (141) and the third P-type heavily doped region (143) are arranged in sequence along the vertical direction (Y axis), and the first P-type The heavily doped region (131) and the first N-type heavily doped region (141) are arranged side by side along the horizontal direction (X axis), and the second N-type heavily doped region (132) and the second P-type heavily doped region (142) are arranged side by side along the horizontal direction (X axis), and the two are directly connected by metal, the third N-type heavily doped region (133) and the third P-type heavily doped region (143) are arranged along the horizontal direction (X axes) are arranged side by side, and the two are directly connected by metal; there is a shallow trench isolation between the first P-type heavily doped region (131) and the first N-type heavily doped region (141), and the second N-type A shallow trench isolation is provided between the heavily doped region (132) and the second P-type heavily doped region (142), and the third N-type heavily doped region (133) is connected to the third P-type heavily doped region (143). ) with shallow trench isolation between them.
从工作原理上讲：In terms of working principle:
如图1、图2所示的传统DCSCR器件，其二极管起辅助触发的作用，开启后电流的泄放主要通过SCR的泄放路径；本发明与之相比如图3所示，本实施例将传统DCSCR器件进行结构优化，将N型阱区130内的N型重掺杂区设置到P型重掺杂区131的上下方（垂直方向（Y轴）依次排布），并相互之间均用STI进行隔离；同时将P型阱140内的P型重掺杂区设置到N型重掺杂区141的上下方（垂直方向（Y轴）依次排布），并相互之间均用STI进行隔离；本实施例减小了二极管的宽度，缩小了二极管的面积，通过将DCSCR的触发二极管在原有位置中嵌入到SCR触发路径有源区的上下方，缩短了SCR的导通路径，在不改变器件的ESD防护能力的情况下，实现了器件面积的减小，以及导通电阻、寄生电容的减小。The traditional DCSCR device as shown in Figure 1 and Figure 2, its diode plays the role of auxiliary triggering, and the discharge of the current after it is turned on mainly passes through the discharge path of the SCR; the present invention is compared with it as shown in Figure 3, and this embodiment will The structure of traditional DCSCR devices is optimized, and the N-type heavily doped regions in the N-
实施例2Example 2
本实施例提供了一种相较于实施例1中优化ESD防护性能的DCSCR器件的快速开启结构，其结构如图4所示，其与实施例1的唯一区别在于：This embodiment provides a fast opening structure of a DCSCR device that optimizes the ESD protection performance compared to Embodiment 1. Its structure is shown in FIG. 4 , and the only difference between it and Embodiment 1 is:
所述第二N型重掺杂区（132）与第一P型重掺杂区（131）之间、所述第三N型重掺杂区（133）与第一P型重掺杂区（131）之间、所述第二P型重掺杂区（142）与第一N型重掺杂区（141）之间、以及所述第三P型重掺杂区（143）与第一N型重掺杂区（141）之间均设置多晶硅栅进行隔离（代替STI），依次为第一、第二、第三、第四多晶硅栅151、152、153、154，多晶硅栅均由硅表面上的栅氧化层及其上覆盖的多晶硅层构成。Between the second N-type heavily doped region (132) and the first P-type heavily doped region (131), between the third N-type heavily doped region (133) and the first P-type heavily doped region (131), between the second P-type heavily doped region (142) and the first N-type heavily doped region (141), and between the third P-type heavily doped region (143) and the first One N-type heavily doped region (141) is provided with polysilicon gates for isolation (instead of STI), followed by the first, second, third and
如图4所示，本实例将实例1进行了进一步的结构优化，将N阱区130内的N型重掺杂区设置到P型重掺杂区131的上下方，之间均用多晶硅栅代替STI；同时将P阱140内的P型重掺杂区设置到N型重掺杂区141的上下方，之间均用多晶硅栅代替STI；将传统的STI-Diode改为Gate-diode，加快了二极管的开启速度，进一步提升了DCSCR的开启速度。As shown in Figure 4, this example further optimizes the structure of Example 1, and sets the N-type heavily doped region in the
以上所述，仅为本发明的具体实施方式，本说明书中所公开的任一特征，除非特别叙述，均可被其他等效或具有类似目的的替代特征加以替换；所公开的所有特征、或所有方法或过程中的步骤，除了互相排斥的特征和/或步骤以外，均可以任何方式组合。The above is only a specific embodiment of the present invention. Any feature disclosed in this specification, unless specifically stated, can be replaced by other equivalent or alternative features with similar purposes; all the disclosed features, or All method or process steps may be combined in any way, except for mutually exclusive features and/or steps.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826523A (en) * | 2010-04-14 | 2010-09-08 | 电子科技大学 | Silicon controlled rectifier electrostatic discharge protection circuit structure triggered by grid controlled diode |
| CN107731811A (en) * | 2017-09-06 | 2018-02-23 | 电子科技大学 | A kind of SCR device triggered by longitudinal BJT for ESD protection |
| CN110335866A (en) * | 2019-06-26 | 2019-10-15 | 电子科技大学 | A bidirectional low-trigger ESD protection device based on nanoscale integrated circuit technology |
| CN111524884A (en) * | 2020-04-15 | 2020-08-11 | 电子科技大学 | Improved LDMOS-SCR device for high-voltage ESD protection |
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| US8921943B2 (en) * | 2012-12-10 | 2014-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for ESD structures |
| US9024354B2 (en) * | 2013-08-06 | 2015-05-05 | Amazing Microelectronics Corp. | Silicon-controlled rectification device with high efficiency |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101826523A (en) * | 2010-04-14 | 2010-09-08 | 电子科技大学 | Silicon controlled rectifier electrostatic discharge protection circuit structure triggered by grid controlled diode |
| CN107731811A (en) * | 2017-09-06 | 2018-02-23 | 电子科技大学 | A kind of SCR device triggered by longitudinal BJT for ESD protection |
| CN110335866A (en) * | 2019-06-26 | 2019-10-15 | 电子科技大学 | A bidirectional low-trigger ESD protection device based on nanoscale integrated circuit technology |
| CN111524884A (en) * | 2020-04-15 | 2020-08-11 | 电子科技大学 | Improved LDMOS-SCR device for high-voltage ESD protection |
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