CN113871382B - DCSCR device for optimizing ESD protection performance - Google Patents
DCSCR device for optimizing ESD protection performance Download PDFInfo
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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Abstract
The invention belongs to the field of design of electrostatic discharge (ESD) protection devices, and particularly provides a DCSCR device with optimized ESD protection performance, which is used for meeting the requirements of an integrated circuit under an advanced process on low trigger voltage, high sensitivity, low parasitic capacitance, small area and the like of ESD protection. According to the invention, through improving the structure of the traditional DCSCR device, the N-type heavily doped region in the N-type well region is arranged above and below the P-type heavily doped region (sequentially arranged in the vertical direction (Y axis)), and the P-type heavily doped region in the P-type well is arranged above and below the N-type heavily doped region, so that the width of the diode is greatly reduced, and the area of the diode is effectively reduced; in addition, the trigger diode of the DCSCR is embedded above and below the active area of the trigger path of the SCR in the original position, so that the conducting path of the SCR is shortened, the on resistance and the parasitic capacitance are reduced, and the starting speed is improved; in summary, the invention realizes the reduction of the device area and the improvement of the device performance on the premise of not reducing the ESD protection capability.
Description
Technical Field
The invention belongs to the field of design of electrostatic Discharge (ESD) protection devices, in particular to a diode Direct-connected triggered silicon controlled rectifier (Direct-Connected Silicon-Controlled Rectifier is called DCSCR) device, and particularly provides a DCSCR device for optimizing ESD protection performance.
Background
An Electro-Static discharge (ESD) phenomenon refers to a charge transfer phenomenon occurring when objects having different electric potentials are close to or contact with each other, and a large current is generated during the discharge due to a very short discharge time; for integrated circuits, modern ICs are more susceptible to damage caused by electrostatic discharge (ESD), and such high currents can damage or even burn out internal devices, resulting in chip failure; the electrostatic discharge phenomenon is likely to occur in each link of the chip production, transportation and use, so that the ESD protection measures of the chip are indispensable for the reliability of the chip.
Full-chip ESD protection networks can be generally classified into three cases, each with advantages and disadvantages. For the analog circuit with small pin number, a local ESD protection network can be selected, a bus is not needed, and each pin can be independently protected; ESD protection based on a power rail has the advantages of small occupied area and strong process portability, but increases the complexity of chip design and verification; PAD-based ESD protection networks are mainly oriented towards chips with multiple types of ports. ESD protection networks based on Power rails are widely used in engineering, which use diodes as upper and lower end protection devices for I/O ports, and Power Clamp as a Power to ground ESD protection circuit. The diode has simple structure, is easy to use, is widely applied to an ESD protection structure, and is particularly aimed at digital signal ports and high-speed signal ports. In addition to meeting the protection window, parasitic capacitance is an important consideration for ESD protection structures. The parasitic capacitance of the series diode decreases proportionally with the number of series connections. The larger the number of series connection, the higher the turn-on voltage, the larger the on-resistance, and the ESD protection performance is affected.
DCSCR (Diode-connected silicon-controlled rectifier) is an SCR device triggered by Diode strings, has the advantages of small resistance, high robustness and the like, and can adjust trigger voltage through device stacking to meet different design window requirements, so that the DCSCR device is widely applied to ESD protection under advanced technology. The DCSCR device is equivalent to two diodes in series and can be used in place of the diodes in an ESD protection network. The trigger voltage of DCSCR is only about 1.4V, which is already the lowest turn-on voltage achievable by SCR type devices on silicon technology, and is well suited for the most advanced low voltage ESD window (e.g., 0.8V circuit under 14nm finfet technology); for relatively higher working voltage in the traditional planar CMOS process, DCSCR can be flexibly met in a stacking mode, and diode devices of I/O ports can be replaced in a full-chip ESD protection architecture based on a power rail, so that better parasitic capacitance characteristics are realized; on the other hand, in DCSCR, since the emitter junctions of the two transistors parasitic to the SCR structure are just on the auxiliary trigger path, the charging time (i.e. tcarges) is fast, which makes DCSCR have the advantage of fast turn-on speed.
With the progress of the semiconductor process, the semiconductor process enters the nano field, and the gate oxide breakdown voltage and the source drain breakdown voltage of the device are further reduced, so that the ESD protection device is required to have a lower window and stronger sensitivity; and integrated circuits employing advanced processes tend to operate at extremely high frequencies, which requires lower capacitance for ESD protection devices; integrated circuits of advanced technology also require a compact layout, which requires a small area for the ESD protection device; in general, integrated circuits under advanced processes require low trigger voltages, high sensitivity, low parasitic capacitance, and small area for ESD protection. Therefore, high performance ESD protection devices are particularly important.
Disclosure of Invention
The invention aims to provide a DCSCR device with optimized ESD protection performance, and by improving the structure of the traditional DCSCR device, the DCSCR device realizes small area, low on-resistance, low parasitic capacitance and high starting speed on the premise of not reducing the ESD protection capability of the DCSCR device, and is suitable for low-voltage ESD protection under a nanoscale process.
In order to achieve the above purpose, the first technical scheme adopted by the invention is as follows:
a DCSCR device that optimizes ESD protection performance, comprising:
a P-type silicon substrate (110), an N-type well region (130), a P-type well region (140) and an N-type deep well region (120) formed on the P-type silicon substrate (110); the P-type well region (140) is arranged in the N-type well region (130), and the lower part of the P-type well region is isolated from the P-type silicon substrate (110) through the N-type deep well region (120);
a second N-type heavily doped region (132), a first P-type heavily doped region (131) and a third N-type heavily doped region (133) are sequentially arranged in the N-type well region (130), and a second P-type heavily doped region (142), a first N-type heavily doped region (141) and a third P-type heavily doped region (143) are sequentially arranged in the P-type well region (140); the first P type heavily doped region (131) is connected with the Anode (Anode), and the first N type heavily doped region (141) is connected with the Cathode (Cathiode);
the second N-type heavily doped region (132), the first P-type heavily doped region (131) and the third N-type heavily doped region (133) are sequentially arranged along the vertical direction (Y axis), shallow trench isolation is respectively arranged between the second N-type heavily doped region (132) and the first P-type heavily doped region (131) and between the third N-type heavily doped region (133) and the first P-type heavily doped region (131); the second P-type heavy doping region (142), the first N-type heavy doping region (141) and the third P-type heavy doping region (143) are sequentially arranged along the vertical direction (Y axis), shallow trench isolation is respectively arranged between the second P-type heavy doping region (142) and the first N-type heavy doping region (141) and between the third P-type heavy doping region (143) and the first N-type heavy doping region (141); the first P-type heavy doping region (131) and the first N-type heavy doping region (141) are arranged in parallel along the horizontal direction (X axis), the second N-type heavy doping region (132) and the second P-type heavy doping region (142) are arranged in parallel along the horizontal direction (X axis) and are directly connected through metal, and the third N-type heavy doping region (133) and the third P-type heavy doping region (143) are arranged in parallel along the horizontal direction (X axis) and are directly connected through metal; shallow trench isolation is respectively arranged between the second N-type heavily doped region (132) and the second P-type heavily doped region (142) and between the third N-type heavily doped region (133) and the third P-type heavily doped region (143).
Further, shallow trench isolation between the second N-type heavily doped region (132) and the first P-type heavily doped region (131), between the third N-type heavily doped region (133) and the first P-type heavily doped region (131), between the second P-type heavily doped region (142) and the first N-type heavily doped region (141), and between the third P-type heavily doped region (143) and the first N-type heavily doped region (141) is replaced with polysilicon gates, respectively.
The invention has the beneficial effects that:
the invention provides an improved DCSCR device for low-voltage ESD protection, which is characterized in that the structure of a traditional DCSCR device is improved, an N-type heavily doped region in an N-type well region is arranged above and below a P-type heavily doped region (which are sequentially distributed in the vertical direction (Y axis)), the P-type heavily doped region in a P-type well is arranged above and below the N-type heavily doped region, the width of a diode is greatly reduced, and the area of the diode is effectively reduced; in addition, the trigger diode of the DCSCR is embedded above and below the active area of the trigger path of the SCR in the original position, so that the conducting path of the SCR is shortened, the on resistance and the parasitic capacitance are reduced, and the starting speed is improved; in summary, the invention realizes the reduction of the device area and the improvement of the device performance on the premise of not reducing the ESD protection capability.
Drawings
Fig. 1 is a schematic cross-sectional structure of a conventional DCSCR device.
Fig. 2 is a schematic top view of a conventional DCSCR device.
Fig. 3 is a schematic structural diagram of a DCSCR device for optimizing ESD protection performance according to embodiment 1 of the present invention.
Fig. 4 is a schematic structural diagram of a DCSCR device for optimizing ESD protection performance according to embodiment 2 of the present invention.
Detailed Description
The invention will be described in detail below with reference to the drawings and the detailed description.
Example 1
The present embodiment provides a DCSCR device for optimizing ESD protection performance, whose structure is shown in fig. 3, and includes:
a P-type silicon substrate (110), an N-type well region (130), a P-type well region (140) and an N-type deep well region (120) formed on the P-type silicon substrate (110); the P-type well region (140) is arranged in the N-type well region (130) and is isolated from the P-type silicon substrate (110) below the P-type well region through the N-type deep well region (120), namely the P-type well region (140) is surrounded by the N-type well region (130) and the N-type deep well region (120);
a second N-type heavily doped region (132), a first P-type heavily doped region (131) and a third N-type heavily doped region (133) are sequentially arranged in the N-type well region (130); wherein shallow trench isolation is arranged between the second N-type heavily doped region (132) and the first P-type heavily doped region (131), and shallow trench isolation is arranged between the third N-type heavily doped region (133) and the first P-type heavily doped region (131); the first P-type heavily doped region (131) is connected with an Anode (Anode);
a second P type heavily doped region (142), a first N type heavily doped region (141) and a third P type heavily doped region (143) are sequentially arranged in the P type well region (140); wherein shallow trench isolation is arranged between the second P-type heavily doped region (142) and the first N-type heavily doped region (141), and shallow trench isolation is arranged between the third P-type heavily doped region (143) and the first N-type heavily doped region (141); the first N-type heavily doped region (141) is connected with a Cathode (Cathode);
the second N-type heavily doped region (132), the first P-type heavily doped region (131) and the third N-type heavily doped region (133) are sequentially arranged along a vertical direction (Y axis), the second P-type heavily doped region (142), the first N-type heavily doped region (141) and the third P-type heavily doped region (143) are sequentially arranged along the vertical direction (Y axis), the first P-type heavily doped region (131) and the first N-type heavily doped region (141) are arranged in parallel along a horizontal direction (X axis), the second N-type heavily doped region (132) and the second P-type heavily doped region (142) are arranged in parallel along the horizontal direction (X axis), the second N-type heavily doped region (133) and the third P-type heavily doped region (143) are directly connected through metal, and the third N-type heavily doped region (133) and the third P-type heavily doped region (143) are arranged in parallel along the horizontal direction (X axis), and the second N-type heavily doped region and the third P-type heavily doped region (143) are directly connected through metal; shallow trench isolation is arranged between the first P type heavily doped region (131) and the first N type heavily doped region (141), shallow trench isolation is arranged between the second N type heavily doped region (132) and the second P type heavily doped region (142), and shallow trench isolation is arranged between the third N type heavily doped region (133) and the third P type heavily doped region (143).
In terms of working principle:
as shown in fig. 1 and 2, the diode of the traditional DCSCR device plays a role of auxiliary triggering, and the current discharge after opening mainly passes through the discharge path of the SCR; compared with the embodiment of the invention, as shown in fig. 3, the structure of the conventional DCSCR device is optimized, the N-type heavily doped region in the N-type well region 130 is arranged above and below the P-type heavily doped region 131 (sequentially arranged in the vertical direction (Y axis)), and STI is used to isolate each other; meanwhile, the P-type heavily doped region in the P-type well 140 is arranged above and below the N-type heavily doped region 141 (which are sequentially arranged in the vertical direction (Y axis)) and are isolated by STI; according to the embodiment, the width of the diode is reduced, the area of the diode is reduced, the trigger diode of the DCSCR is embedded above and below the active area of the trigger path of the SCR in the original position, the conducting path of the SCR is shortened, and the reduction of the area of the device, the reduction of the on-resistance and the parasitic capacitance are realized under the condition that the ESD protection capability of the device is not changed.
Example 2
This embodiment provides a fast turn-on structure of the DCSCR device with optimized ESD protection performance compared to embodiment 1, which is shown in fig. 4, and the only difference from embodiment 1 is that:
polysilicon gates are arranged between the second N-type heavy doping region (132) and the first P-type heavy doping region (131), between the third N-type heavy doping region (133) and the first P-type heavy doping region (131), between the second P-type heavy doping region (142) and the first N-type heavy doping region (141) and between the third P-type heavy doping region (143) and the first N-type heavy doping region (141) to isolate (replace STI), and the polysilicon gates are sequentially a first polysilicon gate 151, a second polysilicon gate 152, a third polysilicon gate 153 and a fourth polysilicon gate 154, and each polysilicon gate consists of a gate oxide layer on the surface of silicon and a polysilicon layer covered on each polysilicon gate oxide layer.
As shown in fig. 4, in this example, the structure of example 1 is further optimized, the N-type heavily doped region in the N-well region 130 is disposed above and below the P-type heavily doped region 131, and the STI is replaced by the polysilicon gate therebetween; meanwhile, the P-type heavily doped region in the P well 140 is arranged above and below the N-type heavily doped region 141, and the STI is replaced by a polysilicon gate; the traditional STI-Diode is changed into the Gate-Diode, so that the starting speed of the Diode is increased, and the starting speed of the DCSCR is further improved.
While the invention has been described in terms of specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the equivalent or similar purpose, unless expressly stated otherwise; all of the features disclosed, or all of the steps in a method or process, except for mutually exclusive features and/or steps, may be combined in any manner.
Claims (2)
1. A DCSCR device that optimizes ESD protection performance, comprising:
a P-type silicon substrate (110), an N-type well region (130), a P-type well region (140) and an N-type deep well region (120) formed on the P-type silicon substrate (110); the P-type well region (140) is arranged in the N-type well region (130), and the lower part of the P-type well region is isolated from the P-type silicon substrate (110) through the N-type deep well region (120);
a second N-type heavily doped region (132), a first P-type heavily doped region (131) and a third N-type heavily doped region (133) are sequentially arranged in the N-type well region (130), and a second P-type heavily doped region (142), a first N-type heavily doped region (141) and a third P-type heavily doped region (143) are sequentially arranged in the P-type well region (140); the first P type heavily doped region (131) is connected with the Anode (Anode), and the first N type heavily doped region (141) is connected with the Cathode (Cathiode);
the second N-type heavily doped region (132), the first P-type heavily doped region (131) and the third N-type heavily doped region (133) are sequentially arranged along the vertical direction (Y axis), shallow trench isolation is respectively arranged between the second N-type heavily doped region (132) and the first P-type heavily doped region (131) and between the third N-type heavily doped region (133) and the first P-type heavily doped region (131); the second P-type heavy doping region (142), the first N-type heavy doping region (141) and the third P-type heavy doping region (143) are sequentially arranged along the vertical direction (Y axis), shallow trench isolation is respectively arranged between the second P-type heavy doping region (142) and the first N-type heavy doping region (141) and between the third P-type heavy doping region (143) and the first N-type heavy doping region (141); the first P-type heavy doping region (131) and the first N-type heavy doping region (141) are arranged in parallel along the horizontal direction (X axis), the second N-type heavy doping region (132) and the second P-type heavy doping region (142) are arranged in parallel along the horizontal direction (X axis) and are directly connected through metal, and the third N-type heavy doping region (133) and the third P-type heavy doping region (143) are arranged in parallel along the horizontal direction (X axis) and are directly connected through metal; shallow trench isolation is respectively arranged between the second N-type heavily doped region (132) and the second P-type heavily doped region (142) and between the third N-type heavily doped region (133) and the third P-type heavily doped region (143).
2. The DCSCR device of claim 1, wherein shallow trench isolations between said second N-type heavily doped region (132) and said first P-type heavily doped region (131), between said third N-type heavily doped region (133) and said first P-type heavily doped region (131), between said second P-type heavily doped region (142) and said first N-type heavily doped region (141), and between said third P-type heavily doped region (143) and said first N-type heavily doped region (141) are replaced with polysilicon gates, respectively.
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| CN114497032B (en) * | 2022-04-02 | 2022-07-15 | 深圳市晶扬电子有限公司 | Compact electrostatic protection device and electrostatic protection circuit suitable for consumer electronics |
| CN114709210B (en) * | 2022-06-07 | 2022-09-02 | 深圳市晶扬电子有限公司 | Low clamping voltage electrostatic protection device suitable for nanoscale FinFET (field effect transistor) process |
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| CN101826523A (en) * | 2010-04-14 | 2010-09-08 | 电子科技大学 | Silicon controlled rectifier electrostatic discharge protection circuit structure triggered by grid controlled diode |
| CN107731811A (en) * | 2017-09-06 | 2018-02-23 | 电子科技大学 | A kind of SCR device triggered by longitudinal BJT for ESD protection |
| CN110335866A (en) * | 2019-06-26 | 2019-10-15 | 电子科技大学 | A kind of two-way low triggering ESD protective device based on nanometer-grade IC technique |
| CN111524884A (en) * | 2020-04-15 | 2020-08-11 | 电子科技大学 | Improved LDMOS-SCR device for high-voltage ESD protection |
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| US6770918B2 (en) * | 2001-09-11 | 2004-08-03 | Sarnoff Corporation | Electrostatic discharge protection silicon controlled rectifier (ESD-SCR) for silicon germanium technologies |
| US8921943B2 (en) * | 2012-12-10 | 2014-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for ESD structures |
| US9024354B2 (en) * | 2013-08-06 | 2015-05-05 | Amazing Microelectronics Corp. | Silicon-controlled rectification device with high efficiency |
| DE102016119813B4 (en) * | 2016-10-18 | 2024-03-28 | Infineon Technologies Ag | Electrostatic discharge protection structure and method of manufacturing an electrostatic discharge protection structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826523A (en) * | 2010-04-14 | 2010-09-08 | 电子科技大学 | Silicon controlled rectifier electrostatic discharge protection circuit structure triggered by grid controlled diode |
| CN107731811A (en) * | 2017-09-06 | 2018-02-23 | 电子科技大学 | A kind of SCR device triggered by longitudinal BJT for ESD protection |
| CN110335866A (en) * | 2019-06-26 | 2019-10-15 | 电子科技大学 | A kind of two-way low triggering ESD protective device based on nanometer-grade IC technique |
| CN111524884A (en) * | 2020-04-15 | 2020-08-11 | 电子科技大学 | Improved LDMOS-SCR device for high-voltage ESD protection |
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