CN111048508B - ESD or surge protection method of bidirectional LVTSCR - Google Patents
ESD or surge protection method of bidirectional LVTSCR Download PDFInfo
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims abstract description 11
- 238000002347 injection Methods 0.000 claims abstract description 203
- 239000007924 injection Substances 0.000 claims abstract description 203
- 239000002184 metal Substances 0.000 claims abstract description 129
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 76
- 229920005591 polysilicon Polymers 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000001052 transient effect Effects 0.000 claims abstract description 18
- 230000001629 suppression Effects 0.000 claims abstract description 12
- 238000002513 implantation Methods 0.000 claims description 36
- 230000001960 triggered effect Effects 0.000 claims description 8
- 230000009471 action Effects 0.000 claims description 6
- 238000007599 discharging Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 230000008901 benefit Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000007943 implant Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 4
- 238000011160 research Methods 0.000 description 4
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
- H01L27/0277—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor
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Abstract
The invention discloses an ESD (electro-static discharge) protection or anti-surge method of a bidirectional LVTSCR (Low Voltage thyristor switched capacitor), belonging to the field of electrostatic discharge protection and surge of an integrated circuit. The invention provides a protection device for transient voltage suppression or ESD (electro-static discharge) and application thereof, wherein the protection device comprises an SCR (silicon controlled rectifier), an NMOS (N-channel metal oxide semiconductor) and a metal wire, and the application example device mainly comprises a P substrate, a first N well, a second N well, a P well, a first P + injection region, a second P + injection region, a third P + injection region, a first N + injection region, a second N + injection region, a third N + injection region, a fourth N + injection region, a fifth N + injection region, a sixth N + injection region, a first polysilicon gate, a first thin gate oxide layer covered by the first polysilicon gate, a second polysilicon gate and a second thin gate oxide layer covered by the second polysilicon gate. The invention utilizes the advantage of strong ESD robustness of the SCR structure, can reduce the trigger voltage by introducing the NMOS structure and a plurality of SCR paths, enhances the ESD robustness of the device in unit area, and is beneficial to improving the ESD or surge protection efficiency of the circuit unit area.
Description
Technical Field
The invention belongs to the field of electrostatic discharge protection and surge of an integrated circuit, and relates to an ESD (electro-static discharge) protection or anti-surge method of a bidirectional LVTSCR (Low Voltage thyristor switched capacitor).
Background
Electrostatic discharge (ESD) or transient surge refers to a physical phenomenon of electrostatic charge transfer or rapid drop of potential between objects at different potentials, which is likely to cause functional disorder of an Integrated Circuit (IC) or a circuit system or failure of an electronic product. In order to reduce the losses of various industries caused by ESD and transient surge events, an ESD laboratory and a research team are established in each large company and colleges, and the losses caused by the ESD and the transient surge events are reduced. The state recently proposed the latest standard GB/T17626.2-2018 on ESD protection, where explicit regulations are made on the production environment, transportation process, test conditions, etc. of the IC, which is of guiding significance for reducing ESD and transient surge events and standardizing ESD protection. Therefore, the research on how to improve the ESD protection and surge resistance of the IC and the circuit system has the scientific research value, and the design of the novel ESD protection method is beneficial to promoting the development of the IC and even the electronic industry, and has very important significance for promoting the scientific and technological progress and the national economic development.
Silicon Controlled Rectifiers (SCRs) are ESD protection or anti-surge devices that are currently receiving much attention and have a large potential value, and they have a prominent advantage of high current discharging capability compared to commonly used diodes and gate-grounded NMOS (N-Metal-Oxide-Semiconductor). However, an ordinary SCR as a unidirectional protection device is equivalent to an ordinary diode under the action of reverse ESD stress or surge, the protection efficiency of the SCR cannot meet the design window of ESD protection or surge resistance, the transparency in a protected circuit is poor, the working performance of the protected circuit is affected, and functional disorder is easily caused, even the circuit is damaged and fails. In order to meet the increasingly complex IC design requirements, researchers have designed improved SCR devices with various specific functions, and bidirectional SCRs are a research focus therein, because bidirectional SCRs help solve the ESD protection problem of some positive and negative alternating stress ports. However, the common bidirectional SCR structure has a high trigger voltage and a large voltage hysteresis, and has the problems of difficult triggering and latch-up.
Disclosure of Invention
[ problem ] to
The invention aims at the problems of weak transparency in unidirectional ESD protection or anti-surge and high trigger voltage and easy latch-up in the existing bidirectional ESD protection.
[ solution ]
The invention provides a novel ESD or surge protection method of a bidirectional LVTSCR, which reduces the trigger voltage of a device by introducing an auxiliary trigger NMOS structure; the maintaining voltage of the device is improved by embedding an NPN triode; and the ESD robustness of the device is enhanced by designing a plurality of SCR current discharge paths. In addition, through the design of the circuit structure, the bidirectional ESD protection or anti-surge function can be realized on the premise of not greatly increasing the area of the device.
Specifically, the present invention provides a protection device useful for transient voltage suppression or ESD, comprising: the semiconductor device comprises an SCR, an NMOS and a metal wire, and further mainly comprises a P substrate, a first N well, a second N well, a P well, a first P + injection region, a second P + injection region, a third P + injection region, a first N + injection region, a second N + injection region, a third N + injection region, a fourth N + injection region, a fifth N + injection region, a sixth N + injection region, a first polysilicon gate, a first thin gate oxide layer covered by the first polysilicon gate, a second polysilicon gate and a second thin gate oxide layer covered by the second polysilicon gate;
preparing a first N well, a P well and a second N well on a P substrate, wherein the left edge of the P substrate is connected with the left edge of the first N well, the right side of the first N well is connected with the left side of the P well, the right side of the P well is connected with the left side of the second N well, and the right edge of the second N well is connected with the right edge of the P substrate;
a first P + injection region and a first N + injection region are sequentially arranged in the surface region of the first N well, a safety distance is kept between the first P + injection region and the left edge of the first N well, a safety distance is kept between the first N + injection region and the first P + injection region, a second N + injection region is arranged in the surface region where the first N well is connected with the P well, and a safety distance is arranged between the left side of the second N + injection region and the first N + injection region;
the surface area of the P trap is sequentially provided with a first polysilicon gate, a first thin gate oxide layer, a third N + injection area, a second P + injection area, a fourth N + injection area, a second polysilicon gate and a second thin gate oxide layer, wherein the first thin gate oxide layer, the third N + injection area, the second P + injection area and the third N + injection area are covered by the first polysilicon gate, the left side edge of the first polysilicon gate oxide layer is covered by the first polysilicon gate is connected with the right side edge of the third N + injection area, the safety interval is kept between the fourth N + injection area and the second P + injection area, the left side of the second polysilicon gate and the second thin gate oxide layer is covered by the second polysilicon gate is connected with the right side of the fourth N + injection area, the surface area where the P trap is connected with the second N trap is provided with a fifth N + injection area, the left side of the fifth N + injection region is connected with the second polysilicon gate and the right side of the second thin gate oxide layer covered by the second polysilicon gate;
a sixth N + injection region and a third P + injection region are sequentially arranged in the surface region of the second N well, a safety interval is kept between the sixth N + injection region and the fifth N + injection region, and a safety interval is kept between the third P + injection region and the sixth N + injection region;
metal lines are connected to the highly doped implanted regions, and a portion of the metal is used as a connecting line and an anode and a cathode of the device, wherein: the first P + injection region is connected with the first metal 1, the first N + injection region is connected with the second metal 1, the third N + injection region is connected with the fourth metal 1, the second P + injection region is connected with the eighth metal 1, the fourth N + injection region is connected with the third metal 1, the sixth N + injection region is connected with the fifth metal 1, the third P + injection region is connected with the sixth metal 1, the first polysilicon gate is connected with the seventh metal 1, and the second polysilicon gate is connected with the ninth metal 1; the seventh metal 1, the eighth metal 1 and the ninth metal 1 are connected with the tenth metal 1 of the connecting wire; the first metal 1, the second metal 1 and the third metal 1 are connected with the eleventh metal 1, and a first electrode is led out from the eleventh metal 1 and is used as a metal anode of the device; the fourth metal 1, the fifth metal 1 and the sixth metal 1 are connected with the twelfth metal 1, and a second electrode is led out from the twelfth metal 1 and used as a metal cathode of the device.
The beneficial technical effects of the invention are as follows:
(1) in the protection device provided by the invention, when the first electrode is connected with a high potential and the second electrode is grounded, the first P + injection region, the first N well, the second N + injection region, the P well and the third N + injection region form an SCR path for discharging ESD or surge in a forward direction, and when the first electrode is grounded and the second electrode is connected with a high potential, the third P + injection region, the second N well, the fifth N + injection region, the P well and the fourth N + injection region form an SCR path for discharging ESD or surge in a reverse direction.
(2) In the protection device provided by the invention, when the first electrode is connected with a high potential and the second electrode is grounded, the second N + injection region, the first polysilicon gate, the first thin gate oxide layer covered by the first polysilicon gate and the third N + injection region form a forward auxiliary triggered NMOS, so that the trigger voltage of the device can be reduced.
(3) In the protection device provided by the invention, the NPN tube is formed by the third N + injection region, the P well, the second P + injection region and the fourth N + injection region, so that the maintenance voltage can be improved and the latch-up risk can be reduced in the forward or reverse ESD protection or surge resistance.
(4) In the protection device provided by the invention, after the device is triggered and started, the first P + injection region, the first N well, the second N + injection region, the P well, the second N well and the sixth N + injection region form an extra SCR path for positive discharge of ESD or surge, and the third P + injection region, the second N well, the fifth N + injection region, the P well, the first N well and the first N + injection region form an extra SCR path for reverse discharge of ESD or surge, so that the robustness of the device can be enhanced.
(5) The technical scheme of the invention can be used for improving the reliability of the on-chip IC and the electronic product system.
Drawings
FIG. 1 is a cross-sectional block diagram of an exemplary device of the present invention;
FIG. 2 is a metal wiring diagram of an example device of the invention;
FIG. 3 is an equivalent circuit diagram of an exemplary device of the present invention under forward electrical stress;
fig. 4 is an equivalent circuit diagram of an example device of the invention under reverse electrical stress.
100: p substrate, 101: first N-well, 102: p-well, 103: second N-well, 104: first P + implant region, 105: first N + implant region, 106: second N + implant region, 107: third N + implant region, 108: second P + implant region, 109: fourth N + implant region, 110: fifth N + implant region, 111: sixth N + implant region, 112: third P + implant region, 113: first thin gate oxide covered by first polysilicon gate, 114: first polysilicon gate, 115: second thin gate oxide covered by second polysilicon gate, 116: a second polysilicon gate;
201: first metal 1, 202: second metal 1, 203: third metal 1, 204: fourth metal 1, 205: fifth metal 1, 206: sixth metal 1, 207: seventh metal 1, 208: eighth metal 1, 209: ninth metal 1, 210: tenth metal 1, 211: eleventh metal 1, 212: a twelfth metal 1;
301: first electrode, 302: a second electrode.
Detailed Description
The invention is described in further detail below with reference to example 1 of the accompanying drawings:
example 1
The present embodiments relate to ESD or surge protection methods that may be used for transient voltage suppression or ESD protection devices, and novel bidirectional LVTSCRs. The strong ESD robustness advantage of the SCR structure is utilized, a plurality of SCR paths are introduced to discharge current, and NMOS is introduced to assist in triggering the SCR, so that the trigger voltage is reduced, the voltage hysteresis amplitude is reduced, the latch-up effect of the device in the ESD protection or anti-surge process is avoided, and the ESD protection or anti-surge efficiency is improved.
The cross-sectional structure of the device of the present invention is shown in fig. 1, and the transient voltage suppressor mainly includes a P substrate 100, a first N well 101, a second N well 103, a P well 102, a first P + implantation region 104, a second P + implantation region 108, a third P + implantation region 112, a first N + implantation region 105, a second N + implantation region 106, a third N + implantation region 107, a fourth N + implantation region 109, a fifth N + implantation region 110, a sixth N + implantation region 111, a first polysilicon gate 114, a first thin gate oxide layer 113 covering the first N + implantation region, a second polysilicon gate 116, and a second thin gate oxide layer 115 covering the second N + implantation region 111.
A first N well 101, a P well 102 and a second N well 103 are prepared on a P substrate 100, the left edge of the P well 102 is connected with the right edge of the first N well 101, the left side of the first N well 101 is connected with the left side of the P substrate 100, the right side of the P well 102 is connected with the left side of the second N well 103, and the right edge of the second N well 103 is connected with the right edge of the P substrate 100.
A first P + injection region 104 and a first N + injection region 105 are sequentially arranged on the surface region of the first N well 101, a safety distance is kept between the first P + injection region 104 and the left edge of the first N well 101, and a safety distance is kept between the first N + injection region 105 and the first P + injection region 104; in the surface region where the first N well 101 and the P well 102 are connected, a second N + implantation region 106 is provided, and a space is provided between the left side of the second N + implantation region 106 and the first N + implantation region 105.
A first polysilicon gate 114, a first thin gate oxide layer 113, a third N + injection region 107, a second P + injection region 108, a fourth N + injection region 109, a second polysilicon gate 116 and a second thin gate oxide layer 115 covered by the first polysilicon gate 114 are sequentially arranged in the surface region of the P well 102, the left side edge of the first polysilicon gate 114 and the first thin gate oxide layer 113 covered by the first polysilicon gate 114 are connected with the right side edge of the second N + injection region 106, the right side of the first polysilicon gate 114 and the first thin gate oxide layer 113 covered by the first polysilicon gate 114 are connected with the left side edge of the third N + injection region 107, a safety spacing is maintained between the second P + implant region 108 and the third N + implant region 107, a safety interval is kept between the fourth N + implantation region 109 and the second P + implantation region 108, and the second polysilicon gate 116 and the left side of the second thin gate oxide layer 115 covered by the second polysilicon gate are connected with the right side of the fourth N + implantation region 109; in the surface region where the P-well 102 is connected to the second N-well 103, a fifth N + implantation region 110 is disposed, and the left side of the fifth N + implantation region 110 is connected to the second polysilicon gate 116 and the right side of the second thin gate oxide layer 115 covered by the second polysilicon gate 116.
A sixth N + implantation region 111 and a third P + implantation region 112 are sequentially disposed in a surface region of the second N well 103, a safety interval is maintained between the sixth N + implantation region 111 and the fifth N + implantation region 110, and a safety interval is maintained between the third P + implantation region 112 and the sixth N + implantation region 111.
The metal connection diagram of the device of this embodiment is shown in fig. 2, where the metal line is connected to the highly doped implantation region, and part of the metal is used as the connection line and the anode and cathode of the device, where: the first P + injection region 104 is connected with a first metal 1201, the first N + injection region 105 is connected with a second metal 1202, the third N + injection region 107 is connected with a fourth metal 1204, the second P + injection region 108 is connected with an eighth metal 1208, the fourth N + injection region 109 is connected with a third metal 1203, the sixth N + injection region 111 is connected with a fifth metal 1205, the third P + injection region 112 is connected with a sixth metal 1206, the first polysilicon gate 114 is connected with a seventh metal 1207, and the second polysilicon gate 116 is connected with a ninth metal 1209; the seventh metal 1207, the eighth metal 1208 and the ninth metal 1209 are connected to the tenth metal 1210 of the connection line; the first metal 1201, the second metal 1202 and the third metal 1203 are connected with the eleventh metal 1211, and the first electrode 301 is led out from the eleventh metal 1211 and is used as a metal anode of the device; the fourth metal 1204, the fifth metal 1205 and the sixth metal 1206 are connected to the twelfth metal 1212, and the second electrode 302 is led out from the twelfth metal 1212 and used as a metal cathode of the device.
The equivalent circuit diagram of the device under the action of the forward electrical stress is shown in fig. 3, when the first electrode 301 is connected with high potential and the second electrode 302 is grounded, the first P + injection region 104, the first N well 101, the second N + injection region 106 and the P well 102 can form a PNP triode T1The first N well 101, the second N + injection region 106, the P well 102 and the third N + injection region 107 can form an NPN transistor T2Composed of PNP triode T1And NPN triode T2The forward SCR leakage path is formed, and the auxiliary trigger NMOS formed by the second N + injection region 106, the first polysilicon gate 114, the first thin gate oxide layer 113 covered by the second N + injection region and the third N + injection region 107 can reduce the trigger voltage of the device, the gates of the auxiliary trigger NMOS are all connected to the second P + injection region 108 through metal wires, when the device is under the action of electrical stress, the substrate leakage current can provide weak potential for the gates of the auxiliary trigger NMOS through the substrate resistor, and the device can be promoted to be quickly started. PNP triode T1And an NPN triode T composed of a first N well 101, a second N + injection region 106, a P well 102, a second N well 103 and a sixth N + injection region 1113An additional SCR path can be formed, and the unit area ESD or surge resistance between the chip pins can be improved.
The equivalent circuit diagram of the device under the action of the reverse electrical stress is shown in fig. 4, when the first electrode 301 is grounded and the second electrode 302 is connected with a high potential, the third P + injection region 112, the second N well 103, the fifth N + injection region 110 and the P well 102 can form a PNP triode T1The second N well 103, the fifth N + injection region 110, the P well 102 and the fourth N + injection region 109 may form an NPN transistor T2Composed of PNP triode T1And NPN triode T2An inverse SCR leakage path is formed, and an auxiliary trigger NMOS is formed by the fifth N + injection region 110, the second polysilicon gate 116, the second thin gate oxide layer 115 covered by the fifth N + injection region and the fourth N + injection region 109, so that the trigger voltage of the device can be reduced, the gates of the auxiliary trigger NMOS are all connected to the second P + injection region 108 through metal wires, and when the device is subjected to the action of electrical stress, the substrate leakage current can provide weak potential for the gates of the auxiliary trigger NMOS through the substrate resistor, so that the device can be promoted to be rapidly started. PNP triode T1And a second N well 103, a fifth N + wellAn NPN triode T composed of an implantation region 110, a P well 102, a first N well 101 and a first N + injection region 1053An additional SCR path can be formed, and the unit area ESD or surge resistance between the chip pins can be improved.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A protection device for transient voltage suppression or ESD, characterized by: the device comprises an SCR, an NMOS and a metal wire, wherein the SCR and the NMOS comprise a P substrate (100), a first N well (101), a second N well (103), a P well (102), a first P + injection region (104), a second P + injection region (108), a third P + injection region (112), a first N + injection region (105), a second N + injection region (106), a third N + injection region (107), a fourth N + injection region (109), a fifth N + injection region (110), a sixth N + injection region (111), a first polysilicon gate (114), a first thin gate oxide layer (113) covered by the first polysilicon gate (114), a second polysilicon gate (116) covered by the second polysilicon gate and a second thin gate oxide layer (115) covered by the first polysilicon gate (114);
preparing a first N well (101), a P well (102) and a second N well (103) on a P substrate (100), wherein the left edge of the P substrate (100) is connected with the left edge of the first N well (101), the right side of the first N well (101) is connected with the left side of the P well (102), the right side of the P well (102) is connected with the left side of the second N well (103), and the right edge of the second N well (103) is connected with the right edge of the P substrate (100);
a first P + injection region (104) and a first N + injection region (105) are sequentially arranged on the surface region of the first N well (101), a safety distance is kept between the first P + injection region (104) and the left side edge of the first N well (101), a safety distance is kept between the first N + injection region (105) and the first P + injection region (104), a second N + injection region (106) is arranged on the surface region where the first N well (101) is connected with the P well (102), and a safety distance is arranged between the left side of the second N + injection region (106) and the first N + injection region (105);
a first polysilicon gate (114), a first thin gate oxide layer (113), a third N + injection region (107), a second P + injection region (108), a fourth N + injection region (109), a second polysilicon gate (116) and a second thin gate oxide layer (115) which are covered by the first polysilicon gate (114), the left edge of the first thin gate oxide layer (113) which is covered by the first polysilicon gate (114) is connected with the right edge of the second N + injection region (106), the right edge of the first polysilicon gate (114) and the first thin gate oxide layer (113) which is covered by the first polysilicon gate (114) is connected with the left edge of the third N + injection region (107), a safety interval is kept between the second P + injection region (108) and the third N + injection region (107), and a safety interval is kept between the fourth N + injection region (109) and the second P + injection region (108), the left side of the second polysilicon gate (116) and the second thin gate oxide layer (115) covered by the second polysilicon gate is connected with the right side of the fourth N + injection region (109), a fifth N + injection region (110) is arranged in the surface region where the P well (102) is connected with the second N well (103), and the left side of the fifth N + injection region (110) is connected with the second polysilicon gate (116) and the right side of the second thin gate oxide layer (115) covered by the second polysilicon gate;
a sixth N + injection region (111) and a third P + injection region (112) are sequentially arranged on the surface region of the second N well (103), a safety distance is kept between the sixth N + injection region (111) and the fifth N + injection region (110), and a safety distance is kept between the third P + injection region (112) and the sixth N + injection region (111);
the metal wire is connected with the high-doped injection region, and part of metal is used as a connecting wire and an anode and a cathode of the device, wherein: the first P + injection region (104) is connected with the first metal 1(201), the first N + injection region (105) is connected with the second metal 1(202), the third N + injection region (107) is connected with the fourth metal 1(204), the second P + injection region (108) is connected with the eighth metal 1(208), the fourth N + injection region (109) is connected with the third metal 1(203), the sixth N + injection region (111) is connected with the fifth metal 1(205), the third P + injection region (112) is connected with the sixth metal 1(206), the first polysilicon gate (114) is connected with the seventh metal 1(207), and the second polysilicon gate (116) is connected with the ninth metal 1 (209);
the seventh metal 1(207), the eighth metal 1(208) and the ninth metal 1(209) are connected with the tenth metal 1(210) of the connecting line;
the first metal 1(201), the second metal 1(202) and the third metal 1(203) are connected with the eleventh metal 1(211), and a first electrode (301) is led out from the eleventh metal 1(211) and is used as a metal anode of the device;
the fourth metal 1(204), the fifth metal 1(205) and the sixth metal 1(206) are connected with the twelfth metal 1(212), and a second electrode (302) is led out from the twelfth metal 1(212) and is used as a metal cathode of the device.
2. A protection device for transient voltage suppression or ESD as claimed in claim 1, wherein: when the first electrode (301) is connected with a high potential and the second electrode (302) is grounded, an SCR path for discharging ESD or surge in a forward direction is formed by the first P + injection region (104), the first N well (101), the second N + injection region (106), the P well (102) and the third N + injection region (107), when the first electrode (301) is grounded and the second electrode (302) is connected with a high potential, an SCR path for discharging ESD or surge in a reverse direction is formed by the third P + injection region (112), the second N well (103), the fifth N + injection region (110), the P well (102) and the fourth N + injection region (109), and internal conduction current paths of the device are the same under the action of forward and reverse electrical stress, and the structure of the device has bidirectional symmetry and is used for improving the unit area ESD or anti-surge capacity between chip pins.
3. A protection device for transient voltage suppression or ESD as claimed in claim 1, wherein: when the first electrode (301) is connected with a high potential and the second electrode (302) is grounded, a forward auxiliary triggered NMOS is formed by the second N + injection region (106), the first polysilicon gate (114) and the first thin gate oxide layer (113) and the third N + injection region (107) which are covered by the first N + injection region, and is used for reducing the trigger voltage of the device, when the first electrode (301) is grounded and the second electrode (302) is connected with a high potential, a reverse auxiliary triggered NMOS is formed by the fifth N + injection region (110), the second polysilicon gate (116) and the second thin gate oxide layer (115) and the fourth N + injection region (109) which are covered by the second polysilicon gate (116) and the second thin gate oxide layer (115) and the fourth N + injection region, and is used for reducing the trigger voltage of the device, and the gates of the forward auxiliary triggered NMOS and the reverse triggered NMOS are connected to the second P + injection region (108) through metal wires, and when the device is subjected to an electric stress, the substrate leakage current provides a weak potential for the gate of the auxiliary triggered NMOS through the substrate resistor, for facilitating rapid turn-on of the device.
4. A protection device for transient voltage suppression or ESD as claimed in claim 1, wherein: an NPN tube is formed by the third N + injection region (107), the P well (102), the second P + injection region (108) and the fourth N + injection region (109) and is used for improving the maintaining voltage in forward or reverse ESD protection or anti-surge.
5. A protection device for transient voltage suppression or ESD as claimed in claim 1, wherein: after the device is triggered and started, an additional SCR path for positive discharge of ESD or surge is formed by the first P + injection region (104), the first N well (101), the second N + injection region (106), the P well (102), the second N well (103) and the sixth N + injection region (111), and an additional SCR path for reverse discharge of ESD or surge is formed by the third P + injection region (112), the second N well (103), the fifth N + injection region (110), the P well (102), the first N well (101) and the first N + injection region (105), so that the robustness of the device is enhanced.
6. Use of a protection device for transient voltage suppression or ESD according to any one of claims 1 to 5 for electrostatic discharge or transient surge protection.
7. An integrated circuit comprising a protection device for transient voltage suppression or ESD as claimed in any one of claims 1 to 5.
8. A method of manufacturing a protection device for transient voltage suppression or ESD as claimed in any one of claims 1 to 5.
9. An ESD or surge protection method of a bidirectional LVTSCR is characterized in that the triggering voltage of a device is reduced by introducing an auxiliary triggering NMOS structure; the maintaining voltage of the device is improved by embedding an NPN triode; a plurality of SCR current discharge paths are designed, so that the ESD robustness of the device is enhanced;
the ESD or surge protection method of the bidirectional LVTSCR is implemented based on the protection device for transient voltage suppression or ESD of any one of claims 1 to 5, the protection device comprises an SCR, an NMOS and a metal line, the SCR and the NMOS comprise a P substrate (100), a first N well (101), a second N well (103), a P well (102), a first P + implantation region (104), a second P + implantation region (108), a third P + implantation region (112), a first N + implantation region (105), a second N + implantation region (106), a third N + implantation region (107), a fourth N + implantation region (109), a fifth N + implantation region (110), a sixth N + implantation region (111), a first polysilicon gate (114) and a first thin gate oxide layer (113), a second polysilicon gate (116) and a second thin gate oxide layer (115) covered thereby;
preparing a first N well (101), a P well (102) and a second N well (103) on a P substrate (100), wherein the left edge of the P substrate (100) is connected with the left edge of the first N well (101), the right side of the first N well (101) is connected with the left side of the P well (102), the right side of the P well (102) is connected with the left side of the second N well (103), and the right edge of the second N well (103) is connected with the right edge of the P substrate (100);
a first P + injection region (104) and a first N + injection region (105) are sequentially arranged on the surface region of the first N well (101), a safety distance is kept between the first P + injection region (104) and the left side edge of the first N well (101), a safety distance is kept between the first N + injection region (105) and the first P + injection region (104), a second N + injection region (106) is arranged on the surface region where the first N well (101) is connected with the P well (102), and a safety distance is arranged between the left side of the second N + injection region (106) and the first N + injection region (105);
a first polysilicon gate (114), a first thin gate oxide layer (113), a third N + injection region (107), a second P + injection region (108), a fourth N + injection region (109), a second polysilicon gate (116) and a second thin gate oxide layer (115) which are covered by the first polysilicon gate (114), the left edge of the first thin gate oxide layer (113) which is covered by the first polysilicon gate (114) is connected with the right edge of the second N + injection region (106), the right edge of the first polysilicon gate (114) and the first thin gate oxide layer (113) which is covered by the first polysilicon gate (114) is connected with the left edge of the third N + injection region (107), a safety interval is kept between the second P + injection region (108) and the third N + injection region (107), and a safety interval is kept between the fourth N + injection region (109) and the second P + injection region (108), the left side of the second polysilicon gate (116) and the second thin gate oxide layer (115) covered by the second polysilicon gate is connected with the right side of the fourth N + injection region (109), a fifth N + injection region (110) is arranged in the surface region where the P well (102) is connected with the second N well (103), and the left side of the fifth N + injection region (110) is connected with the second polysilicon gate (116) and the right side of the second thin gate oxide layer (115) covered by the second polysilicon gate;
a sixth N + injection region (111) and a third P + injection region (112) are sequentially arranged on the surface region of the second N well (103), a safety distance is kept between the sixth N + injection region (111) and the fifth N + injection region (110), and a safety distance is kept between the third P + injection region (112) and the sixth N + injection region (111);
the metal wire is connected with the high-doped injection region, and part of metal is used as a connecting wire and an anode and a cathode of the device, wherein: the first P + injection region (104) is connected with the first metal 1(201), the first N + injection region (105) is connected with the second metal 1(202), the third N + injection region (107) is connected with the fourth metal 1(204), the second P + injection region (108) is connected with the eighth metal 1(208), the fourth N + injection region (109) is connected with the third metal 1(203), the sixth N + injection region (111) is connected with the fifth metal 1(205), the third P + injection region (112) is connected with the sixth metal 1(206), the first polysilicon gate (114) is connected with the seventh metal 1(207), and the second polysilicon gate (116) is connected with the ninth metal 1 (209);
the seventh metal 1(207), the eighth metal 1(208) and the ninth metal 1(209) are connected with the tenth metal 1(210) of the connecting line;
the first metal 1(201), the second metal 1(202) and the third metal 1(203) are connected with the eleventh metal 1(211), and a first electrode (301) is led out from the eleventh metal 1(211) and is used as a metal anode of the device;
the fourth metal 1(204), the fifth metal 1(205) and the sixth metal 1(206) are connected with the twelfth metal 1(212), and a second electrode (302) is led out from the twelfth metal 1(212) and is used as a metal cathode of the device.
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| CN116093104B (en) * | 2023-03-28 | 2024-06-14 | 江南大学 | Electrostatic and surge protection circuit applied to direct current/direct current conversion chip |
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| CN108807376B (en) * | 2018-07-03 | 2021-05-14 | 江南大学 | Bidirectional transient voltage suppressor of low-voltage MOS auxiliary trigger SCR |
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