CN111223855B - Method for improving ESD protection performance of circuit system by using gate isolation technology - Google Patents
Method for improving ESD protection performance of circuit system by using gate isolation technology Download PDFInfo
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- CN111223855B CN111223855B CN201911132334.3A CN201911132334A CN111223855B CN 111223855 B CN111223855 B CN 111223855B CN 201911132334 A CN201911132334 A CN 201911132334A CN 111223855 B CN111223855 B CN 111223855B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
Abstract
The invention discloses a method for improving ESD protection performance of a circuit system by using a gate isolation technology, belonging to the field of electrostatic discharge protection and anti-surge of an integrated circuit. The device comprises a P substrate, an N trap, a P trap, a first N + injection region, a second N + injection region, a third N + injection region, a first P + injection region, a second P + injection region, a first polysilicon gate and a first thin gate oxide layer covered by the first polysilicon gate, a second polysilicon gate and a second thin gate oxide layer covered by the second polysilicon gate, a third polysilicon gate and a third thin gate oxide layer covered by the third polysilicon gate, a fourth polysilicon gate and a fourth thin gate oxide layer covered by the fourth polysilicon gate, a fifth polysilicon gate and a fifth thin gate oxide layer covered by the fifth polysilicon gate, a sixth polysilicon gate and a sixth thin gate oxide layer covered by the sixth polysilicon gate. The invention utilizes the gate isolation technology, improves the maintaining voltage and enhances the latch-up resistance of the device in the ESD protection or surge resistance process.
Description
Technical Field
The invention belongs to the field of electrostatic discharge protection and anti-surge of an integrated circuit, relates to an ESD protection or anti-surge method, and particularly relates to a method for improving the ESD protection performance of a circuit system by using a gate isolation technology.
Background
Electrostatic discharge (ESD) or transient surge is a common phenomenon in daily life, which not only brings trouble to life but also affects scientific research activities and industrial production, and in recent years, due to special requirements in the aerospace and military fields and rapid development of consumer electronics industries, various microelectronic devices have become more and more miniaturized, and the requirements for multifunction, low power consumption and high reliability have been increasingly increased. With the integration level of the circuit and the thinner and thinner insulating layer, the width and the spacing of the interconnection wires are smaller and smaller, and the resistance of the circuit system to the ESD or transient surge is seriously weakened while the circuit system meets the comprehensive requirements. Statistically, ESD and transient surge factors account for up to 37% of the factors that cause Integrated Circuit (IC) damage.
In order to reduce the economic loss of the ESD and the transient surge event to the electronic product, various electrostatic protection means are widely applied to the production, transportation, packaging, testing and other links of the electronic product. In recent 30 years, the design and research of various off-chip Transient Voltage Suppressors (TVS) and on-chip ESD protection or anti-surge structures are being improved and innovated continuously, and the importance of ESD and transient surge protection of ICs is particularly prominent under the demand of increasingly portable electronic products. Therefore, the research on the ESD protection and surge resistance of electronic products, particularly ICs, not only has important scientific research value, but also is beneficial to reducing national economic loss, and has very important significance for promoting scientific and technological progress and national economic development.
Silicon Controlled Rectifiers (SCRs) have recently become a research hotspot in the field of ESD protection or surge protection due to their outstanding advantages of simple structure, fast turn-on, low parasitics, and strong robustness. Part of the research efforts have been applied in industrial practice. However: the common SCR has the defects of high trigger voltage, low holding voltage, easy latching and the like, is greatly restricted in industrial application, has electrical characteristics exceeding the design window of ESD protection or surge resistance, reduces the transparency, influences the working performance of a normal circuit, and even possibly causes the damage and failure of the circuit. In order to reduce the trigger voltage of the SCR, researchers have proposed an improved LVTSCR in 2005, which greatly reduced the trigger voltage. But LVTSCR also has a certain risk of latching. Therefore, increasing the holding voltage of the SCR and reducing the latch-up risk are important and difficult points in the current research of SCR-type ESD or surge protection technology.
Disclosure of Invention
[ problem ] to
Aiming at the problems of weak transparency, low trigger voltage and easy latch-up existing in ESD protection or anti-surge.
[ solution ]
The invention provides a method for improving the ESD protection performance of a circuit system by using a gate isolation technology, which can be used for improving the ESD protection performance of the circuit system. The invention utilizes the advantage of strong ESD robustness of the SCR structure, improves the maintaining voltage by introducing the grid isolation structure, avoids the latch-up effect of the device in the ESD protection or anti-surge process, can enhance the ESD robustness of the device in unit area, and is beneficial to improving the ESD protection or anti-surge efficiency.
The ESD protection device constructed by applying the method for improving the ESD protection performance of the circuit system by utilizing the gate isolation technology comprises an SCR, a GGNMOS, an isolation gate structure and a metal wire, and mainly comprises a P substrate, an N well, a P well, a first N + injection region, a second N + injection region, a third N + injection region, a first P + injection region, a second P + injection region, a first polysilicon gate and a first thin gate oxide layer covered by the first polysilicon gate, a second polysilicon gate and a second thin gate oxide layer covered by the second polysilicon gate, a third polysilicon gate and a third thin gate oxide layer covered by the third polysilicon gate, a fourth polysilicon gate and a fourth thin gate oxide layer covered by the fourth polysilicon gate, a fifth polysilicon gate and a fifth thin gate oxide layer covered by the fifth polysilicon gate, a sixth polysilicon gate and a sixth thin gate oxide layer covered by the sixth polysilicon gate;
preparing an N trap and a P trap on a P substrate, wherein the left edge of the P substrate is connected with the left edge of the N trap, the right side of the N trap is connected with the left side of the P trap, and the right edge of the P trap is connected with the right edge of the P substrate;
an isolation gate structure is arranged in the surface area of the P trap, the isolation gate structure comprises a first polysilicon gate, a first thin gate oxide layer covered by the first polysilicon gate, a second thin gate oxide layer covered by the second polysilicon gate, a third thin gate oxide layer covered by the third polysilicon gate, a fourth thin gate oxide layer covered by the fourth polysilicon gate, a fifth thin gate oxide layer covered by the fifth polysilicon gate, a sixth polysilicon gate and a sixth thin gate oxide layer covered by the sixth polysilicon gate, wherein the first polysilicon gate, the first thin gate oxide layer covered by the first polysilicon gate, the second thin gate oxide layer covered by the second polysilicon gate are aligned in the width direction of the device, a safety interval is arranged in the width direction of the device, the third polysilicon gate and the third thin gate oxide layer covered by the third polysilicon gate and the third thin gate oxide layer are respectively arranged at a safety interval with the upper edge and the lower edge of the P trap, and the fourth polysilicon gate, the fourth thin gate oxide layer covered by the fourth polysilicon gate and the fifth polysilicon gate are arranged along the width direction of the device The device is aligned in the horizontal direction, and a safety interval is arranged in the width direction of the device;
the surface area of the N trap is sequentially provided with a first N + injection area and a first P + injection area, a certain safety interval is kept between the first N + injection area and the left edge of the N trap, a certain safety interval is kept between the first P + injection area and the first N + injection area, a second N + injection area is arranged in the surface area where the N trap is connected with the P trap, and a safety interval is arranged between the left side of the second N + injection area and the first P + injection area;
the right side of the second N + injection region is connected with the sixth polysilicon gate and the left side of the sixth thin gate oxide layer covered by the sixth polysilicon gate, the first polysilicon gate and the first thin gate oxide layer covered by the first polysilicon gate, the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate, the third polysilicon gate and the third thin gate oxide layer covered by the third polysilicon gate, the fourth polysilicon gate and the fourth thin gate oxide layer covered by the fourth polysilicon gate, the fifth polysilicon gate and the fifth thin gate oxide layer covered by the fifth polysilicon gate are all located in the second N + injection region, wherein: along the length direction of the device, a space is arranged between the first polysilicon gate and the first thin gate oxide layer covered by the first polysilicon gate as well as the third polysilicon gate and the third thin gate oxide layer covered by the third polysilicon gate, a space is arranged between the third polysilicon gate and the third thin gate oxide layer covered by the third polysilicon gate as well as the fifth polysilicon gate and the fifth thin gate oxide layer covered by the fifth polysilicon gate, and a space is arranged between the fifth polysilicon gate and the fifth thin gate oxide layer covered by the fifth polysilicon gate as well as the sixth polysilicon gate and the sixth thin gate oxide layer covered by the sixth polysilicon gate;
a third N + injection region and a second P + injection region are sequentially arranged on the right side of a sixth polycrystalline silicon gate and a sixth thin gate oxide layer covered by the sixth polycrystalline silicon gate in the surface region of the P well, the right side of the sixth polycrystalline silicon gate and the sixth thin gate oxide layer covered by the sixth polycrystalline silicon gate are connected with the left side of the third N + injection region, a space is formed between the second P + injection region and the third N + injection region, and a certain safety space is kept between the second P + injection region and the edge of the P well;
the metal wire is connected with the high-doped injection region, and part of metal is used as an anode and a cathode of the device, wherein: the first N + injection region is connected with the first metal 1, the first P + injection region is connected with the second metal 1, the sixth polysilicon gate is connected with the fourth metal 1, the third N + injection region is connected with the fifth metal 1, and the second P + injection region is connected with the sixth metal 1;
the first metal 1 and the second metal 1 are connected with the third metal 1, and a first electrode is led out from the third metal 1 and is used as a metal anode of the device;
the fourth metal 1, the fifth metal 1 and the sixth metal 1 are connected with the seventh metal 1, and a second electrode is led out from the seventh metal 1 and is used as a metal cathode of the device.
The beneficial technical effects of the invention are as follows:
(1) the ESD protection device combined with the gate isolation technology provided by the invention utilizes the isolation gate technology to set a first polysilicon gate and a first thin gate oxide layer covered by the first polysilicon gate, a second polysilicon gate and a second thin gate oxide layer covered by the second polysilicon gate, a third polysilicon gate and a third thin gate oxide layer covered by the third polysilicon gate, a fourth polysilicon gate and a fourth thin gate oxide layer and a fifth polysilicon gate covered by the fourth polysilicon gate as well as a fifth thin gate oxide layer covered by the fifth polysilicon gate in the surface area of a second N + injection region, the specific arrangement mode is as claimed in claim 1, the internal current trend of the device is controlled by the isolation gate, the current path is prolonged, and the ESD or electric over-stress protection performance of the device can be improved on the premise of not increasing the area of the device; the current conduction capability of the device and the robustness of ESD protection and electric overstress protection are adjusted by controlling the distance between the first polysilicon gate and the first thin gate oxide layer covered by the first polysilicon gate, the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate, and the distance between the fourth polysilicon gate and the fourth thin gate oxide layer covered by the fourth polysilicon gate, the fifth polysilicon gate and the fifth thin gate oxide layer covered by the fifth polysilicon gate in the width direction of the device.
(2) The ESD protection device combined with the grid isolation technology provided by the invention comprises the following components in the width direction of the device: the ESD robustness of the device can be changed by adjusting the distance between the first polysilicon gate and the first thin gate oxide layer covered by the first polysilicon gate, and the distance between the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate; and the opening speed and the triggering characteristic of the device can be changed by adjusting the distance between the fourth polysilicon gate and the fourth thin gate oxide layer covered by the fourth polysilicon gate and the fifth thin gate oxide layer covered by the fifth polysilicon gate.
(3) The ESD protection device combined with the gate isolation technology provided by the invention has a GGNMOS structure consisting of a groove type second N + injection region, a sixth polysilicon gate, a sixth thin gate oxide layer covered by the sixth polysilicon gate and a third N + injection region, can adjust the trigger voltage and ESD robustness of the device, and realizes the function of controllable voltage hysteresis amplitude.
Drawings
FIG. 1 is a schematic diagram of the structure of an example device of the present invention;
FIG. 2 is a metal wiring diagram of an example device of the invention;
FIG. 3 is a layout and current path designation for an exemplary device of the present invention;
101: p substrate, 102: n-well, 103: p-well, 104: first N + implant region, 105: first P + implant region, 106: second N + implant region, 107: third N + implant region, 108: second P + implant region, 110: first polysilicon gate, 109: first thin gate oxide covered with first polysilicon gate, 112: second polysilicon gate, 111: second thin gate oxide covered by second polysilicon gate, 114: third polysilicon gate, 113: third thin gate oxide covered by third polysilicon gate, 116: fourth polysilicon gate, 115: fourth thin gate oxide covered by fourth polysilicon gate, 118: fifth polysilicon gate, 117: a fifth thin gate oxide covered by a fifth polysilicon gate, 120: sixth polysilicon gate, 119: a sixth thin gate oxide layer covered by a sixth polysilicon gate;
201: first metal 1, 202: second metal 1, 203: third metal 1, 204: fourth metal 1, 205: fifth metal 1, 206: sixth metal 1, 207: a seventh metal 1;
301: first electrode, 302: a second electrode.
Detailed Description
The invention is explained in more detail below with reference to the drawing and example 1:
example 1
The embodiment provides an ESD protection device combined with a gate isolation technology, which can be used as a transient voltage suppression or ESD protection device. On the basis of the strong ESD robustness advantage of the SCR structure and the technology that the GGNMOS structure is used for reducing trigger voltage and the like, the isolation gate structure is introduced, on the premise that the area of a device is not changed, the conduction path of current inside the device is greatly prolonged, the holding voltage is improved, the voltage hysteresis amplitude is reduced, the latch-up effect of the device in the ESD protection or anti-surge process is avoided, and the ESD protection or anti-surge efficiency is improved.
The three-dimensional structure of the ESD protection device with the gate isolation technology is schematically shown in fig. 1, and mainly includes a P substrate 101, an N well 102, a P well 103, a first N + implantation region 104, a second N + implantation region 106, a third N + implantation region 107, a first P + implantation region 105, a second P + implantation region 108, a first polysilicon gate 110 and a first thin gate oxide layer 109 covered by the first polysilicon gate 110, a second polysilicon gate 112 and a second thin gate oxide layer 111 covered by the second polysilicon gate 112, a third polysilicon gate 114 and a third thin gate oxide layer 113 covered by the third polysilicon gate 114, a fourth polysilicon gate 116 and a fourth thin gate oxide layer 115 covered by the fourth polysilicon gate 116, a fifth polysilicon gate 118 and a fifth thin gate oxide layer 117 covered by the fifth polysilicon gate 118, a sixth polysilicon gate 120 and a sixth thin gate oxide layer 119 and a metal wire covered by the sixth polysilicon gate 120;
preparing an N well 102 and a P well 103 on a P substrate 101, wherein the left edge of the P substrate 101 is connected with the left edge of the N well 102, the right side of the N well 102 is connected with the left side of the P well 103, and the right edge of the P well 103 is connected with the right edge of the P substrate 101;
an isolation gate structure is arranged in the surface region of the P-well 103, and the isolation gate structure is composed of a first polysilicon gate 110, a first thin gate oxide layer 109 covered by the first polysilicon gate 110, a second polysilicon gate 112, a second thin gate oxide layer 111 covered by the second polysilicon gate 112, a third polysilicon gate 114, a third thin gate oxide layer 113 covered by the third polysilicon gate 114, a fourth polysilicon gate 116, a fourth thin gate oxide layer 115 covered by the fourth polysilicon gate 116, a fifth polysilicon gate 118, a fifth thin gate oxide layer 117 and a sixth polysilicon gate 120 covered by the fifth polysilicon gate 118, and a sixth thin gate oxide layer 119 covered by the sixth polysilicon gate 120, wherein the first polysilicon gate 110, the first thin gate oxide layer 109 and the second polysilicon gate 112 covered by the first polysilicon gate 110, and the second thin gate oxide layer 111 covered by the fifth polysilicon gate 112, and the second thin gate oxide layer 111 covered by the sixth polysilicon gate 120 are aligned in the width direction of the device, and have a safety gap in the width direction of the device, and the third polysilicon gate 114 and the third thin gate oxide layer 113 are respectively aligned with the width direction of the P-well 103, and the P-well 103, The lower edges of the first polysilicon gate 110, the first thin gate oxide layer 109 and the second polysilicon gate 112 covered by the first polysilicon gate and the second thin gate oxide layer 111 covered by the second polysilicon gate are all provided with a safety distance, the fourth polysilicon gate 116, the fourth thin gate oxide layer 115 covered by the fourth polysilicon gate 116, the fifth polysilicon gate 118 and the fifth thin gate oxide layer 117 covered by the fifth polysilicon gate 118 are aligned along the width direction of the device, and the safety distance is arranged along the width direction of the device, and the fourth polysilicon gate 116, the fourth thin gate oxide layer 115 covered by the fourth polysilicon gate 116, the fifth polysilicon gate 118 covered by the fourth polysilicon gate 118, the fifth thin gate oxide layer 117 covered by the fifth polysilicon gate 114, the third thin gate oxide layer 113 covered by the third polysilicon gate 114 and the third thin gate oxide layer 113 covered by the fourth polysilicon gate 116 keep the safety distance in the length direction; a safety distance is kept between the sixth polysilicon gate 120 and the sixth thin gate oxide layer 119 covered by the sixth polysilicon gate, the fourth polysilicon gate 116 and the fourth thin gate oxide layer 115 and the fifth polysilicon gate 118 covered by the fourth polysilicon gate, and the fifth thin gate oxide layer 117 covered by the fifth polysilicon gate 118 in the length direction;
a first N + injection region 104 and a first P + injection region 105 are sequentially arranged on the surface region of the N well 102, the first N + injection region 104 keeps a certain safety distance from the edge of the well region, the first P + injection region 105 keeps a certain safety distance from the first N + injection region 104, a second N + injection region 106 (a region marked by a dotted line in fig. 1) is arranged on the surface region where the N well 102 is connected with the P well 103, and a distance is arranged between the left side of the second N + injection region 106 and the first P + injection region 105;
the right side of the second N + implantation region 106 is connected to the sixth polysilicon gate 120 and the left side of the sixth thin gate oxide 119 covered by the sixth polysilicon gate, and the first polysilicon gate 110 and the first thin gate oxide 109 and the second polysilicon gate 112 covered by the first polysilicon gate and the second thin gate oxide 111 and the third polysilicon gate 114 and the third thin gate oxide 113 and the fourth polysilicon gate 116 covered by the first polysilicon gate and the fourth thin gate oxide 115 and the fifth polysilicon gate 118 covered by the second polysilicon gate and the fifth thin gate oxide 117 covered by the fifth polysilicon gate 118 are all located in the second N + implantation region 106, where: along the length direction of the device, a distance is arranged between the first polysilicon gate 110 and the first thin gate oxide layer 109 and the third polysilicon gate 114 covered by the first polysilicon gate and the third thin gate oxide layer 113 covered by the third polysilicon gate, a distance is arranged between the third polysilicon gate 114 and the third thin gate oxide layer 113 and the fifth polysilicon gate 118 covered by the third polysilicon gate and the fifth thin gate oxide layer 117 covered by the fifth polysilicon gate, and a distance is arranged between the fifth polysilicon gate 118 and the fifth thin gate oxide layer 117 covered by the fifth polysilicon gate and the sixth polysilicon gate 120 and the sixth thin gate oxide layer 119 covered by the sixth polysilicon gate;
a third N + injection region 107 and a second P + injection region 108 are further sequentially arranged on the sixth polysilicon gate 120 in the surface region of the P well 103 and on the right side of a sixth thin gate oxide layer 119 covered by the sixth polysilicon gate 120, the sixth polysilicon gate 120 and the right side of the sixth thin gate oxide layer 119 covered by the sixth polysilicon gate are connected with the left side of the third N + injection region 107, a gap is arranged between the second P + injection region 108 and the third N + injection region 107, and a certain safety distance is kept between the second P + injection region 108 and the edge of the P well 103;
a metal connection line of the ESD protection device according to the present embodiment and combining with the gate isolation technology is shown in fig. 2, where the metal connection line is used to connect an injection region with an anode and a cathode, a first N + injection region 104 is connected to a first metal 1201, a first P + injection region 105 is connected to a second metal 1202, a sixth polysilicon gate 120 is connected to a fourth metal 1204, a third N + injection region 107 is connected to a fifth metal 1205, and a second P + injection region 108 is connected to a sixth metal 1206;
the first metal 1201 and the second metal 1202 are connected with a third metal 1203, and a first electrode 301 is led out of the third metal 1203 and is used as a metal anode of the device;
the fourth metal 1204, the fifth metal 1205, and the sixth metal 1206 are connected to the seventh metal 1207, and the second electrode 302 is led out from the seventh metal 1207 to serve as a metal cathode of the device.
In this embodiment, a layout of the ESD protection device and an internal current path thereof are marked as shown in fig. 3, where a first polysilicon gate 110, a first thin gate oxide layer 109 covered by the first polysilicon gate, a second polysilicon gate 112, a second thin gate oxide layer 111 covered by the second polysilicon gate 112, a third polysilicon gate 114, a third thin gate oxide layer 113 covered by the third polysilicon gate 114, a fourth polysilicon gate 116, a fourth thin gate oxide layer 115 covered by the fourth polysilicon gate 116, a fifth polysilicon gate 118, and a fifth thin gate oxide layer 117 covered by the fifth polysilicon gate 118 are established in a surface region of the second N + implantation region 106 located in the P well 103, and an internal current conduction path of the device under the action of ESD stress is changed through a gate isolation technique, so that a curved current channel is formed inside the device, and the curved current channel is shown by a dotted line in fig. 3, so that a current conduction path of a parasitic SCR structure inside the device can be greatly extended without increasing the area of the device, the sustain voltage is increased. Furthermore, the ESD robustness of the device can be changed by controlling the distance D1 between the first polysilicon gate 110 and the first and second polysilicon gates 109 and 112 covered by the first polysilicon gate and the second thin gate oxide 111 covered by the second polysilicon gate along the width direction of the device, when the distance D1 is increased appropriately, the device turn-on is reduced, the robustness is increased, when the distance D2 between the fourth polysilicon gate 116 and the fourth and fifth polysilicon gates 115 and 118 covered by the fourth and fifth polysilicon gates 118 and the fifth thin gate oxide 117 covered by the fifth polysilicon gate along the width direction of the device is controlled to change the turn-on speed and the trigger characteristic, and when the distance D2 is increased appropriately, the area of the GGNMOS assisted trigger is increased, and the turn-on speed of the device can be increased. In addition, the GGNMOS structure formed by the trench-type second N + implantation region 106, the sixth polysilicon gate 120, and the sixth thin gate oxide 119 and the third N + implantation region 107 covered by the trench-type second N + implantation region can adjust the trigger voltage and ESD robustness of the device, and realize the function of controllable voltage hysteresis amplitude.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A method for improving ESD protection performance of a circuit system is characterized in that a gate isolation technology is utilized, a constructed protection device comprises an SCR, a GGNMOS, an isolation gate structure and a metal wire, and the protection device comprises: the transistor comprises a P substrate (101), an N trap (102), a P trap (103), a first N + injection region (104), a second N + injection region (106), a third N + injection region (107), a first P + injection region (105), a second P + injection region (108), a first polysilicon gate (110) and a first thin gate oxide layer (109) covered by the first polysilicon gate, a second polysilicon gate (112) and a second thin gate oxide layer (111) covered by the second polysilicon gate, a third polysilicon gate (114) and a third thin gate oxide layer (113) covered by the third polysilicon gate, a fourth polysilicon gate (116) and a fourth thin gate oxide layer (115) covered by the fourth polysilicon gate (118), a fifth thin gate oxide layer (117) covered by the fifth polysilicon gate (118), a sixth polysilicon gate (120) and a sixth thin gate oxide layer (119) covered by the sixth polysilicon gate (120);
preparing an N well (102) and a P well (103) on a P substrate (101), wherein the left edge of the P substrate (101) is connected with the left edge of the N well (102), the right side of the N well (102) is connected with the left side of the P well (103), and the right edge of the P well (103) is connected with the right edge of the P substrate (101);
an isolation gate structure is arranged in the surface area of the P trap (103), the isolation gate structure is composed of a first polysilicon gate (110), a first thin gate oxide layer (109) covered by the first polysilicon gate, a second polysilicon gate (112), a second thin gate oxide layer (111) covered by the second polysilicon gate, a third polysilicon gate (114), a third thin gate oxide layer (113) covered by the third polysilicon gate, a fourth polysilicon gate (116), a fourth thin gate oxide layer (115) covered by the fourth polysilicon gate, a fifth polysilicon gate (118), a fifth thin gate oxide layer (117) covered by the fifth polysilicon gate and a sixth polysilicon gate (120) covered by the sixth polysilicon gate, and a sixth thin gate oxide layer (119) covered by the sixth polysilicon gate, wherein the first polysilicon gate (110) and the first thin gate oxide layer (109) covered by the fifth polysilicon gate (118) are aligned with the second polysilicon gate (112) and the second thin gate oxide layer (111) covered by the sixth polysilicon gate oxide layer along the width direction of the device, and a safety interval is arranged in the width direction of the device, a third polysilicon gate (114) and a third thin gate oxide layer (113) covered by the third polysilicon gate have safe intervals with the upper edge and the lower edge of the P well (103), respectively, a fourth polysilicon gate (116) and a fourth thin gate oxide layer (115) covered by the fourth polysilicon gate are aligned with a fifth polysilicon gate (118) and a fifth thin gate oxide layer (117) covered by the fifth polysilicon gate along the width direction of the device, and the safe intervals are arranged in the width direction of the device;
a first N + injection region (104) and a first P + injection region (105) are sequentially arranged on the surface region of the N well (102), a certain safety distance is kept between the first N + injection region (104) and the left side edge of the N well (102), a certain safety distance is kept between the first P + injection region (105) and the first N + injection region (104), a second N + injection region (106) is arranged on the surface region where the N well (102) is connected with the P well (103), and a safety distance is arranged between the left side of the second N + injection region (106) and the first P + injection region (105);
the right side of the second N + implantation region (106) is connected to the sixth polysilicon gate (120) and the left side of the sixth thin gate oxide layer (119) covered by the sixth polysilicon gate, the first polysilicon gate (110) and the first thin gate oxide layer (109) and the second polysilicon gate (112) covered by the first polysilicon gate and the second thin gate oxide layer (111) covered by the second polysilicon gate, the third polysilicon gate (114) and the third thin gate oxide layer (113) covered by the third polysilicon gate, the fourth polysilicon gate (116) and the fourth thin gate oxide layer (115) and the fifth polysilicon gate (118) covered by the fourth polysilicon gate and the fifth thin gate oxide layer (117) covered by the fifth polysilicon gate are all located in the second N + implantation region (106), wherein: along the length direction of the device, a safety distance is arranged between a first polysilicon gate (110) and a first thin gate oxide layer (109) and a third polysilicon gate (114) covered by the first polysilicon gate and a third thin gate oxide layer (113) covered by the third polysilicon gate, a safety distance is arranged between the third polysilicon gate (114) and a third thin gate oxide layer (113) and a fifth polysilicon gate (118) covered by the third polysilicon gate and a fifth thin gate oxide layer (117) covered by the fifth polysilicon gate, and a safety distance is arranged between the fifth polysilicon gate (118) and a fifth thin gate oxide layer (117) covered by the fifth polysilicon gate and a sixth polysilicon gate (120) covered by the sixth thin gate oxide layer (119);
a third N + injection region (107) and a second P + injection region (108) are sequentially arranged on the sixth polysilicon gate (120) in the surface region of the P well (103) and on the right side of a sixth thin gate oxide layer (119) covered by the sixth polysilicon gate, the right side of the sixth polysilicon gate (120) and the sixth thin gate oxide layer (119) covered by the sixth polysilicon gate are connected with the left side of the third N + injection region (107), a safety interval is arranged between the second P + injection region (108) and the third N + injection region (107), and a certain safety interval is kept between the second P + injection region (108) and the edge of the P well (103);
the metal wire is connected with the high-doped injection region, and part of metal is used as an anode and a cathode of the device, wherein: the first N + injection region (104) is connected with the first metal 1(201), the first P + injection region (105) is connected with the second metal 1(202), the sixth polysilicon gate (120) is connected with the fourth metal 1(204), the third N + injection region (107) is connected with the fifth metal 1(205), and the second P + injection region (108) is connected with the sixth metal 1 (206);
the first metal 1(201) and the second metal 1(202) are connected with the third metal 1(203), and a first electrode (301) is led out from the third metal 1(203) and is used as a metal anode of the device;
the fourth metal 1(204), the fifth metal 1(205) and the sixth metal 1(206) are connected with the seventh metal 1(207), and a second electrode (302) is led out from the seventh metal 1(207) and is used as a metal cathode of the device.
2. The method of claim 1, wherein the ESD protection performance of the circuit system is improved by: by utilizing an isolation gate technology, through a first polysilicon gate (110), a first thin gate oxide layer (109) covered by the first polysilicon gate, a second polysilicon gate (112), a second thin gate oxide layer (111) covered by the second polysilicon gate, a third polysilicon gate (114), a third thin gate oxide layer (113) covered by the third polysilicon gate, a fourth polysilicon gate (116), a fourth thin gate oxide layer (115) covered by the fourth polysilicon gate, a fifth polysilicon gate (118) covered by the fifth polysilicon gate and a fifth thin gate oxide layer (117) covered by the fifth polysilicon gate, the trend of current in the device is controlled, the current path is prolonged, and the ESD or electrical over-stress protection performance of the device is improved on the premise of not increasing the area of the device; the current conducting capability of the device and the robustness of ESD protection and electrical overstress protection are adjusted by controlling the distance between the first polysilicon gate (110) and the first thin gate oxide layer (109) covered by the first polysilicon gate, the second polysilicon gate (112) and the second thin gate oxide layer (111) covered by the second polysilicon gate, and the distance between the fourth polysilicon gate (116) and the fourth thin gate oxide layer (115) and the fifth polysilicon gate (118) covered by the fourth polysilicon gate and the fifth thin gate oxide layer (117) covered by the fifth polysilicon gate in the width direction of the device.
3. The method of claim 1, wherein the ESD protection performance of the circuit system is improved by: along the device width direction: adjusting the distance between the first polysilicon gate (110) and the first thin gate oxide layer (109) covered by the first polysilicon gate and the second polysilicon gate (112) and the second thin gate oxide layer (111) covered by the second polysilicon gate for changing the ESD robustness of the device; and adjusting the distance between the fourth polysilicon gate (116) and the fourth thin gate oxide layer (115) covered by the fourth polysilicon gate and the fifth polysilicon gate (118) and the fifth thin gate oxide layer (117) covered by the fifth polysilicon gate for changing the opening speed and the triggering characteristics of the device.
4. The method of claim 1, wherein the ESD protection performance of the circuit system is improved by: the GGNMOS structure formed by the groove type second N + injection region (106), the sixth polysilicon gate (120), the sixth thin gate oxide layer (119) covered by the groove type second N + injection region and the third N + injection region (107) can adjust the trigger voltage and the ESD robustness of the device, and the function of controllable voltage hysteresis amplitude is realized.
5. The device for ESD protection of a circuit system, which is constructed by the method of any one of claims 1 to 4, comprises an SCR, a GGNMOS, an isolation gate structure and metal wires, and is characterized in that the device for the application example mainly comprises a P substrate (101), an N well (102), a P well (103), a first N + injection region (104), a second N + injection region (106), a third N + injection region (107), a first P + injection region (105), a second P + injection region (108), a first polysilicon gate (110) and a first thin gate oxide layer (109) covered by the first polysilicon gate (110), a second polysilicon gate (112) and a second thin gate oxide layer (111) covered by the second polysilicon gate (112), a third polysilicon gate (114) and a third thin gate oxide layer (113) covered by the third polysilicon gate (116), a fourth polysilicon gate (116) and a fourth thin gate oxide layer (115) covered by the fourth polysilicon gate (118), a fifth thin gate oxide layer (117) covered by the fifth polysilicon gate (118), A sixth polysilicon gate (120) and a sixth thin gate oxide layer (119) covering the sixth polysilicon gate;
preparing an N well (102) and a P well (103) on a P substrate (101), wherein the left edge of the P substrate (101) is connected with the left edge of the N well (102), the right side of the N well (102) is connected with the left side of the P well (103), and the right edge of the P well (103) is connected with the right edge of the P substrate (101);
an isolation gate structure is arranged in the surface area of the P trap (103), the isolation gate structure is composed of a first polysilicon gate (110), a first thin gate oxide layer (109) covered by the first polysilicon gate, a second polysilicon gate (112), a second thin gate oxide layer (111) covered by the second polysilicon gate, a third polysilicon gate (114), a third thin gate oxide layer (113) covered by the third polysilicon gate, a fourth polysilicon gate (116), a fourth thin gate oxide layer (115) covered by the fourth polysilicon gate, a fifth polysilicon gate (118), a fifth thin gate oxide layer (117) covered by the fifth polysilicon gate and a sixth polysilicon gate (120) covered by the sixth polysilicon gate, and a sixth thin gate oxide layer (119) covered by the sixth polysilicon gate, wherein the first polysilicon gate (110) and the first thin gate oxide layer (109) covered by the fifth polysilicon gate (118) are aligned with the second polysilicon gate (112) and the second thin gate oxide layer (111) covered by the sixth polysilicon gate oxide layer along the width direction of the device, and a safety interval is arranged in the width direction of the device, a third polysilicon gate (114) and a third thin gate oxide layer (113) covered by the third polysilicon gate have safe intervals with the upper edge and the lower edge of the P well (103), respectively, a fourth polysilicon gate (116) and a fourth thin gate oxide layer (115) covered by the fourth polysilicon gate are aligned with a fifth polysilicon gate (118) and a fifth thin gate oxide layer (117) covered by the fifth polysilicon gate along the width direction of the device, and the safe intervals are arranged in the width direction of the device;
a first N + injection region (104) and a first P + injection region (105) are sequentially arranged on the surface region of the N well (102), a certain safety distance is kept between the first N + injection region (104) and the left side edge of the N well (102), a certain safety distance is kept between the first P + injection region (105) and the first N + injection region (104), a second N + injection region (106) is arranged on the surface region where the N well (102) is connected with the P well (103), and a safety distance is arranged between the left side of the second N + injection region (106) and the first P + injection region (105);
the right side of the second N + implantation region (106) is connected to the sixth polysilicon gate (120) and the left side of the sixth thin gate oxide layer (119) covered by the sixth polysilicon gate, the first polysilicon gate (110) and the first thin gate oxide layer (109) and the second polysilicon gate (112) covered by the first polysilicon gate and the second thin gate oxide layer (111) covered by the second polysilicon gate, the third polysilicon gate (114) and the third thin gate oxide layer (113) covered by the third polysilicon gate, the fourth polysilicon gate (116) and the fourth thin gate oxide layer (115) and the fifth polysilicon gate (118) covered by the fourth polysilicon gate and the fifth thin gate oxide layer (117) covered by the fifth polysilicon gate are all located in the second N + implantation region (106), wherein: along the length direction of the device, a safety distance is arranged between a first polysilicon gate (110) and a first thin gate oxide layer (109) and a third polysilicon gate (114) covered by the first polysilicon gate and a third thin gate oxide layer (113) covered by the third polysilicon gate, a safety distance is arranged between the third polysilicon gate (114) and a third thin gate oxide layer (113) and a fifth polysilicon gate (118) covered by the third polysilicon gate and a fifth thin gate oxide layer (117) covered by the fifth polysilicon gate, and a safety distance is arranged between the fifth polysilicon gate (118) and a fifth thin gate oxide layer (117) covered by the fifth polysilicon gate and a sixth polysilicon gate (120) covered by the sixth thin gate oxide layer (119);
a third N + injection region (107) and a second P + injection region (108) are sequentially arranged on the sixth polysilicon gate (120) in the surface region of the P well (103) and on the right side of a sixth thin gate oxide layer (119) covered by the sixth polysilicon gate, the right side of the sixth polysilicon gate (120) and the sixth thin gate oxide layer (119) covered by the sixth polysilicon gate are connected with the left side of the third N + injection region (107), a safety interval is arranged between the second P + injection region (108) and the third N + injection region (107), and a certain safety interval is kept between the second P + injection region (108) and the edge of the P well (103);
the metal wire is connected with the high-doped injection region, and part of metal is used as an anode and a cathode of the device, wherein: the first N + injection region (104) is connected with the first metal 1(201), the first P + injection region (105) is connected with the second metal 1(202), the sixth polysilicon gate (120) is connected with the fourth metal 1(204), the third N + injection region (107) is connected with the fifth metal 1(205), and the second P + injection region (108) is connected with the sixth metal 1 (206);
the first metal 1(201) and the second metal 1(202) are connected with the third metal 1(203), and a first electrode (301) is led out from the third metal 1(203) and is used as a metal anode of the device;
the fourth metal 1(204), the fifth metal 1(205) and the sixth metal 1(206) are connected with the seventh metal 1(207), and a second electrode (302) is led out from the seventh metal 1(207) and is used as a metal cathode of the device.
6. Use of a device for ESD protection of electronic circuits according to claim 5 for electrostatic discharge and electrostatic overstress protection.
7. An integrated circuit comprising the device for ESD protection of a circuit system of claim 5.
8. An integrated circuit obtained by the method of any one of claims 1 to 4.
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