CN106252400B - A kind of improvement method of thick film SOI-LIGBT device and its latch-up immunity - Google Patents
A kind of improvement method of thick film SOI-LIGBT device and its latch-up immunity Download PDFInfo
- Publication number
- CN106252400B CN106252400B CN201610835934.6A CN201610835934A CN106252400B CN 106252400 B CN106252400 B CN 106252400B CN 201610835934 A CN201610835934 A CN 201610835934A CN 106252400 B CN106252400 B CN 106252400B
- Authority
- CN
- China
- Prior art keywords
- contact zone
- type
- negative contact
- layer
- isolation channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000036039 immunity Effects 0.000 title claims abstract description 11
- 230000006872 improvement Effects 0.000 title claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 55
- 238000002955 isolation Methods 0.000 claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002161 passivation Methods 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of improvement method of thick film SOI-LIGBT device and its latch-up immunity, including P type substrate, one layer of buries oxide layer is equipped in P type substrate, there is N-type drift region above buries oxide layer, the inside of N-type drift region is equipped with the area PXing Ti and N-type buffer area, p-type negative contact zone and N-shaped negative contact zone are equipped in p-type body surface, contact zone is connected with cathode contacts metal layer, p type anode contact zone is equipped on the surface of N-type buffer area, contact zone is connected with positive contact metal layer, there are field oxide and conductive polysilicon gate in the surface of N-type drift region, in negative contact zone, positive contact area, the surface of field oxide and conductive polysilicon gate is equipped with passivation layer, it is characterized in that, isolation channel is equipped on the outside of device cathodes, conductive polycrystalline silicon and negative contact zone and cathode metal layer are shorted in isolation channel, Potential difference between conductive polycrystalline silicon and N-type drift region, reduces the hole current for flowing through lateral channel in the area PXing Ti, realizes the raising of latch-up immunity in the method increase isolation channel.
Description
Technical field
It is about a kind of thick film SOI-LIGBT device and its anti-latch the present invention relates to the reliability field of integrated circuit
The method that ability improves.
Background technique
High power semiconductor device and integrated circuit have occupied 75% or so of international power semiconductor industry total value.I
State's independent research high-power component technology also gradually internationalizes, while the overheat of device, over-voltage, electrostatic protection (Electronic
Static Discharge protection, ESD), the integrity problems such as anti-latch it is also especially prominent.Wherein since latch is imitated
Cross caused by answering flow problem make insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT),
Silicon-on-insulator lateral insulated gate bipolar transistor (Silicon-On-Insulated-Lateral Insulated Gate
Bipolar Transistor, SOI-LIGBT), silicon controlled rectifier (SCR) (Semiconductor Control Rectifier,
) etc. SCR devices reliability when circuit works is greatly reduced.For SOI-LIGBT device in actual push-pull circuit, power
Device once enters latch mode, will directly form low impedance path between the power supply and ground of push-pull circuit, will between power supply and ground
It flows through high current and makes power device or even entire circuit burnout.Therefore the latch that SOI-LIGBT device must be studied in detail is special
Property is to improve the reliability of device and its circuit.
At present for SOI-LIGBT device, latch-up is mainly derived from NPN crystal parasitic in device architecture
Pipe.According to the working mechanism of SOI-LIGBT, exist in device architecture by cathode N-type contact zone, the area PXing Ti and N-type drift region group
At parasitic NPN transistor.When device work, there are two strands of electric currents in structure, one flows to the electricity of anode from cathode
Electron current, another stock derive from the hole current emitted by anode.Wherein hole current flows through N-type buffer area, N by anode sending
Type drift region and the area PXing Ti are finally collected by cathode p-type contact zone；It can be flowed through when hole current is excessive horizontal in the area PXing Ti
Pressure drop to channel region reaches 0.7V, and at this moment parasitic NPN transistor is opened, at this time parasitic NPN transistor meeting and collector
The PNP transistor at place mutually provides base current, to make device that can not turn off, ultimately forms latch phenomenon.The present invention is directed to
Such case proposes a kind of device latch-up immunity promotion new method.
Summary of the invention
The present invention is to provide a kind of thick film SOI-LIGBT device and its anti-door bolt on the basis of original device architecture
The improvement method of lock ability, and latch-up immunity have significantly improve.
The present invention adopts the following technical scheme that
A kind of thick film SOI-LIGBT device, including P type substrate are equipped with one layer of buries oxide layer in P type substrate, are burying oxygen
Changing has N-type drift region above layer, the inside of N-type drift region is equipped with the area PXing Ti and N-type buffer area, is equipped with P in p-type body surface
Type negative contact zone and N-shaped negative contact zone, p-type negative contact zone and N-shaped negative contact zone are connected with cathode contacts metal layer,
It is equipped with p type anode contact zone on the surface of N-type buffer area, p type anode contact zone is connected with positive contact metal layer, N-type drift
There are field oxide and conductive polysilicon gate in the surface in area, field oxide between N-shaped negative contact zone and p-type contact zone,
Conductive polysilicon gate extends to field oxide upper surface by the boundary of N-shaped negative contact zone, in p-type negative contact zone, N-shaped
Negative contact zone, p type anode contact zone, field oxide and conductive polysilicon gate surface be equipped with passivation layer, outside device cathodes
Side is equipped with isolation channel, and the isolation channel is formed by isolating oxide layer and by the conductive polycrystalline silicon that the isolating oxide layer wraps up,
It is characterized in that, the conductive polycrystalline silicon wrapped up by the isolating oxide layer and p-type negative contact zone, N-shaped negative contact zone and yin
Pole metal layer is shorted.
A kind of improvement method of the latch-up immunity of the thick film SOI-LIGBT device, the SOI-LIGBT device include
P type substrate is equipped with one layer of buries oxide layer in P type substrate, there is N-type drift region, the inside of N-type drift region above buries oxide layer
Equipped with the area PXing Ti and N-type buffer area, p-type negative contact zone and N-shaped negative contact zone, p-type cathode are equipped in p-type body surface
Contact zone and N-shaped negative contact zone are connected with cathode contacts metal layer, are equipped with p type anode contact zone on the surface of N-type buffer area,
P type anode contact zone is connected with positive contact metal layer, and there are field oxide and conductive polysilicon gate in the surface of N-type drift region,
Field oxide between N-shaped negative contact zone and p-type contact zone, opened by N-shaped negative contact zone boundary by conductive polysilicon gate
Beginning extend to field oxide upper surface, p-type negative contact zone, N-shaped negative contact zone, p type anode contact zone, field oxide and
The surface of conductive polysilicon gate is equipped with passivation layer, is equipped with isolation channel on the outside of device cathodes, the isolation channel is by isolating oxide layer
With the conductive polycrystalline silicon composition wrapped up by the isolating oxide layer, which is characterized in that led what is wrapped up by the isolating oxide layer
Electric polysilicon and p-type negative contact zone, N-shaped negative contact zone and cathode metal layer are shorted so that entire isolation channel have with
The identical current potential of cathode reduces the current potential inside isolation channel, increases potential between conductive polycrystalline silicon and N-type drift region in isolation channel
Difference, and potential difference is utilized, reduce the hole current for flowing through lateral channel in the area PXing Ti.
Compared with prior art, this when invention has the following advantages that
(1) structure in the method for the present invention can effectively improve device latch-up immunity.Isolation channel is used in the present invention
In the form that is grounded of conductive polycrystalline silicon 15, can be dry by the external world to avoid the current potential of the conductive polycrystalline silicon 15 in device isolation slot
It disturbs, keeps a constant low potential, to effectively increase conductive polysilicon electrode 15 and N-type drift region 3 in device
Voltage difference, as shown in fig. 6, Fig. 6 comparison diagram 5, conductive polysilicon electrode 15 and 3 potential difference of N-type drift region are increased close to twice,
- 44V is increased to by -24.2V, due to the effect of this larger potential difference in new construction, so that there must be more skies in device
Cave electric current is flowed along ditch non-intercommunicating cells lateral wall.The highlight regions as shown in 16 in Fig. 6 subtract under the premise of hole current total amount is constant
It is small that the hole current of position 17 in the area PXing Ti 4 is flowed through by N-type drift region 3, to reduce the dead resistance at position 17
On pressure drop, reduce device generate latch a possibility that, so that the latch voltage of device has been increased to 263V from 210V.
(2) conductive polysilicon electrode 15 and cathode are shorted the breakdown voltage that method does not change device in isolation channel in the present invention
With current capacity.Since the breakdown point of device architecture is located at 6 lower section of p-type contact zone, however isolation channel will not change p-type contact zone
The field distribution of 6 lower sections, so the ground connection of conductive polysilicon electrode 15 can't generate shadow to the breakdown voltage of device in isolation channel
It rings.In addition, the presence of the isolation moat structure in the method for the present invention passes through the partial holes electric current of position 17 in the area PXing Ti 4
It changes and flows into cathode along ditch non-intercommunicating cells lateral wall behind original path, increase the hole current for flowing through ditch non-intercommunicating cells lateral wall, reduce
Flow through the hole current of position 17 in the area PXing Ti 4, the highlight regions as shown in 16 in Fig. 6, but size of current total in device
There is no changes.
(3) in the isolation channel in the present invention conductive polysilicon electrode 15 and 9 short circuit method of cathode due to not needing new light
It cuts blocks for printing, is not also related to new domain technique, so not will increase the process costs of manufacture in the manufacture of device.
(4) its latch-up immunity when realizing in parallel of the structure in the method for the present invention is unaffected, increases parallel-connection structure
The stability of middle device.Parallel-connection structure is commonly used in high power device application and forms the more finger device parts of racetrack, is passed described in Fig. 2 as system device
The racetrack that part structure composes in parallel refers to element layout more, is that the racetrack that novel device architecture composes in parallel is more described in Fig. 4
Refer to element layout.The parallel-connection structure of conventional device structure composition will receive the dry of other external devices and ambient enviroment in the application
It disturbs, on the one hand will cause the potential fluctuation problem that the China and foreign countries Fig. 2 enclose the conductive polycrystalline silicon 15 in isolation channel 19；On the other hand it will affect
Enclose the current potential of conductive polycrystalline silicon 15 in isolation channel 19 and the conductive polycrystalline silicon 15 in the isolation channel 18 of inside configuration in the China and foreign countries Fig. 2
Current potential is uniformly distributed.However, parallel-connection structure in Fig. 4 due in isolation channel conductive polycrystalline silicon 15 and cathode be shorted, can be with
Make the potential difference of conductive polycrystalline silicon 15 and device inside N-type drift region 3 in all devices in parallel keep stablizing, finally avoid by
The problem of device property floats in the parallel-connection structure caused by external interference, enhances the stability of device in parallel-connection structure.
Detailed description of the invention
Fig. 1 is the two dimensional cross-section structure of traditional thick film SOI-LIGBT device.
Fig. 2 is the domain for the more finger device parts of racetrack that traditional thick film SOI-LIGBT device architecture composes in parallel, in domain
Conductive polycrystalline silicon is not shorted with cathode in isolation channel near cathode.
Fig. 3 is the two dimensional cross-section knot for the novel thick film SOI-LIGBT device that conductive polycrystalline silicon and cathode are shorted in isolation channel
Structure.
Fig. 4 is the domain for the more finger device parts of racetrack that novel thick film SOI-LIGBT device architecture composes in parallel, in domain
The conductive polycrystalline silicon and cathode short circuit in isolation channel near interior device cathodes.
It is 10V in grid voltage, anode voltage is 200V situation when Fig. 5 is that conductive polycrystalline silicon is not shorted with cathode in isolation channel
Under thick film SOI-LIGBT device hole current distributed simulation figure.
Fig. 6 be in isolation channel conductive polycrystalline silicon be connected with cathode ground connection when, grid voltage be 10V, anode voltage be 200V feelings
The hole current distributed simulation figure of thick film SOI-LIGBT device under condition.
Fig. 7 is traditional thick film SOI-LIGBT device and novel thick film SOI-LIGBT device latch voltage tester result pair
Than.
Specific embodiment
Embodiment 1
A kind of thick film SOI-LIGBT device, including P type substrate 1 are equipped with one layer of buries oxide layer 2 in P type substrate 1, are burying
There is N-type drift region 3 above oxide layer 2, the inside of N-type drift region 3 is equipped with the area PXing Ti 4 and N-type buffer area 14, in the area PXing Ti 4
Surface is equipped with p-type negative contact zone 6 and N-shaped negative contact zone 7, and p-type negative contact zone 6 and N-shaped negative contact zone 7 connect with cathode
It touches metal layer 9 to be connected, is equipped with p type anode contact zone 13 on the surface of N-type buffer area 14, p type anode contact zone 13 connects with anode
It touches metal layer 12 to be connected, there are field oxide 11 and conductive polysilicon gate 10 in the surface of N-type drift region 3, and field oxide 11 is between n
Between type negative contact zone 7 and p-type contact zone 13, conductive polysilicon gate 10 is extended to by 7 boundary of N-shaped negative contact zone
11 upper surface of field oxide, in p-type negative contact zone 6, N-shaped negative contact zone 7, p type anode contact zone 13,11 and of field oxide
The surface of conductive polysilicon gate 10 is equipped with passivation layer 8, is equipped with isolation channel on the outside of device cathodes, the isolation channel is by isolation oxidation
Layer 5 and is formed by the conductive polycrystalline silicon 15 that the isolating oxide layer 5 wraps up, which is characterized in that is wrapped up by the isolating oxide layer 5
Conductive polycrystalline silicon 15 and p-type negative contact zone 6, N-shaped negative contact zone 7 and cathode metal layer 9 be shorted.
Embodiment 2
A kind of improvement method of the latch-up immunity of the thick film SOI-LIGBT device, the SOI-LIGBT device include
P type substrate 1 is equipped with one layer of buries oxide layer 2 in P type substrate 1, there is N-type drift region 3, N-type drift region 3 above buries oxide layer 2
Inside be equipped with the area PXing Ti 4 and N-type buffer area 14,4 surface of the area PXing Ti be equipped with p-type negative contact zone 6 and N-shaped cathode contacts
Area 7, p-type negative contact zone 6 and N-shaped negative contact zone 7 are connected with cathode contacts metal layer 9, set on the surface of N-type buffer area 14
There is p type anode contact zone 13, p type anode contact zone 13 is connected with positive contact metal layer 12, and there is field on the surface of N-type drift region 3
Oxide layer 11 and conductive polysilicon gate 10, field oxide 11 are conductive between N-shaped negative contact zone 7 and p-type contact zone 13
Polysilicon gate 10 extends to 11 upper surface of field oxide by 7 boundary of N-shaped negative contact zone, in p-type negative contact zone 6, n
Type negative contact zone 7, p type anode contact zone 13, field oxide 11 and conductive polysilicon gate 10 surface be equipped with passivation layer 8,
Isolation channel is equipped on the outside of device cathodes, the isolation channel is more by isolating oxide layer 5 and the conduction wrapped up by the isolating oxide layer 5
Crystal silicon 15 forms, which is characterized in that by the conductive polycrystalline silicon 15 wrapped up by the isolating oxide layer 5 and p-type negative contact zone 6, n
Type negative contact zone 7 and cathode metal layer 9 are shorted, so that entire isolation channel has current potential identical with cathode, reduce isolation
Current potential inside slot increases potential difference between conductive polycrystalline silicon 15 and N-type drift region 3 in isolation channel, and utilizes potential difference, reduces
Flow through the hole current of lateral channel in the area PXing Ti 4.
For our thick film SOI technique, soi layer is with a thickness of 18 μm, in order to realize the isolation between device, the three of device
The isolation slot thickness of Mingzhi should also reach 18 μm, and the width of isolation channel should have 2 μm or so.
The present invention is prepared with the following method:
It is soi layer production first, wherein drift region 3 using injection phosphonium ion and carries out high annealing formation N-type drift region
3.For SiO2The isolation channel for the high-aspect-ratio that oxide layer 5 and conductive polycrystalline silicon 15 are formed, first progress sidewall oxidation are again with leading
Electric polysilicon filling.Next is the production of lateral isolation bipolar junction transistor, including passes through injection in N-type drift region 3
Phosphonium ion forms N-type buffer layer 14, and injection boron ion forms the area PXing Ti 4, followed by field oxide 11, and deposit later is conductive more
Crystal silicon 10, etching forms grid, then makes p type anode contact zone 13, N-shaped negative contact zone 7, p-type negative contact zone 6.And then
Silicon dioxide passivation layer 8 is deposited in overall structure upper surface, deposits metal after etching electrode contact zone, then etch metal and draw
Electrode is finally passivated processing.
Claims (4)
1. a kind of thick film SOI-LIGBT device, including P type substrate (1) are equipped with one layer of buries oxide layer (2) on P type substrate (1),
Have N-type drift region (3) above buries oxide layer (2), the inside of N-type drift region (3) is equipped with the area PXing Ti (4) and N-type buffer area
(14), p-type negative contact zone (6) and N-shaped negative contact zone (7) are equipped on the area PXing Ti (4) surface, p-type negative contact zone (6)
It is connected with N-shaped negative contact zone (7) with cathode contacts metal layer (9), is connect on the surface of N-type buffer area (14) equipped with p type anode
It touches area (13), p type anode contact zone (13) are connected with positive contact metal layer (12), and there is field oxidation on the surface of N-type drift region (3)
Layer (11) and conductive polysilicon gate (10), field oxide (11) is between N-shaped negative contact zone (7) and p type anode contact zone
(13) between, conductive polysilicon gate (10) extends to table on field oxide (11) by N-shaped negative contact zone (7) boundary
Face, it is more in p-type negative contact zone (6), N-shaped negative contact zone (7), p type anode contact zone (13), field oxide (11) and conduction
The surface of polysilicon gate (10) is equipped with passivation layer (8), isolation channel is equipped on the outside of device cathodes, the isolation channel is by isolating oxide layer
(5) and by the isolating oxide layer (5) conductive polycrystalline silicon (15) wrapped up forms, which is characterized in that by the isolating oxide layer
(5) conductive polycrystalline silicon (15) and p-type negative contact zone (6), N-shaped negative contact zone (7) and cathode metal layer (9) wrapped up is short
It connects.
2. thick film SOI-LIGBT device according to claim 1, which is characterized in that the conduction in the isolation channel is more
Crystal silicon (15) and the optimum distance of p-type contact zone (6) between the two are 5 μm -10 μm.
3. thick film SOI-LIGBT device according to claim 1, which is characterized in that the conduction in the isolation channel is more
The doping concentration of crystal silicon (15) is in 1E19cm-3~1E22cm-3In range.
4. the improvement method of the latch-up immunity of thick film SOI-LIGBT device, the SOI-LIGBT described in a kind of claim 1
Device includes P type substrate (1), and one layer of buries oxide layer (2) is equipped on P type substrate (1), has N-type drift above buries oxide layer (2)
It moves area (3), the inside of N-type drift region (3) is equipped with the area PXing Ti (4) and N-type buffer area (14), is equipped with P on the area PXing Ti (4) surface
Type negative contact zone (6) and N-shaped negative contact zone (7), p-type negative contact zone (6) and N-shaped negative contact zone (7) connect with cathode
It touches metal layer (9) to be connected, is equipped with p type anode contact zone (13) on the surface of N-type buffer area (14), p type anode contact zone (13)
It is connected with positive contact metal layer (12), there are field oxide (11) and conductive polysilicon gate in the surface of N-type drift region (3)
(10), field oxide (11) is between N-shaped negative contact zone (7) and p type anode contact zone (13), conductive polysilicon gate
(10) field oxide (11) upper surface is extended to by N-shaped negative contact zone (7) boundary, in p-type negative contact zone (6), N-shaped
Negative contact zone (7), p type anode contact zone (13), field oxide (11) and conductive polysilicon gate (10) surface be equipped with it is blunt
Change layer (8), isolation channel is equipped on the outside of device cathodes, the isolation channel is by isolating oxide layer (5) and by the isolating oxide layer (5)
The conductive polycrystalline silicon (15) of package forms, which is characterized in that the conductive polycrystalline silicon (15) that will be wrapped up by the isolating oxide layer (5)
Be shorted with p-type negative contact zone (6), N-shaped negative contact zone (7) and cathode metal layer (9) so that entire isolation channel have with
The identical current potential of cathode reduces the current potential inside isolation channel, increases conductive polycrystalline silicon (15) and N-type drift region (3) in isolation channel
Between potential difference, and utilize potential difference, reduce and flow through the hole current of lateral channel in the area PXing Ti (4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610835934.6A CN106252400B (en) | 2016-09-20 | 2016-09-20 | A kind of improvement method of thick film SOI-LIGBT device and its latch-up immunity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610835934.6A CN106252400B (en) | 2016-09-20 | 2016-09-20 | A kind of improvement method of thick film SOI-LIGBT device and its latch-up immunity |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106252400A CN106252400A (en) | 2016-12-21 |
| CN106252400B true CN106252400B (en) | 2019-06-18 |
Family
ID=57599049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610835934.6A Active CN106252400B (en) | 2016-09-20 | 2016-09-20 | A kind of improvement method of thick film SOI-LIGBT device and its latch-up immunity |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106252400B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107256885B (en) * | 2017-06-30 | 2022-08-26 | 北京工业大学 | High-reliability insulated gate bipolar transistor and manufacturing method thereof |
| CN111223855B (en) * | 2019-11-19 | 2021-12-03 | 江南大学 | Method for improving ESD protection performance of circuit system by using gate isolation technology |
| CN111261722B (en) * | 2020-01-21 | 2023-03-24 | 东南大学 | Low reverse recovery charge lateral diode of integrated capacitor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103762230A (en) * | 2014-01-24 | 2014-04-30 | 东南大学 | N-channel injection efficiency reinforced insulated gate bipolar transistor |
| CN105826367A (en) * | 2016-03-18 | 2016-08-03 | 东南大学 | Large-current silicon on insulator lateral insulated gate bipolar transistor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004193486A (en) * | 2002-12-13 | 2004-07-08 | Toshiba Corp | Horizontal semiconductor device |
-
2016
- 2016-09-20 CN CN201610835934.6A patent/CN106252400B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103762230A (en) * | 2014-01-24 | 2014-04-30 | 东南大学 | N-channel injection efficiency reinforced insulated gate bipolar transistor |
| CN105826367A (en) * | 2016-03-18 | 2016-08-03 | 东南大学 | Large-current silicon on insulator lateral insulated gate bipolar transistor device |
Non-Patent Citations (1)
| Title |
|---|
| Novel lateral insulated gate bipolar transistor on SOI substrate for optimizing hot-carrier degradation;Huang Tingting etc;《Journalof Southeast University》;20140331;第30卷(第1期);第17-21页 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106252400A (en) | 2016-12-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103441148B (en) | A kind of groove grid VDMOS device of integrated schottky diode | |
| CN103383958B (en) | A kind of RC-IGBT device and making method thereof | |
| CN110190113A (en) | A kind of anode in short circuit type landscape insulation bar double-pole-type transistor for eliminating negative resistance effect | |
| CN105870179B (en) | A kind of trench gate charge storage type RC-IGBT and its manufacturing method | |
| CN109037337A (en) | A kind of power semiconductor and manufacturing method | |
| CN105679816B (en) | A kind of trench gate charge storage type IGBT and its manufacturing method | |
| CN105679819A (en) | Reverse conducting MOS gate-controlled thyristor and fabrication method thereof | |
| CN106252400B (en) | A kind of improvement method of thick film SOI-LIGBT device and its latch-up immunity | |
| CN105870180B (en) | Double division trench gate charge storage type RC-IGBT and its manufacturing method | |
| CN103633087A (en) | Strong anti-latch-up controllable LIGBT (Lateral Insulated Gate Bipolar Transistor) device with ESD (Electro-Static Discharge) protective function | |
| CN102522404B (en) | Bidirectional SCR ESD protective circuit for low triggered voltage | |
| CN110504307A (en) | A kind of SA-LIGBT device with grid-control collector | |
| CN105789291B (en) | A kind of double division trench gate charge storage type IGBT and its manufacturing method | |
| CN110518059A (en) | Longitudinal floating field plate device and its manufacturing method with charge balance Withstand voltage layer | |
| CN104934466B (en) | The LIGBT devices and manufacture method that a kind of anode is raised | |
| CN102832213B (en) | Lateral insulator gate bipolar transistor (LIGBT) device with electronic static discharge (ESD) protection function | |
| CN102130153A (en) | Silicon-on-insulator N-type transverse insulated gate bipolar transistor and preparation method thereof | |
| CN106098764B (en) | A kind of binary channels RC-LIGBT device and preparation method thereof | |
| CN108010963A (en) | The vertical channel semiconductor devices of saturation voltage with reduction | |
| CN106505106A (en) | A kind of shielding gated power transistors of high avalanche capability and preparation method thereof | |
| CN106098763B (en) | A kind of RC-LIGBT device and preparation method thereof | |
| CN105702674B (en) | A kind of electrostatic discharge protective device | |
| CN209328904U (en) | Semiconductor devices | |
| CN103367396B (en) | Super junction Schottky semiconductor device and preparation method thereof | |
| CN206134681U (en) | Fast -speed slot MOS device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |