CN209328904U - Semiconductor devices - Google Patents
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- CN209328904U CN209328904U CN201822196795.4U CN201822196795U CN209328904U CN 209328904 U CN209328904 U CN 209328904U CN 201822196795 U CN201822196795 U CN 201822196795U CN 209328904 U CN209328904 U CN 209328904U
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Abstract
The utility model provides a kind of semiconductor devices, including first electrode layer, substrate layer, N-type drift region, source configuration and the second electrode lay being cascading；Source configuration includes mutually independent N+ doped region, and around the base area P of each N+ doped region setting, the adjacent base area P is spaced each other；The second electrode lay includes source electrode and gate electrode, source electrode is corresponding and connects N+ doped region and the setting of the base area P, gate electrode corresponds to the setting of the N-type drift region between N+ doped region, the base area P and the adjacent base area P, and is connected between gate electrode and N-type drift region and source configuration by gate oxide；Al is provided between gate oxide and N-type drift regionxGa1‑xN layers, AlxGa1‑xN layers of correspondence simultaneously connect N-type drift region, 0 x≤1 <.Semiconductor devices provided by the utility model has improved accumulation layer resistance and higher working efficiency.
Description
Technical field
The utility model relates to a kind of semiconductor devices.
Background technique
Metal Oxide Semiconductor Field Effect Transistor (Metal Oxide Semiconductor Field Effect
Transistor, MOSFET) it is fast, low in energy consumption because having the advantages that switching speed, and it is widely used in every field.But
MOSFET haves the shortcomings that current density is small, conducting resistance is big.
Utility model content
In view of the problems in the background art, the utility model embodiment provides a kind of semiconductor devices, to improve
Current density reduces conducting resistance.
In order to solve the above-mentioned technical problem, the utility model embodiment provides a kind of semiconductor devices, semiconductor devices packet
Include the first electrode layer being cascading, substrate layer, N-type drift region, source configuration and the second electrode lay；Source configuration packet
Mutually independent N+ doped region is included, and around the base area P of each N+ doped region setting, the adjacent base area P is spaced each other；Second
Electrode layer includes source electrode and gate electrode, and source electrode is corresponding and connects N+ doped region and the setting of the base area P, and gate electrode corresponds to N+ doping
N-type drift region setting between area, the base area P and the adjacent base area P, and lead between gate electrode and N-type drift region and source configuration
Cross gate oxide connection；Al is provided between gate oxide and N-type drift regionxGa1-xN layers, AlxGa1-xN layers of correspondence simultaneously connect
The N-type drift region, 0 x≤1 <.
According to the one aspect of the utility model embodiment, AlxGa1-xN layers with a thickness of 5nm~500nm.
According to the one aspect of the utility model embodiment, AlxGa1-xN layers with a thickness of 10nm~100nm.
According to the one aspect of the utility model embodiment, AlxGa1-xN layers with a thickness of 10nm~50nm.
According to the one aspect of the utility model embodiment, AlxGa1-xIn N layers, 0.1≤x≤0.5.
According to the one aspect of the utility model embodiment, the adjacent base area P passes through N-type drift region interval, AlxGa1-xN
The surface of layer correspondence and the N-type drift region being set between the adjacent base area P.
According to the one aspect of the utility model embodiment, AlxGa1-xN layers of surface towards N-type drift region and grid oxygen
The surface towards N-type drift region for changing layer flushes.
According to the one aspect of the utility model embodiment, AlxGa1-xN layers of length be equal to or less than the adjacent base area P it
Between distance.
According to the one aspect of the utility model embodiment, semiconductor devices is the MOS field of plane formula
Effect transistor MOSFET or insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT).
According to the one aspect of the utility model embodiment, the adjacent base area P is floated by groove interval, the base area P and N-type
The interface moved between area is higher than the bottom surface of groove；Gate electrode, gate oxide and AlxGa1-xN layers are set in groove；Gate electrode with
It is isolated between source electrode by insulating oxide.
According to the one aspect of the utility model embodiment, AlxGa1-xN layers be set to groove be located at interface wall below
Face.
According to the one aspect of the utility model embodiment, semiconductor devices is the MOS field of plough groove type
Effect transistor MOSFET or insulated gate bipolar transistor IGBT.
Semiconductor devices provided by the embodiment of the utility model in the on-state, between gate oxide and N-type drift region
Accumulation layer is formed, electronics can reach N-type drift region by source configuration and through accumulation layer, by gate oxide and N-type
Al is set between drift regionxGa1-xN layers, and make AlxGa1-xN layers of correspondence simultaneously connect N-type drift region, can significantly improve accumulation layer
Current density, reduce conducting resistance, improve the working efficiency of semiconductor devices.
Detailed description of the invention
It, below will be in the utility model embodiment in order to illustrate more clearly of the technical solution of the utility model embodiment
Required attached drawing is briefly described, for those of ordinary skill in the art, what is do not made the creative labor
Under the premise of, it is also possible to obtain other drawings based on these drawings.Attached drawing is not drawn according to actual proportions.
Fig. 1 is the structural schematic diagram for the semiconductor devices that the utility model one embodiment provides.
Fig. 2 is the structural schematic diagram for the plane formula MOSFET that the utility model one embodiment provides.
Fig. 3 is the conducting resistance schematic diagram of plane formula MOSFET in Fig. 2.
Fig. 4 is the structural schematic diagram for the plane formula IGBT that the utility model one embodiment provides.
Fig. 5 is the structural schematic diagram for the grooved MOSFET that the utility model one embodiment provides.
Fig. 6 is the structural schematic diagram for the plough groove type IGBT that another embodiment of the utility model provides.
Label declaration:
110, first electrode layer；
120, substrate layer；121, N+ type substrate layer；122, N+ type buffer layer；123, P+ type current collection layer；
130, N-type drift region；131, accumulation layer；
140, source configuration；141, the base area P；142, N+ doped region；
150, the second electrode lay；151, source electrode；152, gate electrode；153, gate oxide；154,AlxGa1-xN layers；155,
Insulating oxide.
Specific embodiment
The feature and exemplary embodiment of the various aspects of the utility model is described more fully below, in order to keep this practical new
The objects, technical solutions and advantages of type are more clearly understood, and with reference to the accompanying drawings and embodiments, carry out the utility model into one
Step detailed description.It should be understood that specific embodiment described herein is only configured to explain the utility model, it is not configured as
Limit the utility model.To those skilled in the art, the utility model can be in not needing these details
Implement in the case where some details.Below the description of embodiment is used for the purpose of mentioning by showing the example of the utility model
For being better understood to the utility model.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence " including ... ", it is not excluded that including
There is also other identical elements in the process, method, article or equipment of the element.In addition, herein, " multiples' "
The meaning for two or more, " more than ", " following " be include this number.
Fig. 1 schematically shows a kind of semiconductor devices provided by the embodiment of the utility model.Please refer to Fig. 1, this reality
It include the first electrode layer 110 being cascading, substrate layer with a kind of semiconductor devices that novel one embodiment provides
120, N-type drift region 130, source configuration 140 and the second electrode lay 150；Source configuration 140 is adulterated including mutually independent N+
Area 142, and around the base area P 141 of each N+ doped region 142 setting, the adjacent base area P 141 is spaced each other；The second electrode lay
150 include source electrode 151 and gate electrode 152, and source electrode 151 is corresponding and connects N+ doped region 142 and the setting of the base area P 141, grid electricity
Pole 152 corresponds to the N-type drift region 130 between N+ doped region 142, the base area P 141 and the adjacent base area P 141 and is arranged, and gate electrode
It is connected between 152 and N-type drift region 130 and source configuration 140 by gate oxide 153；Gate oxide 153 and N-type are drifted about
Al is provided between area 130xGa1-xN layer 154,0 < x≤1, AlxGa1-xN layer 154 is corresponding and connects N-type drift region 130, grid oxygen
Change layer 153 and covers AlxGa1-xN layer 154 is arranged.
Semiconductor devices provided by the embodiment of the utility model in the on-state, gate oxide 153 and N-type drift region
Accumulation layer 131 is formed between 130, electronics can reach N-type drift region 130 by source configuration 140 and through accumulation layer 131, lead to
It crosses and Al is set between gate oxide 153 and N-type drift region 130xGa1-xN layer 154, and make AlxGa1-xN layer 154 is corresponding and connects
Connect N-type drift region 130, AlxGa1-xN layer 154 can generate the two-dimensional electron gas (two-dimensional of high concentration
Electron gas, 2DEG), to significantly improve the current density of accumulation layer 131, the conducting resistance of semiconductor devices is reduced,
Improve the working efficiency of semiconductor devices.
Further, AlxGa1-xThe thickness of N layer 154 can be required according to the specific targets of semiconductor devices, pass through theory
It calculates, is determined using simulation softwares such as SENTAURUS or SILVACO, achieve the purpose that most preferably to improve accumulation layer resistance.
In some embodiments, AlxGa1-xThe upper thickness limit of N layer 154 can for 30nm, 50nm, 70nm, 100nm,
120nm,150nm,200nm,300nm,400nm,500nm；AlxGa1-xThe lower thickness limit of N layer 154 can for 5nm, 8nm,
10nm、15nm、20nm、30nm、50nm、80nm、100nm、130nm、180nm、200nm。AlxGa1-xThe thickness of N layer 154 can be with
It is any combination of the upper limit or lower limit.
Optionally, AlxGa1-xN layer 154 with a thickness of 5nm~500nm.
Optionally, AlxGa1-xN layer 154 with a thickness of 10nm~100nm.
Optionally, AlxGa1-xN layer 154 with a thickness of 10nm~50nm.
Optionally, AlxGa1-xIn N layer 154,0.1≤x≤0.5.
Optionally, the material of N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.
AlxGa1-xN layer 154 can be after the base area P 141 and N+ doped region 142 are formed, and pass through deposit or other techniques
It is formed.
In some embodiments, it is spaced between the adjacent base area P 141 by N-type drift region 130, AlxGa1-xN layer 154
The surface of N-type drift region 130 for corresponding to and being set between the adjacent base area P 141.
Further, AlxGa1-xThe surface towards N-type drift region 130 of N layer 154 and gate oxide 153 towards N-
The surface of type drift region 130 flushes.
Further, AlxGa1-xThe length of N layer 154 can be equal to or less than the distance between the adjacent base area P 141 L.
Such as AlxGa1-xThe length of N layer 154 is equal to the distance between the adjacent base area P 141 L, can preferably improve accumulation layer 131
Current density reduces the conducting resistance of semiconductor devices.
Semiconductor devices can be plane formula MOSFET.As an example, please with reference to Fig. 2, plane formula MOSFET
Including first electrode layer 110, substrate layer 120, N-type drift region 130, source configuration 140 and the second electrode being cascading
Layer 150；Source configuration 140 includes mutually independent N+ doped region 142, and around the base area P of each N+ doped region 142 setting
141, it is spaced by N-type drift region 130 between the adjacent base area P 141；The second electrode lay 150 includes source electrode 151 and grid electricity
Pole 152, source electrode 151 is corresponding and connects N+ doped region 142 and the setting of the base area P 141, gate electrode 152 corresponding N+ doped region 142, P
N-type drift region 130 between base area 141 and the adjacent base area P 141 is arranged, and gate electrode 152 and N-type drift region 130 and source electrode
It is connected between structure 140 by gate oxide 153；Al is provided between gate oxide 153 and N-type drift region 130xGa1-xN
Layer 154, AlxGa1-xN layer 154 is corresponding and connects N-type drift region 130, and gate oxide 153 covers AlxGa1-xN layer 154 is arranged.
Wherein, first electrode layer 110 is drain electrode.
Substrate layer 120 is N+ type substrate layer 121.Optionally, the material of N+ type substrate layer 121 is Si, SiC, GaAs, GaN
Or other semiconductor materials.
Optionally, the material of N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.
As shown in figure 3, the conducting resistance of plane formula MOSFET includes source contact resistance RCS, source resistance RN+, channel electricity
Hinder RCH, accumulation layer resistance RA, JFET zone resistance RJFET, drift zone resistance RD, resistance substrate RSUB, drain contact resistance RCD.By
Al is provided between gate oxide 153 and N-type drift region 130 in plane formula MOSFETxGa1-xN layer 154, AlxGa1-xN layers
154 can generate the two-dimensional electron gas of high concentration, significantly improve the current density of accumulation layer 131, make accumulation layer resistance RASignificant drop
It is low, to reduce the conducting resistance of semiconductor devices, improve the working efficiency of semiconductor devices.
In order to more clearly show AlxGa1-xThe beneficial effect of N layer 154, is provided in gate oxide 153 and N-type drift region
Al is not provided between 130xGa1-xThe conventional plane formula MOSFET of N layer 154 in gate oxide 153 and N-type drift region 130
Between be provided with AlxGa1-xAs a comparison, conventional plane formula MOSFET and the utility model are real by the plane formula MOSFET of N layer 154
Other features for applying the plane formula MOSFET of example are identical.Wherein, conventional plane formula MOSFET and the utility model embodiment is flat
Cellular size (cell pitch) width W of face formula MOSFET is 20 μm, and the distance between adjacent base area P 141 L is 6 μm,
Al in the plane formula MOSFET of the utility model embodimentxGa1-xN layer 154 with a thickness of 30nm, x=0.3.
Conventional plane formula MOSFET, voltage rating are accumulation layer resistance R under 50VAFor 0.66m Ω cm2, in its electric conduction
Accounting in resistance is 29.5%, is only second to channel resistance RCH.According to formula RA=ρ × L=L/ (q × μn× n), it is available to be somebody's turn to do
Electron amount in the accumulation layer of conventional plane formula MOSFET is n=L/ (q × μn×RA).By between the adjacent base area P 141 away from
From L=6 μm, quantity of electric charge q=1.6 × 10-19C, accumulation layer resistance RA=0.66m Ω cm2, accumulation layer electron mobility μn=
200cm2It is available that/(Vs) brings formula into, accumulation layer electron amount n=2.84 × 1016cm-3。
And the plane formula MOSFET of the utility model embodiment, due between gate oxide 153 and N-type drift region 130
It is provided with AlxGa1-xN layer 154, AlxGa1-xThe two-dimensional electron gas that N layer 154 generates is up to 5 × 1019cm-3, significantly improve accumulation
The current density of layer 131, makes accumulation layer resistance RAIt significantly reduces, is only about 6.6 × 10-4mΩ·cm2, reduce 3 quantity
Grade, the component part compared to other conducting resistances can be ignored substantially, therefore, significantly reduce the conducting of semiconductor devices
Resistance improves the working efficiency of semiconductor devices.
Semiconductor devices can be plane formula IGBT.As an example, include please with reference to Fig. 4, plane formula IGBT
First electrode layer 110, substrate layer 120, N-type drift region 130, source configuration 140 and the second electrode lay being cascading
150；Source configuration 140 includes mutually independent N+ doped region 142, and around the base area P of each N+ doped region 142 setting
141, it is spaced by N-type drift region 130 between the adjacent base area P 141；The second electrode lay 150 includes source electrode 151 and grid electricity
Pole 152, source electrode 151 is corresponding and connects N+ doped region 142 and the setting of the base area P 141, gate electrode 152 corresponding N+ doped region 142, P
N-type drift region 130 between base area 141 and the adjacent base area P 141 is arranged, and gate electrode 152 and N-type drift region 130 and source electrode
It is connected between structure 140 by gate oxide 153；Al is provided between gate oxide 153 and N-type drift region 130xGa1-xN
Layer 154, AlxGa1-xN layer 154 is corresponding and connects N-type drift region 130, and gate oxide 153 covers AlxGa1-xN layer 154 is arranged.
Wherein, first electrode layer 110 is collector.
Substrate layer 120 includes the N+ type buffer layer 122 and P+ type current collection layer 123 being stacked, wherein N+ type buffer layer
122 is adjacent with N-type drift region 130, and P+ type current collection layer 123 and first electrode layer 110 are adjacent.
Optionally, the material of N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.
In some embodiments, the adjacent base area P 141 is by groove interval, between the base area P 141 and N-type drift region 130
Interface be higher than groove bottom surface；Gate electrode 152, gate oxide 153 and AlxGa1-xN layer 154 is set in groove；Gate electrode
It is isolated between 152 and source electrode 151 by insulating oxide 154.
Further, AlxGa1-xN layer 154 is set to the boundary between the base area P 141 and N-type drift region 130 of groove
Face wall surface below.That is AlxGa1-xInterface of the N layer 154 between the base area P 141 and N-type drift region 130 changes hereinafter, reaching
Kind accumulation layer resistance RAEffect.
Optionally, AlxGa1-xN layer 154 be set to the wall surface of groove and the partial sidewall face that is connect with wall surface on,
AlxGa1-xThe top surface of N layer 154 is flushed with the interface between the base area P 141 and N-type drift region 130.In other examples,
AlxGa1-xThe top surface of N layer 154 may also be below the interface between the base area P 141 and N-type drift region 130.Can play compared with
Improve accumulation layer resistance R wellAEffect.
It is understood that can also be the interface between the base area P 141 and N-type drift region 130 of groove with
Under part wall on Al is setxGa1-xN layer 154, such as in groove between the base area P 141 and N-type drift region 130
Al is set in the side wall surface below of interfacexGa1-xN layer 154, is arranged Al on the wall surface of groovexGa1-xN layer 154, or in ditch
It is arranged in the side wall surface below of the interface between the base area P 141 and N-type drift region 130 of slot and on base wall portion face
AlxGa1-xN layer 154, can play improves accumulation layer resistance RAEffect.
Further, when being provided with Al in the side wall surface of groovexGa1-xWhen N layer 154, AlxGa1-xN layer 154 towards N-type
The surface of drift region 130 is flushed with the surface towards source configuration 140 of gate oxide 153.
Semiconductor devices can be grooved MOSFET.As an example, please with reference to Fig. 5, grooved MOSFET
Including first electrode layer 110, substrate layer 120, N-type drift region 130, source configuration 140 and the second electrode being cascading
Layer 150；Source configuration 140 includes mutually independent N+ doped region 142, and around the base area P of each N+ doped region 142 setting
141, by groove interval between the adjacent base area P 141, and the interface between the base area P 141 and N-type drift region 130 is higher than ditch
The bottom surface of slot；The second electrode lay 150 includes source electrode 151 and gate electrode 152, and gate electrode 152 is set in groove, and gate electrode
It is connected between 152 and N-type drift region 130 and source configuration 140 by gate oxide 153；Insulation is covered in the notch of groove
Oxide layer 155, source electrode 151 covers insulating oxide 155 and is arranged, and source electrode 151 is corresponding and connects N+ doped region 142 and P
Base area 141 is arranged；Al is provided between gate oxide 153 and N-type drift region 130xGa1-xN layer 154, AlxGa1-xN layer 154
N-type drift region 130 is corresponded to and connects, gate oxide 153 covers AlxGa1-xN layer 154 is arranged.
Wherein, first electrode layer 110 is drain electrode.
Substrate layer 120 is N+ type substrate layer 121.Optionally, the material of N+ type substrate layer 121 is Si, SiC, GaAs, GaN
Or other semiconductor materials.
Optionally, the material of N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.
Semiconductor devices can be plough groove type IGBT.As an example, include please with reference to Fig. 6, plough groove type IGBT
First electrode layer 110, substrate layer 120, N-type drift region 130, source configuration 140 and the second electrode lay being cascading
150；Source configuration 140 includes mutually independent N+ doped region 142, and around the base area P of each N+ doped region 142 setting
141, by groove interval between the adjacent base area P 141, and the interface between the base area P 141 and N-type drift region 130 is higher than ditch
The bottom surface of slot；The second electrode lay 150 includes source electrode 151 and gate electrode 152, and gate electrode 152 is set in groove, and gate electrode
It is connected between 152 and N-type drift region 130 and source configuration 140 by gate oxide 153；Insulation is covered in the notch of groove
Oxide layer 155, source electrode 151 covers insulating oxide 155 and is arranged, and source electrode 151 is corresponding and connects N+ doped region 142 and P
Base area 141 is arranged；Al is provided between gate oxide 153 and N-type drift region 130xGa1-xN layer 154, AlxGa1-xN layer 154
N-type drift region 130 is corresponded to and connects, gate oxide 153 covers AlxGa1-xN layer 154 is arranged.
Wherein, first electrode layer 110 is collector.
Substrate layer 120 includes the N+ type buffer layer 122 and P+ type current collection layer 123 being stacked, wherein N+ type buffer layer
122 is adjacent with N-type drift region 130, and P+ type current collection layer 123 and first electrode layer 110 are adjacent.
Optionally, the material of N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.
Above description is only a specific implementation of the present invention, those skilled in the art can be clearly
It solves, for convenience of description and succinctly, the specific work process of the system of foregoing description can refer to aforementioned system embodiment
In be correspondingly connected with structure, details are not described herein.It should be understood that the protection scope of the utility model is not limited thereto, it is any ripe
Know those skilled in the art within the technical scope disclosed by the utility model, can readily occur in various equivalent modifications or
Replacement, these modifications or substitutions should be covered within the scope of the utility model.
Claims (10)
1. a kind of semiconductor devices, which is characterized in that first electrode layer, substrate layer, N-type including being cascading are drifted about
Area, source configuration and the second electrode lay；The source configuration includes mutually independent N+ doped region, and around each N+
The base area P of doped region setting, the adjacent base area P is spaced each other；The second electrode lay includes source electrode and gate electrode, institute
It is corresponding and connect the N+ doped region and the base area P setting to state source electrode, the gate electrode corresponds to the N+ doped region, described
N-type drift region setting between the base area P and the adjacent base area P, and the gate electrode and the N-type drift region and the source
It is connected between the structure of pole by gate oxide；
Al is provided between the gate oxide and the N-type drift regionxGa1-xN layers, the AlxGa1-xN layers of correspondence simultaneously connect
Connect the N-type drift region, 0 x≤1 <.
2. semiconductor devices according to claim 1, which is characterized in that the AlxGa1-xN layers with a thickness of 5nm~
500nm；
Alternatively, the AlxGa1-xN layers with a thickness of 10nm~100nm；
Alternatively, the AlxGa1-xN layers with a thickness of 10nm~50nm.
3. semiconductor devices according to claim 1, which is characterized in that the AlxGa1-xIn N layers, 0.1≤x≤0.5.
4. semiconductor devices according to claim 1-3, which is characterized in that the adjacent base area P passes through institute
State N-type drift region interval, the AlxGa1-xN layers of correspondence and the N-type drift region being set between the adjacent base area P
Surface.
5. semiconductor devices according to claim 4, which is characterized in that the AlxGa1-xN layers towards the N-type float
The surface for moving area is flushed with the surface towards the N-type drift region of the gate oxide.
6. semiconductor devices according to claim 4, which is characterized in that the AlxGa1-xN layers of length is equal to or less than
The distance between adjacent described base area P.
7. semiconductor devices according to claim 4, which is characterized in that the semiconductor devices is the metal oxygen of plane formula
Compound semiconductor field effect transistor MOSFET or insulated gate bipolar transistor IGBT.
8. semiconductor devices according to claim 1-3, which is characterized in that the adjacent base area P passes through ditch
Slot interval, the interface between the base area P and the N-type drift region are higher than the bottom surface of the groove；
The gate electrode, the gate oxide and the AlxGa1-xN layers are set in the groove；
It is isolated between the gate electrode and the source electrode by insulating oxide.
9. semiconductor devices according to claim 8, which is characterized in that the AlxGa1-xN layers are set to the groove
Positioned at interface wall surface below.
10. semiconductor devices according to claim 8, which is characterized in that the semiconductor devices is the metal of plough groove type
Oxide semiconductor field effect transistor MOSFET or insulated gate bipolar transistor IGBT.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822196795.4U CN209328904U (en) | 2018-12-26 | 2018-12-26 | Semiconductor devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822196795.4U CN209328904U (en) | 2018-12-26 | 2018-12-26 | Semiconductor devices |
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Family
ID=67728719
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109599434A (en) * | 2018-12-26 | 2019-04-09 | 瑞能半导体有限公司 | Semiconductor devices |
| CN114843346A (en) * | 2022-06-29 | 2022-08-02 | 瑞能半导体科技股份有限公司 | Low resistance trench type silicon carbide transistor and method of manufacturing the same |
-
2018
- 2018-12-26 CN CN201822196795.4U patent/CN209328904U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109599434A (en) * | 2018-12-26 | 2019-04-09 | 瑞能半导体有限公司 | Semiconductor devices |
| CN114843346A (en) * | 2022-06-29 | 2022-08-02 | 瑞能半导体科技股份有限公司 | Low resistance trench type silicon carbide transistor and method of manufacturing the same |
| CN114843346B (en) * | 2022-06-29 | 2022-09-20 | 瑞能半导体科技股份有限公司 | Low-resistance trench type silicon carbide transistor and manufacturing method thereof |
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