CN107256885B - High-reliability insulated gate bipolar transistor and manufacturing method thereof - Google Patents
High-reliability insulated gate bipolar transistor and manufacturing method thereof Download PDFInfo
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- CN107256885B CN107256885B CN201710524879.3A CN201710524879A CN107256885B CN 107256885 B CN107256885 B CN 107256885B CN 201710524879 A CN201710524879 A CN 201710524879A CN 107256885 B CN107256885 B CN 107256885B
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Abstract
The invention provides a high-reliability Insulated Gate Bipolar Transistor (IGBT), which comprises an N-type monocrystalline silicon substrate, P wells positioned on the upper surface of the substrate, isolation grooves with the depth of the P wells not less than the junction depth of the P wells and a groove bottom oxide layer, floating P wells positioned between adjacent isolation grooves, an N + source region close to the upper surface of the P wells, P + shallow wells positioned below an N + source region and adjacent to the isolation grooves, a gate oxide layer positioned on the upper surface of the substrate, a neck region oxide layer with the thickness larger than that of the gate oxide layer positioned between the two P wells, a silicon dioxide layer, a polycrystalline silicon layer, a dielectric layer, an emitter and an emitter contact hole groove spanning and exposing the N + source region and the P + shallow wells and overlapping with the adjacent isolation grooves, a doping layer and a collector positioned on the lower surface of the substrate, and an isolation groove and a groove bottom local oxide layer structure are added on the basis of a conventional self-aligned planar IGBT structure, the whole performance of the IGBT device is improved, and the IGBT device becomes a high-reliability IGBT with radiation resistance.
Description
Technical Field
The invention relates to an insulated gate bipolar transistor, in particular to a high-reliability insulated gate bipolar transistor with radiation resistance and a manufacturing method thereof.
Background
Insulated Gate Bipolar Transistors (IGBTs) are a very rapidly developing power semiconductor device. The IGBT integrates the advantages of the MOSFET and the double-click device, and has the advantages of high gate input impedance, low driving power, simple driving circuit, high switching speed, low switching loss, low on-state voltage and high current processing capacity.
Under the forward working state of the IGBT, a conductance modulation effect exists in the N-drift region, so that the drift region has a large number of electron-hole pairs, and the on-state voltage drop can be reduced. At the surface P well, the pumping action on holes exists, the conductance modulation effect is weakened, and the on-state loss is increased. Therefore, when designing an IGBT device, the P-well design needs to be improved and optimized to reduce the collecting effect of the P-well on the cavity, reduce the on-state voltage drop, and at the same time, facilitate reducing the switching loss, so as to improve the overall performance of the device.
The application field of the IGBT is very wide, and the working environment of the IGBT is also extremely complex. When applied to the plateau environment or the aerospace field, the IGBT can be subjected to various cosmic rays and radiation of high-energy particles. These radiations may cause damages such as threshold voltage drift, burn-out, and gate-through of the IGBT, which may seriously affect the operating performance and reliability of the IGBT. The total dose effect and the single event effect of the ionizing radiation are two common radiation effects of the IGBT device in a radiation environment. The total dose effect of ionizing radiation refers to that when high-energy electromagnetic waves or gamma rays irradiate the IGBT, positive charges are accumulated in a gate oxide layer, so that the threshold voltage and the breakdown voltage of the IGBT drift, and the reliability of a device is influenced. The single event effect means that when cosmic rays or high-energy heavy particles bombard the IGBT, especially under the condition that the heavy particles are incident between two adjacent P wells, the high-energy particles collide lattices in the device to generate a large number of current carriers, so that the device is burnt or gate-through, and the reliability of the IGBT is seriously threatened. Therefore, it is necessary to provide a technical solution for optimizing the structure and manufacturing process of the IGBT, so as to improve the radiation resistance and reliability of the IGBT.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a high-reliability IGBT and a manufacturing method thereof so as to improve the overall performance and reliability of an insulated gate bipolar transistor.
In order to achieve the purpose, the invention provides the following technical scheme:
a high-reliability insulated gate bipolar transistor comprises an N-type monocrystalline silicon substrate 4, a P well 15 on the upper surface of the substrate 4, an isolation groove 10 with the depth not smaller than the junction depth of the P well in the P well, a groove bottom oxide layer 11 of the isolation groove 10, a floating P well 16 between the two isolation grooves, an N + active region 18 on the upper surface of the P well 15, a P + shallow well region 17 below the N + active region 18 and adjacent to the isolation groove, a gate oxide layer 19 positioned on the upper surfaces of the N + active region 18 and the P well 15, a neck region oxide layer 5 with the thickness larger than that of the gate oxide layer 19 between the upper surfaces of the two P wells 15, a silicon dioxide layer I6, a polycrystalline silicon layer 20 and a dielectric layer 21 sequentially arranged on the upper surface of the neck region oxide layer 5, and an emitter 22 and an emitter contact hole groove 23 spanning the N + active region 18, the P + shallow well region 17 and adjacent to the isolation groove 10; and a doping layer 24 and a collector 25 sequentially disposed on the lower surface of the substrate 4.
In a first preferred embodiment of the insulated gate bipolar transistor with high reliability, the bottom oxide layers 11 of adjacent isolation trenches 10 are connected, and the number of the isolation trenches 10 is at least 1.
According to the first preferred scheme of the high-reliability insulated gate bipolar transistor, the groove width of an isolation groove 10 is 0.5-5um, the groove interval is 0.5-2um, the groove depth of the isolation groove 10 is 2-8um, and the distance between the isolation groove 10 and a neck region oxide layer is 55-15 um;
in a first preferred embodiment of the high-reliability insulated gate bipolar transistor, the overlapping size of the emitter contact hole trench 23 and the isolation trench (10) is 0-1 isolation trench width, the trench depth of the isolation trench 10 in the overlapping part is not larger than that of the non-overlapping part, and the trench depth of the non-overlapping part is within the depth range of the P + shallow well region 17;
a manufacturing method of a high-reliability insulated gate bipolar transistor comprises the following steps:
(1) sequentially growing a liner oxide layer 3 and a silicon nitride layer I1 on an N-type monocrystalline silicon manufacturing substrate 4, coating photoresist, and carrying out first photoetching to expose a neck region;
(2) local thermal oxidation, thickening the neck region oxide layer 5, and removing the surface silicon nitride layer I1;
(3) depositing a silicon dioxide layer I6, a silicon nitride layer II 7 and a silicon dioxide layer II 8 in sequence, then coating photoresist for second photoetching, exposing an isolation groove area, etching the silicon dioxide layer I6, the silicon nitride layer II 7, the silicon dioxide layer II 8, the liner oxide layer 3 and the substrate 4 in sequence to form an isolation groove 10, and removing the photoresist;
(4) after depositing a silicon nitride layer III 9, etching the silicon nitride on the clean surface and the bottom of the isolation groove 10 by a dry method;
(5) continuously etching the monocrystalline silicon downwards to form a second silicon groove; performing local thermal oxidation to grow oxide layers on the bottom of the groove in the longitudinal direction and the transverse direction so as to fill the second silicon groove and connect the oxide layers 11 on the bottoms of the adjacent isolation grooves 10;
(6) coating photoresist, carrying out third photoetching to expose the uneven part of the neck region, etching off the top silicon dioxide and the silicon nitride layer in the region, and removing the photoresist;
(7) depositing a silicon dioxide layer III 12, backfilling the isolation groove, and removing silicon nitride after performing chemical mechanical polishing by taking a silicon nitride layer II 7 as a stop layer;
(8) coating photoresist for the fourth time, growing an ion implantation shielding oxide layer 14 in the range of the P well region by using a thermal oxidation method after the P well region is exposed, then carrying out boron ion implantation to form P well doping, and then carrying out high-temperature junction pushing to form a final P well 15;
(9) forming a polysilicon side wall by adopting a side wall growth technology, and then carrying out boron ion implantation to form P + shallow well region doping; removing the side wall of the polycrystalline silicon, and performing arsenic ion implantation to form N + source region doping; then annealing is carried out, so that the impurities of the N + source region and the P + shallow well region are activated, and impurity redistribution is formed;
(10) coating photoresist for the fifth time to expose the gate oxide region, etching silicon dioxide in the region, and removing the photoresist; then thermally growing a gate oxide layer, and then depositing a polycrystalline silicon layer 20 and doping the polycrystalline silicon with phosphorus;
(11) coating photoresist for the sixth time to expose the P well region, etching off the polysilicon in the region, and removing the photoresist;
(12) depositing an isolation dielectric layer 21, coating photoresist for the seventh time to expose an emitter contact hole groove 23, etching the isolation dielectric and silicon to expose the side surface of the n + source region and the P + shallow well region, making the groove depth of the overlapped part of the emitter contact hole and the isolation groove not larger than the groove depth of the non-overlapped part, and removing the photoresist;
(13) growing an aluminum metal emitter 22, then performing an aluminum electrode patterning process including photolithography and etching, an alloy process, a passivation layer growth and patterning process, and finally performing back processing, including: and thinning the back, forming a back doping layer by back ion implantation, and annealing to activate impurities to manufacture a back metal electrode.
A first preferred scheme of a manufacturing method of a high-reliability insulated gate bipolar transistor is that in step 1, dry-oxygen oxidation growth is carried out at the temperature of 900-1000 DEG C
A thick pad oxide layer 3; deposition of silicon nitride layers I1 to
Is thick.
According to a second preferred scheme of the manufacturing method of the high-reliability insulated gate bipolar transistor, in the step (2), the thickness of the neck region oxide layer 5 is 0.5-2 micrometers; in the step (3), a silicon dioxide layer I6 to 0.5 to 2um thick is deposited, and a silicon nitride layer II 7 to 2um thick is deposited
Is thick.
High-reliability insulated gate bipolar transistorIn a third preferred embodiment of the method, in step (8), the thickness of the shielding oxide layer 14 is
At 1 × 10 13 ～5×10 14 cm -2 The boron ions are implanted with the dosage of (1) and the energy of 40-120 kev.
According to a fourth preferred scheme of the manufacturing method of the high-reliability insulated gate bipolar transistor, in the step (10), a gate oxide layer is thermally grown at 800-1000 ℃, and halogen elements are not contained in an oxidizing atmosphere; the polysilicon has a thickness of
Compared with the closest prior art, the technical scheme provided by the invention has the following excellent effects:
the high-reliability insulated gate bipolar transistor structure and the manufacturing method thereof provided by the invention add (multiple) isolation grooves and groove bottom local oxidation layer structures on the basis of the conventional self-aligned planar IGBT structure, and combine with the back gate oxide technology, so that the overall performance of an IGBT device is finally improved, and the IGBT device becomes a high-reliability IGBT with radiation resistance.
Drawings
Fig. 1-17 are schematic cross-sectional views of devices in the process of manufacturing an insulated gate bipolar transistor according to the present invention;
FIG. 18 is a schematic diagram of a transistor according to the present invention;
fig. 19 is a schematic structural diagram of an insulated gate bipolar transistor according to embodiment 1 of the present invention;
fig. 20 is a schematic structural diagram of an insulated gate bipolar transistor according to embodiment 2 of the present invention.
The structure comprises a silicon nitride layer I1, a photoresist obtained by first photoetching on 201, a photoresist obtained by second photoetching on 202, a photoresist obtained by third photoetching on 203, a photoresist obtained by fourth photoetching on 204, a photoresist obtained by fifth photoetching on 205, a photoresist obtained by sixth photoetching on 206, a photoresist obtained by seventh photoetching on 207, a 3-pad oxide layer, a 4-substrate, a 5-neck-region oxide layer, a 6-silicon dioxide layer I, a 7-silicon nitride layer II, a 8-silicon dioxide layer II, a 9-silicon nitride layer III, a 10-isolation groove, an isolation groove obtained by second etching on 101, a 11-groove bottom oxide layer, a 12-silicon dioxide layer III, a silicon dioxide layer left after planarization of 13, a 14-shielding oxide layer, a 15P well, a 16-floating P well, a 17P + shallow polysilicon layer, a 18N + active region, a 19-gate oxide layer, a 20-well region, a 21 dielectric layer, a 22-emitter, a 23-emitter contact hole groove, a 24-doped layer and a 25-collector.
Detailed Description
The technical solutions of the present invention will be described in detail with reference to the accompanying drawings and specific embodiments, and it is to be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The insulated gate bipolar transistor structure of the present invention is shown in fig. 18, and comprises:
the structure comprises an N-type monocrystalline silicon substrate 4, P wells 15 positioned on the upper surface of the substrate, isolation grooves 10 and a groove bottom oxidation layer 11 with the depth not smaller than the junction depth of the P wells in the P wells, floating P wells 16 between adjacent isolation grooves, an N + active region 18 close to the upper surface of the P wells, a P + shallow well region 17 positioned below the N + active region and adjacent to the isolation grooves, a polysilicon layer 20 which is positioned between the upper surfaces of the two P wells and has an anti-radiation effect and is larger than the neck region oxidation layer 5 of a gate oxidation layer, is used as an MOS gate structure, a dielectric layer 21 with an isolation effect, an emitter contact hole groove 23 and an emitter 22 which cross and expose the N + active region and the P + shallow wells and are overlapped with the adjacent isolation grooves, and a doping layer 24 and a collector 25 positioned on the lower surface of the substrate.
The basic function of the isolation trenches 10 in the P-well is to eliminate the collection effect of the bottom of the P-well on the holes injected into the drift region, so that the holes are limited to the side surface of the P-well, thereby improving the conductivity modulation of the drift region and improving the device performance as a whole. With the increase of the withstand voltage level, the doping concentration of the drift region is lower, the thickness of the drift region is larger, the conductivity modulation effect of the drift region needs to be enhanced, and at the moment, the effective P well density needs to be further reduced. In the conventional structure, the P well spacing is increased. In the invention, the original P trap distance can be kept unchanged or the distance can be properly increased (but the increment is smaller than that of the conventional structure), and meanwhile, a plurality of adjacent isolation grooves are arranged in one wide P trap, and the density of the effective P trap is still reduced in practice because the newly increased width of the P trap does not play a role in collecting holes at the bottom. At the same time, the gate-collector capacitance CGC is reduced compared to conventional planar gate structures, since the P-well spacing is unchanged or increased less. Furthermore, the presence of the isolation trenches and their bottom oxide layer can significantly reduce the collector-emitter capacitance CCE. The reduction of the two capacitances is beneficial to the dynamic characteristics of the device.
The isolation groove 10 in the P well is realized by a silicon groove etching process; the isolation groove bottom oxidation layer 11 is formed by secondary groove etching and local thermal oxidation, and the design of the structural parameters and the process parameters is to make the bottom oxidation layers of the adjacent isolation grooves connected so as to make the floating P trap 16 between the adjacent isolation grooves completely suspended. The advantages are that: a) the P trap between the grooves is completely suspended, and even if the upper part of the P trap is connected with an emitter electrode, the P trap can not play a role in collecting holes, so that the collecting effect of the P trap 15 on the holes can be effectively reduced, the conductance modulation effect of the IGBT is improved, and the performance of the device is integrally improved; b) the insulativity of the groove bottom can be enhanced, and the local electric field enhancement caused by the improvement of the withstand voltage level and the increase of the number of the isolation grooves is avoided; c) the requirement on the shape of the groove bottom can be reduced, the flatness, smoothness, roundness and the like of the groove bottom are not as high as those of the groove gate IGBT or MOS gate groove etching process, the process control window can be enlarged, and the process difficulty is reduced.
And the neck region oxide layer 5 is a thickened oxide layer positioned between two adjacent P wells and is realized by local thermal oxidation. The structure improves the voltage strength which can be borne by the oxide layer on the surface of the neck region, is beneficial to improving the single-particle gate penetration effect, reduces the CGC capacitance effect and is also beneficial to improving the switching speed of the IGBT.
The gate oxide layer 19 with the radiation resistance function is prepared by adopting a low-temperature thermal oxidation process at 800-1000 ℃ after high-temperature junction pushing, so that the influence of a high-temperature process in the preparation of a device on the quality of the gate oxide layer is effectively avoided, the density of related traps in the oxide layer is reduced, the radiation resistance total dose effect capability of the IGBT device is improved, and the reliability of the device is improved.
The cell area adopts a self-alignment and side wall (spacer) spacing technology, so that the photoetching times are reduced, the n + area and the cell width are reduced, an inward-contracted P + shallow well area is formed, the transverse resistance of a P well is reduced, the latch-up resistance of the device is improved, the single-particle burning resistance of the device is improved, and the failure rate of cosmic ray induced failure is reduced.
The invention provides a high-reliability IGBT manufacturing method, which comprises the following steps:
the method comprises the following steps: selecting N-type monocrystalline silicon as a substrate 4, carrying out dry-oxygen oxidation at the temperature of 900-
A thick pad oxide layer 3; depositing on the liner oxide layer
A thick silicon nitride layer I1; then, a first photo-etching is performed on the silicon nitride to expose the neck region, the silicon nitride (see fig. 1 above) is etched, and the photoresist is removed.
Step two: performing local thermal oxidation to thicken the oxide layer 5 in the neck region to 0.5-2um (see FIG. 2), and boiling phosphoric acid to remove silicon nitride in the surface layer in large area.
Step three: depositing a 0.5-2um thick silicon dioxide layer I6; then depositing on the silicon dioxide
A thick silicon nitride layer II 7; then silicon dioxide 8 is deposited on the silicon nitride, photoresist 202 is coated on the silicon nitride for the second photoetching, the isolation groove area is exposed, and the silicon dioxide, the silicon nitride, the silicon dioxide, the liner oxide layer and the silicon are etched in sequence to form an isolation groove 10 (see the figure 3 above); wherein the width of the groove is 0.5-5um, the distance between the grooves is 0.5-2um, the distance between the grooves and the local thermal oxidation layer is 5-15um, the depth of the groove is 2-8um, the number of the grooves is increased along with the rise of the withstand voltage grade, and the number is generally 1-30.
Step four: deposition of
And the thick silicon nitride layer III 9 covers the side wall and the bottom of the isolation groove while covering the surface of the substrate (see the figure 4), and then adopts a dry etching method with priority in the vertical direction to etch the silicon nitride on the surface and the bottom of the isolation groove completely, and only the silicon nitride layer on the side wall of the isolation groove is remained (see the figure 5).
Step five: continuously etching the silicon single crystal downwards from the bottom of the original isolation groove to the depth of 0.2-1 um to form an isolation groove 101 (see the figure 6) after the second etching; performing local thermal oxidation: wet oxygen or H 2 +O 2 Mainly synthesizing and oxidizing, and growing a groove bottom oxide layer 11 with enough thickness on the groove bottom in the longitudinal direction and the transverse direction at 1000-1150 ℃, wherein the thickness of the oxide layer is 0.3-1.2 um, so that the oxide layers at the groove bottoms of two adjacent isolation grooves are connected (see the figure 7).
Step six: and the photoresist 203 of the third photoetching is carried out for the third photoetching to expose the uneven part of the neck region, and then the silicon dioxide and the silicon nitride layer (shown in the figure 7) at the topmost layer in the region are etched away to remove the photoresist.
Step seven: depositing a silicon dioxide layer III 12, backfilling the isolation groove to enable the surface of an oxide in the range of the isolation groove to be higher than the position of the silicon dioxide layer II 8 deposited in the step three, then taking the silicon nitride layer as a stop layer (see the figure 8 above), carrying out chemical mechanical polishing to realize surface planarization, and then removing silicon nitride in a large area by using hot phosphoric acid (see the figure 9 above).
Step eight: exposing the photoresist 204 of the fourth photoetching to expose the P well region, etching the silicon dioxide layer I6 (shown in figure 10) in the region with the boundary of the P well being 3-6um away from the local thermal oxide layer and 2-9um away from the isolation groove, removing the photoresist, and growing an ion implantation shielding oxide layer 14 in the range of the P well region by using a thermal oxidation method
Thick and then 1X 10 13 ～5×10 14 cm -2 Performing boron (B +) ion implantation with implantation dosage and energy of 40-120 kev to form a doped P well 15, performing high-temperature junction pushing, and addingThe large P-well junction is deep, with the P-well boundary being 2-9um from the isolation trench (see fig. 11 above).
Step nine: forming a polysilicon side wall 16 by using a side wall growth technology, wherein the lateral thickness of the side wall is 0.2-1 um, then carrying out boron (B +) ion implantation to form a doped P + shallow well region 17, and the implantation dosage of the boron (B +) ion is 1 multiplied by 10 15 ～5×10 15 cm -2 Energy needs to be greater than 100kev (see fig. 12 above); removing the polysilicon sidewall to 3 × 10 15 ～6×10 15 cm -2 Performing arsenic (As +) ion implantation with the implantation dosage and the energy of 60-120 kev to form a doped N + active region 18 (see the figure 13 above); and then annealing is carried out, wherein the annealing temperature is 900-1000 ℃, and the annealing time is 20-40 min, so that the impurities of the N + active region and the P + shallow well region are activated and redistributed (see the figure 14).
Step ten: photoresist 205 of the fifth photolithography exposes the gate oxide region, and etch away the silicon dioxide in the region, and remove the photoresist (see fig. 14 above); then growing a gate oxide layer 19 at a low temperature (800-1000 ℃ dry oxygen without chlorine), and then depositing polycrystalline silicon 20 with the thickness of the polycrystalline silicon
And polysilicon is doped with phosphorus (see fig. 15 above).
Step eleven: photoresist 206 of the sixth photolithography exposes the P-well region and etches away the polysilicon in this region (see fig. 15 above), and the photoresist is removed.
Step twelve: depositing an isolation dielectric layer 21, and then performing seventh photoresist 207 to expose the emitter contact hole groove 23 (see fig. 16 above); the isolation dielectric and silicon are then etched to expose the n + source region side and the P + shallow well region and to make the depth of the overlapping portion of the emitter contact hole and the isolation trench not greater than the depth of the non-overlapping portion (see fig. 17 above), and the photoresist is removed.
Step thirteen: growing an aluminum metal emitter 22, then performing an aluminum electrode patterning process including photolithography and etching, an alloy process, a passivation layer growth and patterning process, and finally performing back processing, including: back side thinning, back side ion implantation to form doped layers, annealing to activate impurities, and making back side metal electrodes (see fig. 18 above).
Example 1
The method for manufacturing the 1200V planar gate high-reliability IGBT insulated gate bipolar transistor shown in fig. 19 according to the present invention is described in detail below with reference to the accompanying drawings, where the P-well only includes one isolation trench according to the withstand voltage design.
The method comprises the following steps: dry oxidizing the N-type monocrystal silicon substrate at 1000 deg.C, and growing
A thick pad oxide layer; depositing on the liner oxide layer
Thick silicon nitride; after the silicon nitride is coated with the photoresist, the photoresist is removed by one-time photoetching to expose the silicon nitride neck region.
Step two: local area thermal oxidation: the oxide layer in the range of the neck area is thickened to be 1um thick, then the hot phosphoric acid is boiled, and the surface silicon nitride is removed in a large area.
Step three: depositing silicon dioxide to 2um thickness and then depositing on the silicon dioxide
Depositing silicon dioxide on the thick silicon nitride, coating photoresist for secondary photoetching, and exposing an isolation groove region; and sequentially etching the silicon dioxide, the silicon nitride, the silicon dioxide, the liner oxide layer and the silicon substrate to form the isolation grooves with the number of 1, the groove width of 5um, the distance from the Locos local oxide layer of 8um and the groove depth of 5 um.
Step four: deposited to a thickness of
The silicon nitride layer covers the surface of the N-type monocrystalline silicon substrate, and then the silicon nitride layer on the surface and at the bottom of the isolation groove is etched by a dry method with priority in the vertical direction after the silicon nitride layer covers the side wall and the bottom of the isolation groove, and the silicon nitride layer on the side wall of the isolation groove is reserved.
Step five: etching the silicon single crystal 0.5um deep downwards to the bottom of the original isolation grooveForming a secondary silicon groove; then carrying out local thermal oxidation: wet oxygen or H 2 +O 2 The synthetic oxidation is mainly carried out, and oxide layers with the thickness of 0.6um grow on the bottoms of the isolation grooves in the longitudinal direction and the transverse direction at the temperature of 1000 ℃, so that the oxide layers at the bottoms of the two adjacent isolation grooves are connected with each other.
Step six: coating a photoresist: and exposing the uneven part of the neck region by third photoetching, etching the silicon dioxide and the silicon nitride layer at the topmost layer in the neck region, and removing the photoresist.
Step seven: depositing silicon dioxide with the thickness more than 2 times of the groove width, backfilling the silicon groove, taking silicon nitride as a stop layer, then carrying out chemical mechanical polishing to realize surface planarization, and removing the silicon nitride in a large area by using hot phosphoric acid.
Step eight: coating photoresist for fourth time of photolithography to expose P well region 4um away from Locos5um boundary and isolation trench, etching silicon dioxide, removing photoresist, and growing ion implantation in P well region by thermal oxidation method
Thick screen oxide layer, then 1 × 10 14 cm -2 And (3) performing boron (B +) ion implantation with implantation dosage and 100kev energy to form P-well doping, and performing high-temperature junction pushing to increase the junction depth of the P-well.
Step nine: the polysilicon sidewall is formed with a lateral thickness of 0.3um by sidewall growth technique and then 1 × 10 15 cm -2 Carrying out boron (B +) ion implantation with implantation dosage and 120kev energy to form P + shallow well region doping; removing the polysilicon sidewall, and then performing a 4 × 10 process 15 cm -2 Performing arsenic (As +) ion implantation with implantation dosage and 120kev energy to form n + source region doping; and then annealing at 1000 ℃ for 40min to activate the impurities of the n + source region and the P + shallow well region and form redistribution.
Step ten: coating photoresist, carrying out fifth photoetching to expose the gate oxide region, etching silicon dioxide in the region, and removing the photoresist; the gate oxide was then grown dry oxygen (chlorine free) at 1000 deg.C followed by deposition
The thickness of the polysilicon is increased to a value of,and polysilicon is doped with phosphorus.
Step eleven: and coating photoresist, performing sixth photoetching to expose the P well region, etching off the polysilicon in the region, and removing the photoresist.
Step twelve: depositing an isolation dielectric layer, then coating photoresist to carry out seventh photoetching, and exposing the metal contact hole; and etching the isolation medium and the silicon to expose the side surface of the n + source region and the P + shallow well region, and removing the photoresist.
Step thirteen: after growing the aluminum metal layer, carrying out an aluminum electrode patterning process including photoetching and etching, an alloy process, a passivation layer growing and patterning process, and finally carrying out back treatment, wherein the back treatment comprises the following steps: and thinning the back, forming a P layer by back ion implantation, and annealing to activate impurities to manufacture a back metal electrode.
Example 2
The following will describe in detail the method for manufacturing a 3300V planar gate high reliability IGBT with high reliability provided in fig. 20 with reference to the accompanying drawings, and its related structure and manufacturing steps are substantially the same as those in embodiment 1, and the P-well includes only three isolation trenches according to the voltage withstanding design, and the back doping layer is implanted with an N-type buffer layer and a back P layer.
The method comprises the following steps: oxidizing the N-type monocrystalline silicon substrate with dry oxygen at 1000 deg.C, and growing
A thick pad oxide layer; depositing on the liner oxide layer
Thick silicon nitride; after the silicon nitride is coated with the photoresist, the photoresist is removed by one-time photoetching to expose the silicon nitride neck region.
Step two: local area thermal oxidation: the oxide layer in the range of the neck area is thickened to be 2um thick, then the hot phosphoric acid is boiled, and the surface silicon nitride is removed in a large area.
Step three: depositing silicon dioxide to 2um thickness and then depositing on the silicon dioxide
Thick silicon nitride, depositing silicon dioxide on the silicon nitride, coating photoresist for secondary photoetching, and exposing the isolation groove region; silicon dioxide, silicon nitride, silicon dioxide, liner oxide layer and silicon substrate are etched in proper order, form quantity for 3, the wide 3um in groove, the 2um in groove interval, apart from LOCOS local oxide layer for 10um and the groove depth is the isolation trench of 6 um.
Step four: deposited to a thickness of
The silicon nitride layer covers the surface of the N-type monocrystalline silicon substrate, and then the silicon nitride layer on the surface and at the bottom of the isolation groove is etched by a dry method with priority in the vertical direction after the silicon nitride layer covers the side wall and the bottom of the isolation groove, and the silicon nitride layer on the side wall of the isolation groove is reserved.
Step five: continuously etching the silicon single crystal to the depth of 0.8um downwards from the bottom of the original isolation groove to form a secondary silicon groove; then carrying out local thermal oxidation: wet oxygen or H 2 +O 2 The synthetic oxidation is mainly carried out, and oxidation layers with the thickness of 1um grow on the bottoms of the isolation grooves in the longitudinal direction and the transverse direction at the temperature of 1000 ℃, so that the oxidation layers at the bottoms of the two adjacent isolation grooves are connected with each other.
Step six: coating a photoresist: and exposing the uneven part of the neck region by third photoetching, etching the silicon dioxide and the silicon nitride layer at the topmost layer in the neck region, and removing the photoresist.
Step seven: depositing silicon dioxide, backfilling the isolation groove, performing chemical mechanical polishing by taking silicon nitride as a stop layer to realize surface planarization, and removing the silicon nitride in a large area by using hot phosphoric acid.
Step eight: coating photoresist to perform fourth photoetching to expose P well region 6um away from Locos5um boundary and isolation groove, etching silicon dioxide, removing photoresist, and growing ion implantation in P well region by thermal oxidation method
Thick barrier oxide layer, then 1.8 × 10 14 cm -2 And (3) carrying out boron (B +) ion implantation with implantation dosage and 100kev energy to form P-well doping, and then carrying out high-temperature junction pushing to increase the junction depth of the P-well.
Step nine: the sidewall of 0.3um lateral thickness polysilicon is formed by sidewall growth technique and then at 5 x 10 15 cm -2 Carrying out boron (B +) ion implantation with implantation dosage and 120kev energy to form P + shallow well region doping; removing the polysilicon sidewall, and then forming a polysilicon layer with a thickness of 8 × 10 15 cm -2 Performing arsenic (As +) ion implantation with implantation dosage and 120kev energy to form n + source region doping; and then annealing at 1000 ℃ for 40min to activate the impurities of the n + source region and the P + shallow well region and form redistribution.
Step ten: coating photoresist, carrying out fifth photoetching to expose the gate oxide region, etching silicon dioxide in the region, and removing the photoresist; the gate oxide was then grown dry oxygen (chlorine free) at 1000 deg.C followed by deposition
And (4) thick polysilicon, and doping the polysilicon with phosphorus.
Step eleven: and coating photoresist, performing sixth photoetching to expose the P well region, etching off the polysilicon in the region, and removing the photoresist.
Step twelve: depositing an isolation dielectric layer, then coating photoresist to carry out seventh photoetching, and exposing the metal contact hole; and etching the isolation medium and the silicon to expose the side surface of the n + source region and the P + shallow well region, and removing the photoresist.
Step thirteen: after growing the aluminum metal layer, carrying out an aluminum electrode patterning process including photoetching and etching, an alloy process, a passivation layer growing and patterning process, and finally carrying out back treatment, wherein the back treatment comprises the following steps: and thinning the back, injecting back ions into the N-type buffer layer and the back P layer, annealing to activate impurities, and manufacturing a back metal electrode.
The finally manufactured high-reliability IGBT with the radiation resistance of 1200V and 3300V inhibits the latch-up effect of the device, reduces the collection effect of a P well on a cavity, reduces the on-state voltage drop, reduces the switching loss of the device, improves the latch-up resistance of the device, is beneficial to improving the single-particle burning resistance of the device, reduces the failure rate of cosmic ray induced failure, and improves the radiation resistance of the IGBT device to the total dose effect, thereby improving the reliability of the device.
The above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and it should be understood by those skilled in the art that the modifications and equivalents of the embodiments of the present invention can be made with reference to the above embodiments, and any modifications and equivalents without departing from the spirit and scope of the present invention are within the scope of the claims of the appended patent application.
Claims (8)
1. A manufacturing method of a high-reliability insulated gate bipolar transistor comprises an N-type monocrystalline silicon substrate (4), a P well (15) on the upper surface of the substrate (4), an isolation groove (10) with the depth not less than the junction depth of the P well and a groove bottom oxide layer (11) of the isolation groove (10) in the P well, a floating P well (16) between the two isolation grooves, an N + active area (18) on the upper surface of the P well (15), a P + shallow well area (17) below the N + active area (18) and adjacent to the isolation groove, a gate oxide layer (19) on the upper surfaces of the N + active area (18) and the P well (15), a silicon dioxide layer I (6), a polycrystalline silicon layer (20) and a dielectric layer (21) are sequentially arranged on the upper surface of the neck oxide layer (5), an emitter (22) and an emitter contact hole trench (23) spanning the N + active region (18), the P + shallow well region (17) and exposed adjacent to the isolation trench (10); the doping layer (24) and the collector electrode (25) are sequentially arranged on the lower surface of the substrate (4);
the method is characterized in that: the manufacturing method comprises the following steps:
(1) growing a liner oxide layer (3) and a silicon nitride layer I (1) on an N-type monocrystalline silicon substrate (4) in sequence, coating photoresist, and carrying out first photoetching to expose a neck region;
(2) local thermal oxidation is carried out, the oxide layer (5) of the neck region is thickened, and then the surface silicon nitride layer I (1) is removed;
(3) depositing a silicon dioxide layer I (6), a silicon nitride layer II (7) and a silicon dioxide layer II (8) in sequence, coating photoresist for second photoetching, exposing an isolation groove area, etching the silicon dioxide layer I (6), the silicon nitride layer II (7), the silicon dioxide layer II (8), a liner oxide layer (3) and a substrate (4) in sequence to form an isolation groove (10), and removing the photoresist;
(4) after depositing the silicon nitride layer III (9), etching the silicon nitride on the clean surface and the bottom of the isolation groove (10) by a dry etching method;
(5) continuously etching the monocrystalline silicon downwards to form a second silicon groove; performing local thermal oxidation to grow oxide layers on the bottom of the groove in the longitudinal direction and the transverse direction so as to fill the second silicon groove and connect the oxide layers (11) on the bottoms of the adjacent isolation grooves (10);
(6) coating photoresist, carrying out third photoetching to expose the uneven part of the neck region, etching to remove the silicon dioxide and the silicon nitride layer on the topmost layer in the uneven part region of the neck region, and removing the photoresist;
(7) depositing a silicon dioxide layer III (12), backfilling the isolation groove (10), and removing silicon nitride after performing chemical mechanical polishing by taking a silicon nitride layer II (7) as a stop layer;
(8) coating photoresist for the fourth time, growing an ion implantation shielding oxide layer (14) in the range of the P well region by using a thermal oxidation method after the P well region is exposed, then carrying out boron ion implantation to form P well doping, and then carrying out high-temperature junction pushing to form a final P well (15);
(9) forming a polysilicon side wall by adopting a side wall growth technology, and then carrying out boron ion implantation to form P + shallow well region doping; removing the side wall of the polycrystalline silicon, and performing arsenic ion implantation to form N + source region doping; then annealing is carried out, so that the impurities of the N + source region and the P + shallow well region are activated, and impurity redistribution is formed;
(10) coating photoresist for the fifth time to expose the gate oxide region, etching silicon dioxide in the region, and removing the photoresist; then thermally growing a gate oxide layer, and then depositing a polycrystalline silicon layer (20) and doping the polycrystalline silicon with phosphorus;
(11) coating photoresist for the sixth time to expose the P well region, etching off the polysilicon in the region, and removing the photoresist;
(12) depositing an isolation dielectric layer (21), coating photoresist for the seventh time to expose an emitter contact hole groove (23), etching the isolation dielectric and silicon to expose the side surface of the n + source region and the P + shallow well region, enabling the groove depth of the overlapped part of the emitter contact hole and the isolation groove to be not larger than the groove depth of the non-overlapped part, and removing the photoresist;
(13) growing an aluminum metal emitter (22), then performing an aluminum electrode patterning process including photolithography and etching, an alloy process, a passivation layer growth and patterning process, and finally performing back processing, including: and thinning the back, forming a back doping layer by back ion implantation, and annealing to activate impurities to manufacture a back metal electrode.
2. The method according to claim 1, wherein the step of forming the insulated gate bipolar transistor comprises: in the step (1), a pad oxide layer (3) with a thickness of 200-1000A is grown by dry-oxidation at a temperature of 900-1000 ℃; silicon nitride I (1) is deposited to a thickness of 500-1000A.
3. The method according to claim 1, wherein the step of forming the insulated gate bipolar transistor comprises: in the step (2), the thickness of the neck region oxide layer (5) is 0.5-2 um; in the step (3), the silicon dioxide layer I (6) is deposited to be 0.5-2um thick, and the silicon nitride layer II (7) is deposited to be 500-1000A thick.
4. The method according to claim 1, wherein the step of forming the insulated gate bipolar transistor comprises the steps of: in the step (8), the thickness of the shielding oxide layer (14) is 200-500A, which is 1 × 10 13 ~5×10 14 cm -2 The boron ions are implanted with the dose of (1) and the energy of 40-120 kev.
5. The method according to claim 1, wherein the step of forming the insulated gate bipolar transistor comprises: in the step (10), the gate oxide layer is thermally grown at 800-1000 ℃, and the oxidizing atmosphere does not contain halogen elements; the thickness of the polycrystalline silicon is 4000-8000A.
6. The method according to claim 1, wherein the method further comprises: and the bottom oxidation layers (11) of the adjacent isolation grooves (10) are connected, and the number of the isolation grooves (10) is at least 1.
7. The method according to claim 1, wherein the method further comprises: isolation groove (10) groove width is 0.5-5um, and the groove interval is 0.5-2um, isolation groove (10) groove depth is 2~8um, distance oxide layer (5) 5~15um are distinguished to the neck.
8. The method according to claim 1, wherein the method further comprises: the size of the mutual overlapping of the emitter contact hole groove (23) and the isolation groove (10) is 0-1 isolation groove width, the groove depth of the isolation groove (10) of the overlapping part is not larger than that of the non-overlapping part, and the groove depth of the non-overlapping part is within the depth range of the P + shallow well region (17).
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