CN203659861U - High-holding-current high-robustness ESD self-protection device of LDMOS-SCR structure - Google Patents
High-holding-current high-robustness ESD self-protection device of LDMOS-SCR structure Download PDFInfo
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- CN203659861U CN203659861U CN201420033295.8U CN201420033295U CN203659861U CN 203659861 U CN203659861 U CN 203659861U CN 201420033295 U CN201420033295 U CN 201420033295U CN 203659861 U CN203659861 U CN 203659861U
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Abstract
A high-holding-current high-robustness ESD self-protection device of an LDMOS-SCR structure can be applied to an on-chip IC high-voltage ESD self-protection circuit. The ESD self-protection device is mainly formed by an P substrate, an P well, an N well, a first P+ injection region, a first N+ injection region, a second P+ injection region, a third P+ injection region, a second N+ injection region, a first field oxygen isolation region, a thin gate oxide layer, a second field oxygen isolation region, a third field oxygen isolation region, a fourth field oxygen isolation region and a polysilicon gate. The ESD protection device of the LDMOS-SCR structure can form an ESD current discharging path with the parasitic LDMOS-SCR structure and an ESD current discharging path formed by connecting two diodes with an LDMOS conducting channel under the effect of high-voltage ESD pulses, so that the ESD current can be rapidly discharged, the holding current and failure current after the device hysteresis triggering are improved; the ESD robustness of the device is enhanced, and the ESD self-protection device is suitable for the ESD self-protection of a high-voltage circuit.
Description
Technical field
The invention belongs to the electrostatic discharge (ESD) protection field of integrated circuit; relate to a kind of high pressure esd protection device; be specifically related to a kind of ESD self-shield device of the LDMOS-SCR structure with high maintenance electric current strong robustness, can be used for improving the reliability of IC high pressure esd protection on sheet.
Background technology
Along with the development of Based Power Integrated Circuit Technology, power integrated circuit (IC) range of application is also more and more wide.Laterally double diffusion isolated gate FET (LDMOS) is to develop indispensable power device last century end rapidly, and in DC power supply, motor driven, is widely used in the high pressure such as automotive electronics, high-power circuit system.But; along with the fast development of semiconductor power integrated technique; in cases of engineering; power integrated circuit suffers the harm of ESD more and more serious, and according to investigations, nearly 37% inefficacy is caused by ESD; therefore; design had both had high reliability, strong robustness, strong anti-breech lock ability, had again the high pressure esd protection device of high performance ratio, was the large technological difficulties of one in whole design of circuit system.
In recent years, people utilize the large electric current of power device, high voltage bearing characteristic, often adopt LDMOS to be both used as power drive pipe at the output port of intelligent power IC, are used as again ESD from protective device.But; facts have proved; the esd protection poor-performing of LDMOS device; once the effect device at high pressure esd pulse triggers back stagnant; just damaged; ESD robustness a little less than, do not reach the electronic product that International Electrotechnical Commission specifies and require manikin to be not less than the electrostatic defending standard (IEC6000-4-2) of 2000 V.Recent years; someone proposes embedded SCR LDMOS to form the device of LDMOS-SCR structure; for high pressure esd protection; compared with common LDMOS device; although the ESD robustness of LDMOS-SCR device significantly improves; but maintain voltage or maintain electric current still lower, device easily enters latch mode.The invention provides a kind of ESD self-shield device scheme of new LDMOS-SCR structure; its one side can form the current drain path of LDMOS-SCR structure; not only can improve the proof voltage ability of device under limited chip area; can also improve current drain efficiency, thus the ESD robustness of enhance device.Device is triggering go back to the ESD current drain path that lags behind and be connected with LDMOS conducting channel by two diodes of design on the other hand, not only can significantly improve the electric current that maintains of device, avoid entering latch mode, and the further ESD robustness of enhance device of energy.
Summary of the invention
For a little less than ubiquitous ESD robustness in existing high pressure ESD protective device, the problem such as anti-breech lock scarce capacity; example design of the present invention a kind of ESD self-shield device of the strong robustness LDMOS-SCR structure with high maintenance electric current; both taken full advantage of the feature that LDOMS device can bear high-voltage breakdown; the domain level that has utilized again device to inject by P+ injection, N trap, P trap and the N+ of particular design; make device under the effect of high pressure esd pulse; form the ESD current drain path of SCR structure, improve secondary failure electric current.Simultaneously by comprehensive balance and rationally control parasitic diode and the relevant domain parameters such as LDMOS conducting channel, can obtain the esd protection device applicable to high pressure IC circuit of high pressure resistant, high maintenance electric current, strong robustness.
The present invention is achieved through the following technical solutions:
A kind of ESD self-shield device of the LDMOS-SCR structure with high maintenance electric current strong robustness; it comprises having the ESD current drain path that two parasitic SCR structures are connected with LDMOS conducting channel with two diodes, maintains electric current with ESD robustness and the raising of enhance device.It is characterized in that: mainly formed by P substrate, P trap, N trap, a P+ injection region, a N+ injection region, the 2nd P+ injection region, the 3rd P+ injection region, the 2nd N+ injection region, first oxygen isolated area, thin gate oxide, second oxygen isolated area, the 3rd oxygen isolated area, the 3rd oxygen isolated area and polysilicon gate;
In the surf zone of described P substrate, be from left to right provided with successively described P trap and described N trap;
In the surf zone of described P trap, from left to right design successively described first oxygen isolated area, a described P+ injection region, a described N+ injection region, described the 2nd P+ injection region;
The left side edge of described first oxygen isolated area is connected with the left side edge of described P substrate, the right side of described first oxygen isolated area is connected with the left side of a described P+ injection region, the right side of a described P+ injection region is connected with the left side of a described N+ injection region, between the left side of the right side of a described P+ injection region and a described N+ injection region, can directly be connected, also can be according to the oxygen isolation of requirements set field or the shallow isolation trench isolation of different esd protections, the right side of a described N+ injection region is connected with the left side of described the 2nd P+ injection region, the right side of a described N+ injection region can directly be connected with the left side of described the 2nd P+ injection region, also can keep the horizontal spacing of certain certain value, but must ensure must be able to not have an oxygen isolation or shallow isolation trench isolation between the right side of a described N+ injection region and the left side of described the 2nd P+ injection region,
In described N trap surface element subregion, be provided with successively described second oxygen isolated area, described the 3rd P+ injection region, described the 3rd oxygen isolated area, described the 2nd N+ injection region and described the 4th oxygen isolated area;
Described polysilicon gate covers the surface element subregion of described thin gate oxide and described second the oxygen isolated area of part, the described thin gate oxide of described polysilicon gate and covering thereof and described second oxygen isolated area are across the surface element subregion at described P trap and described N trap, and the right side of described the 2nd P+ is connected with the described thin gate oxide of described polysilicon gate and covering thereof, and the right side of described second oxygen isolated area is connected with the left side of described the 3rd P+ injection region;
The right side of described the 3rd P+ is connected with the left side of described the 3rd oxygen isolated area, the right side of described the 3rd oxygen isolated area is connected with the left side of described the 2nd N+ injection region, the right side of described the 2nd N+ injection region is connected with the left side of described the 4th oxygen isolated area, and the right side of described the 4th oxygen isolated area is connected with the right side edge of described P substrate;
A described P+ injection region is connected with the first metal 1, a described N+ injection region is connected with the first metal 2, described the 2nd P+ injection region is connected with the first metal 3, described polysilicon gate is connected with the first metal 4, described the first metal 1, described the first metal 2 is connected with the second metal 1, and from described the second metal 1 extraction electrode, be used as the metallic cathode of device, described the first metal 3 is connected with the first metal 5 with described the first metal 4, described the 3rd P+ injection region is connected with the first metal 6, described the 2nd N+ is connected with described the first metal 7, described the first metal 6 is connected with the second metal 2 with described the first metal 7, and from described the second metal 2 extraction electrodes, as the metal anode of device.
Useful technique effect of the present invention is:
(1) example device of the present invention takes full advantage of LDMOS device and can bear the feature of high-voltage breakdown, improve the high-voltage resistance capability of device, form the ESD current drain path of one article of SCR structure by described metal anode, described the 3rd P+ injection region, described N trap, described P trap, a described N+ injection region and described metallic cathode, to improve secondary failure electric current, the enhancing ESD robustness of device.
(2) example of the present invention utilizes described metal anode, forms a parasitic diode D1 by described the 3rd P+ injection region and described N trap, by forming LDMOS conducting channel between the grid thin oxide layer of described polysilicon gate and covering thereof and described P trap, form another parasitic diode D2 by described the 2nd P+ injection region and a described N+ injection region, the ESD current drain path being formed by described parasitic diode D1, described LDMOS conducting channel and described parasitic diode D2, can improve device trigger back lag behind maintain electric current and inefficacy electric current, the ESD robustness of enhance device.
(3) example device of the present invention can also be by regulating the described thin gate oxide of described polysilicon gate and covering thereof the surperficial lateral length that is connected with described P trap; according to different ESD design windows; obtain meeting engineering practice required maintain electric current and ESD robustness, make device can be applied to the high pressure esd protection in the power integrated circuit product of different demands.
brief description of the drawings
Fig. 1 is the internal structure generalized section of the embodiment of the present invention;
Fig. 2 is the circuit connection diagram of example of the present invention for high pressure esd protection;
Fig. 3 is the equivalent electric circuit under the esd pulse effect of example device of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Example design of the present invention a kind of ESD self-shield device of the LDMOS-SCR structure with high maintenance electric current strong robustness, both taken full advantage of the high pressure resistant feature of LDMOS device, utilize again the feature of SCR device low on-resistance, large current drain ability, utilize another current lead-through path being connected to form by two parasitic diodes and LDMOS conducting channel, can increase on the one hand at device and trigger back the electric current that maintains lagging behind; On the other hand, can also increase the ESD current drain ability after break-over of device, the ESD robustness of enhance device.And by adjusting some crucial layout size parameter, can make device meet the high pressure esd protection in the power integrated circuit product of different demands.
The profile of example device inside structure of the present invention as shown in Figure 1; be specially a kind of ESD self-shield device of the LDMOS-SCR structure with high maintenance electric current strong robustness; there are two ESD current drain paths that SCR structure is connected with LDMOS conducting channel with two diodes; with the ESD robustness of enhance device, improve and maintain electric current.It is characterized in that: comprise that P substrate 101, P trap 102, N trap 103, a P+ injection region 104, a N+ injection region 105, the 2nd P+ injection region 106, the 3rd P+ injection region 107, the 2nd N+ injection region 108, first oxygen isolated area 109, thin gate oxide 110, second oxygen isolated area 111, the 3rd oxygen isolated area 112, the 4th oxygen isolated area 113 and polysilicon gate 114 form.
In the surf zone of described P substrate 101, be from left to right provided with successively described P trap 102 and described N trap 103.
In the surf zone of described P trap 102, from left to right design successively described first oxygen isolated area 109, a described P+ injection region 104, a described N+ injection region 105, described the 2nd P+ injection region 106.
The left side edge of described first oxygen isolated area 109 is connected with the left side edge of described P substrate 101, the right side of described first oxygen isolated area 109 is connected with the left side of a described P+ injection region 104, the right side of a described P+ injection region 104 is connected with the left side of a described N+ injection region 105, between the left side of the right side of a described P+ injection region 104 and a described N+ injection region 105, can directly be connected, also can be according to the oxygen isolation of requirements set field or the shallow isolation trench isolation of different esd protections, to regulate the dead resistance of P trap 102, meet the trigger voltage of different demands, the right side of a described N+ injection region 105 is connected with the left side of described the 2nd P+ injection region 106, the right side of a described N+ injection region 105 can directly be connected with the left side of described the 2nd P+ injection region 106, also can keep the horizontal spacing of certain certain value, but must ensure must be able to not have an oxygen isolation or shallow isolation trench isolation between the right side of a described N+ injection region 105 and the left side of described the 2nd P+ injection region 106, to form a parasitic diode structure.
In described N trap 103 surface element subregions, be provided with successively described second oxygen isolated area 111, described the 3rd P+ injection region 107, described the 3rd oxygen isolated area 112, described the 2nd N+ injection region 108 and described the 4th oxygen isolated area 113.
Described polysilicon gate 114 covers the surface element subregion of described thin gate oxide 110 and described second the oxygen isolated area 111 of part, described polysilicon gate 114 and the described thin gate oxide 110 covering thereof and described second oxygen isolated area 111 are across the surface element subregion at described P trap 102 and described N trap 103, and the right side of described the 2nd P+ 106 is connected with the described thin gate oxide 110 of described polysilicon gate 114 and covering thereof, and the right side of described second oxygen isolated area 111 is connected with the left side of described the 3rd P+ injection region 107.
Described polysilicon gate 114 and the described thin gate oxide 110 covering thereof are connected surperficial lateral length from described P trap 102 can be according to the demand flexible of different ESD design windows; adjust the different values that maintain electric current, to meet the high pressure esd protection demand of multiple occasion.
The right side of described the 3rd P+ 107 is connected with the left side of described the 3rd oxygen isolated area 112, the right side of described the 3rd oxygen isolated area 112 is connected with the left side of described the 2nd N+ injection region 108, the right side of described the 2nd N+ injection region 108 is connected with the left side of described the 4th oxygen isolated area 113, and the right side of described the 4th oxygen isolated area 113 is connected with the right side edge of described P substrate 101.
Described the 3rd P+ injection region 107 and described N trap 103 form a parasitic diode, another parasitic diode that the conducting channel forming between described polysilicon gate 114 and the grid thin oxide layer 110 covering and described P trap 102 and described the 2nd P+ injection region 106 and a described N+ injection region 105 form, another ESD current drain path that described two parasitic diodes and described conducting channel form, can improve device and trigger back the inefficacy electric current that maintains electric current and device lagging behind, ESD robustness that can enhance device.
As shown in Figure 2, a described P+ injection region 104 is connected with the first metal 1 115, a described N+ injection region 105 is connected with the first metal 2 116, described the 2nd P+ injection region 106 is connected with the first metal 3 117, described polysilicon gate 114 is connected with the first metal 4 118, and described the first metal 1 115, described the first metal 2 116 are connected with the second metal 1 122, and from described the second metal 1 122 extraction electrodes, be used as the metallic cathode of device, connect the electronegative potential of esd pulse.
Described the first metal 3 117 is connected with the first metal 5 119 with described the first metal 4 118, described the 3rd P+ injection region 107 is connected with the first metal 6 120, described the 2nd N+ 108 is connected with described the first metal 7 121, described the first metal 6 120 is connected with the second metal 2 123 with described the first metal 7 121, and from described the second metal 2 123 extraction electrodes, as the metal anode of device, connect the high potential of esd pulse.
As shown in Figure 3, in the time that esd pulse acts on example device of the present invention, described metal anode connects esd pulse high potential (square-wave pulse), described metallic cathode connects esd pulse electronegative potential (ground connection), now example device of the present invention is on the one hand in the time that the voltage in the resistance R 2 on described P substrate 101 and described P trap 102 rises to 0.7 V, the emitter positively biased of parasitic NPN pipe T2, along with esd pulse further increases, avalanche multiplication effect in the reverse-biased PN junction that described N trap 103 and described P trap 102 form constantly strengthens, and the concentration that causes minority carrier in space charge region is while far exceeding majority carrier, while making voltage in the resistance R 1 on described N trap also rise to 0.7 V, parasitic PNP pipe T1 triggers and opens, form by described the 3rd P+ injection region 107, described N trap 103, described P substrate 101, described P trap 102, the parasitic SCR structure that a described N+ injection region 105 the forms ESD electric current of releasing.Form a parasitic diode D1 by described the 3rd P+ injection region 107 and described N trap 103 on the other hand, by described grid thin oxide layer 110 and the LDMOS conducting channel that described P trap 102 forms and another parasitic diode D2 being formed by described the 2nd P+ injection region 106 and a described N+ injection region 105 of described polysilicon gate 114 and covering thereof, described parasitic diode D1 is connected with described parasitic diode D2 with described LDMOS conducting channel, form Article 2 ESD current drain path, can improve device secondary failure electric current and maintain electric current, the ESD robustness of enhance device.
Finally explanation is, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement technical scheme of the present invention, and not departing from aim and the scope of technical solution of the present invention, it all should be encompassed in the middle of claim scope of the present invention.
Claims (3)
1. one kind has the ESD self-shield device of the LDMOS-SCR structure of high maintenance electric current strong robustness, it comprises having two ESD current drain paths that are connected with LDMOS conducting channel with two diodes by parasitic LDMOS-SCR structure respectively, with enhance device trigger back lag behind maintain electric current and inefficacy electric current, improve the ESD robustness of device, it is characterized in that: mainly by P substrate (101), P trap (102), N trap (103), the one P+ injection region (104), the one N+ injection region (105), the 2nd P+ injection region (106), the 3rd P+ injection region (107), the 2nd N+ injection region (108), first oxygen isolated area (109), thin gate oxide (110), second oxygen isolated area (111), the 3rd oxygen isolated area (112), the 4th oxygen isolated area (113) and polysilicon gate (114) form,
In the surf zone of described P substrate (101), be from left to right provided with successively described P trap (102) and described N trap (103);
In the surf zone of described P trap (102), from left to right design successively described first oxygen isolated area (109), a described P+ injection region (104), a described N+ injection region (105), described the 2nd P+ injection region (106);
The left side edge of described first oxygen isolated area (109) is connected with the left side edge of described P substrate (101), the right side of described first oxygen isolated area (109) is connected with the left side of a described P+ injection region (104), the right side of a described P+ injection region (104) is connected with the left side of a described N+ injection region (105), between the left side of the right side of a described P+ injection region (104) and a described N+ injection region (105), can directly be connected, also can be according to the oxygen isolation of different requirements set field or the shallow isolation trench isolation of esd protection, the right side of a described N+ injection region (105) is connected with the left side of described the 2nd P+ injection region (106), the right side of a described N+ injection region (105) can directly be connected with the left side of described the 2nd P+ injection region (106), also can keep the horizontal spacing of certain certain value, but must ensure can not have an oxygen isolation or shallow isolation trench isolation between the right side of a described N+ injection region (105) and the left side of described the 2nd P+ injection region (106),
In described N trap (103) surface element subregion, be provided with successively described second oxygen isolated area (111), described the 3rd P+ injection region (107), described the 3rd oxygen isolated area (112), described the 2nd N+ injection region (108) and described the 4th oxygen isolated area (113);
Described polysilicon gate (114) covers the surface element subregion of described thin gate oxide (110) and described second the oxygen isolated area of part (111), described polysilicon gate (114) and the described thin gate oxide (110) covering thereof and described second oxygen isolated area (111) are across the surface element subregion at described P trap (102) and described N trap (103), and the right side of described the 2nd P+ (106) is connected with the described thin gate oxide (110) of described polysilicon gate (114) and covering thereof, the right side of described second oxygen isolated area (111) is connected with the left side of described the 3rd P+ injection region (107),
The right side of described the 3rd P+ (107) is connected with the left side of described the 3rd oxygen isolated area (112), the right side of described the 3rd oxygen isolated area (112) is connected with the left side of described the 2nd N+ injection region (108), the right side of described the 2nd N+ injection region (108) is connected with the left side of described the 4th oxygen isolated area (113), and the right side of described the 4th oxygen isolated area (113) is connected with the right side edge of described P substrate (101);
A described P+ injection region (104) is connected with the first metal 1 (115), a described N+ injection region (105) is connected with the first metal 2 (116), described the 2nd P+ injection region (106) is connected with the first metal 3 (117), described polysilicon gate (114) is connected with the first metal 4 (118), described the first metal 1 (115), described the first metal 2 (116) is connected with the second metal 1 (122), and from described the second metal 1 (122) extraction electrode, be used as the metallic cathode of device, described the first metal 3 (117) is connected with the first metal 5 (119) with described the first metal 4 (118), described the 3rd P+ injection region (107) is connected with the first metal 6 (120), described the 2nd N+ (108) is connected with described the first metal 7 (121), described the first metal 6 (120) is connected with the second metal 2 (123) with described the first metal 7 (121), and from described the second metal 2 (123) extraction electrodes, as the metal anode of device.
2. the ESD self-shield device of a kind of LDMOS-SCR structure with high maintenance electric current strong robustness as claimed in claim 1, it is characterized in that: described metal anode, form a parasitic diode D1 by described the 3rd P+ injection region (107) and described N trap (103), by forming LDMOS conducting channel between described polysilicon gate (114) and the grid thin oxide layer (110) covering and described P trap (102), form another parasitic diode D2 by described the 2nd P+ injection region (106) and a described N+ injection region (105), by described parasitic diode D1, the ESD current drain path that described LDMOS conducting channel and described parasitic diode D2 form, can improve device trigger back lag behind maintain electric current and inefficacy electric current, the ESD robustness of enhance device.
3. the ESD self-shield device of a kind of LDMOS-SCR structure with high maintenance electric current strong robustness as claimed in claim 1; it is characterized in that: described polysilicon gate (114) and the described thin gate oxide (110) covering thereof are connected surperficial lateral length from described P trap (102) can be according to the demand flexible of different ESD design windows, to meet the high pressure esd protection demand of multiple occasion.
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| CN201420033295.8U CN203659861U (en) | 2014-01-20 | 2014-01-20 | High-holding-current high-robustness ESD self-protection device of LDMOS-SCR structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730462A (en) * | 2014-01-20 | 2014-04-16 | 江南大学 | ESD self-protection device with LDMOS-SCR structure and high in holding current and robustness |
| CN111696982A (en) * | 2020-06-09 | 2020-09-22 | 深圳能芯半导体有限公司 | Substrate-separated N-type power tube ESD circuit and setting method |
-
2014
- 2014-01-20 CN CN201420033295.8U patent/CN203659861U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730462A (en) * | 2014-01-20 | 2014-04-16 | 江南大学 | ESD self-protection device with LDMOS-SCR structure and high in holding current and robustness |
| CN103730462B (en) * | 2014-01-20 | 2016-03-02 | 江南大学 | A kind of ESD self-protection device with the LDMOS-SCR structure of high maintenance electric current strong robustness |
| CN111696982A (en) * | 2020-06-09 | 2020-09-22 | 深圳能芯半导体有限公司 | Substrate-separated N-type power tube ESD circuit and setting method |
| CN111696982B (en) * | 2020-06-09 | 2023-10-03 | 深圳能芯半导体有限公司 | Substrate separation N-type power tube ESD circuit and setting method |
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