CN104269402A - High-voltage ESD protective circuit with stacked SCR-LDMOS - Google Patents
High-voltage ESD protective circuit with stacked SCR-LDMOS Download PDFInfo
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- CN104269402A CN104269402A CN201410450092.3A CN201410450092A CN104269402A CN 104269402 A CN104269402 A CN 104269402A CN 201410450092 A CN201410450092 A CN 201410450092A CN 104269402 A CN104269402 A CN 104269402A
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- 230000001681 protective effect Effects 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 23
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 54
- 229910052760 oxygen Inorganic materials 0.000 claims description 48
- 239000001301 oxygen Substances 0.000 claims description 48
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 26
- 229920005591 polysilicon Polymers 0.000 claims description 26
- 238000012423 maintenance Methods 0.000 abstract description 20
- 238000005516 engineering process Methods 0.000 abstract description 7
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000001960 triggered effect Effects 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 238000011160 research Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Abstract
The invention provides a high-voltage ESD protective circuit with stacked SCR-LDMOS, and belongs to the field of electronic technologies. The high-voltage ESD protective circuit comprises one NLDMOS, one resistor 232 and N SCR-LDMOS stacking units. Each SCR-LDMOS stacking unit comprises an SCR-LDMOS device and a trigger resistor, wherein the N is larger than or equal to 2. N+2 P-typed heavily doped regions are further arranged on a substrate to serve as protection rings and connected to the ground. According to the circuit, through breakdown of the LDMOS, the stacked SCR-LDMOS is triggered, and the maintenance voltage is increased without increasing the trigger voltage by the adoption of the stacked SCR-LDMOS.
Description
Technical field
The invention belongs to electronic technology field; be specifically related to Electro-static Driven Comb (the ElectroStatic Discharge of semiconductor integrated circuit chip; referred to as ESD) protecting circuit designed technology; espespecially a kind of transverse diffusion metal oxide semiconductor field effect transistor LDMOS (Laterally Diffused Metal Oxide Semiconductor; be called for short LDMOS) trigger the high-voltage ESD protective circuit of stacking SCR-LDMOS (the Silicon Controlled Rectifier of embedded LDMOS, be called for short SCR-LDMOS).
Background technology
Chip production, encapsulation, test, deposit, in handling process, Electro-static Driven Comb (ElectroStatic Discharge, referred to as ESD) is ubiquity as a kind of inevitably natural phenomena.Along with the reduction of integrated circuit technology characteristic size and the development of various advanced technologies, the situation that chip is damaged by ESD phenomenon is more and more general, and relevant research shows, ic failure product 30% all owing to suffering caused by static discharge phenomenon.Therefore, high performance ESD protective device is used to be seemed very important to chip internal circuits protect.
SCR-LDMOS is one of modal ESD protective device, the same with common SCR, has the advantages such as against esd ability is strong.Fig. 1 is traditional SCR-LDMOS ESD protective device, as shown in Figure 1, comprising: P type substrate 101 and high-pressure N-shaped well region 102; P type trap zone 103, two P type heavily doped regions 105 and 107, two N-type heavily doped regions 104 and 106; field oxygen 108, grid oxygen 109 and polysilicon 110.High-pressure N-shaped well region 102 is positioned on P type substrate 101, and the first N-type heavily doped region 104, a P type heavily doped region 105 and P type trap zone 103 are positioned on high-pressure N-shaped well region 102.And a P type heavily doped region 105 is between the first N-type heavily doped region 104 and P type trap zone 103, second N-type heavily doped region 106 and the 2nd P type heavily doped region 107 are positioned on P type trap zone 103, second N-type heavily doped region 106 is between the first P type heavily doped region 105 and the 2nd P type heavily doped region 107, and field oxygen 108, polysilicon 110 and grid oxygen 109 form grid.Its endophyte structure comprises a parasitic PNP triode Q
1(being made up of a P type heavily doped region 105, high-pressure N-shaped well region 102 and P type trap zone 103), a parasitic NPN triode Q
2equivalent resistance substrate R on (being made up of the second N-type heavily doped region 106, P type trap zone 103 and high-pressure N-shaped well region 102) and high-pressure N-shaped well region 102 between a P type heavily doped region 105 and the first N-type heavily doped region 104.One P type heavily doped region 105 and the first N-type heavily doped region 104 connect anode, and the 2nd P type heavily doped region 107 and the second N-type heavily doped region 106 connect negative electrode, and polysilicon 110 connects grid.When anode meets VDD, if polysilicon gate making alive, P type trap zone 103 between second N-type heavily doped region 106 and high-pressure N-shaped well region 102 can form raceway groove, electric current will through resistance substrate R, flow to the first N-type heavily doped region 104 of anode, when electric current is enough large, the pressure drop be added on resistance R makes equivalent triode Q
1emitter junction positively biased, thus open triode Q
1, and Q
1collector current will be Q
2base stage provide electric current, Q
2after conducting, its collector current will be Q
1there is provided base current, final Q
1, Q
2form positive feedback, SCR structure conducting is with ESD electric current of releasing.
SCR-LDMOS relative to the advantage of LDMOS is, under being operated in SCR pattern after unlatching, the SCR from parasitism flows through by electric current, considerably increases ESD relieving capacity.But traditional SCR-LDMOS also has it not enough, and namely ME for maintenance is very low, during as high-voltage ESD protective device, latch-up (latch-up) phenomenon easily occurs.Easily there is latch-up phenomenon because its low-down ME for maintenance result in it when being used as power clamp in SCR-LDMOS, power supply continuous discharge, finally burns out device.
Research shows, effectively ME for maintenance can be improved by stacking SCR-LDMOS, thus improve latch-up phenomenon, Fig. 2 is the stacking structure of conventional two SCR-LDMOS, comprise P type substrate 101, first high-pressure N-shaped well region 102, second high-pressure N-shaped well region 111, first P type trap zone 103, second P type trap zone 112, one P type heavily doped region 120, 2nd P type heavily doped region 105, 3rd P type heavily doped region 107, 4th P type heavily doped region 121, 5th P type heavily doped region 114, 6th P type heavily doped region 116, 7th P type heavily doped region 122, first N-type heavily doped region 104, second N-type heavily doped region 106, 3rd N-type heavily doped region 113, 4th N-type heavily doped region 115, first polysilicon 110, second polysilicon 119, first oxygen 108, second oxygen 117, first grid oxygen 109, second gate oxygen 118, the one high-pressure N-shaped well region 102 in P type heavily doped region 120, first, the 4th high-pressure N-shaped well region 111 in P type heavily doped region 121, second, the 7th P type heavily doped region 122 are positioned on P type substrate 101, wherein the first high-pressure N-shaped well region 102 is between the first P type heavily doped region 120 and the 4th P type heavily doped region 121, and the second high-pressure N-shaped well region 111 is between the 4th P type heavily doped region 121 and the 7th P type heavily doped region 122, first N-type heavily doped region 104, the 2nd P type heavily doped region 105, first P type trap zone 103 are positioned on the first high-pressure N-shaped well region 102, second N-type heavily doped region 106 and the 3rd P type heavily doped region 107 are positioned on the first P type trap zone 103, wherein, 2nd P type heavily doped region 105 is between the first N-type heavily doped region 104 and the second N-type heavily doped region 106, and the second N-type heavily doped region 106 is between the second P type heavily doped region 105 and the 3rd P type heavily doped region 107, 3rd N-type heavily doped region 113, the 5th P type heavily doped region 114 and the second P type trap zone 112 are positioned on the second high-pressure N-shaped well region 111,4th N-type heavily doped region 115 and the 6th P type heavily doped region 116 are positioned on the second P type trap zone 112,5th P type heavily doped region 114 is between the 3rd N-type heavily doped region 113 and the 4th N-type heavily doped region 115, and the 4th N-type heavily doped region 115 is between the 5th P type heavily doped region 114 and the 6th P type heavily doped region 116.Wherein, first N-type heavily doped region 104 and the 2nd P type heavily doped region 105 constitute the anode of SCR-LDMOS1, second N-type heavily doped region 106 and the 3rd P type heavily doped region 107 constitute the negative electrode of SCR-LDMOS1, and the first polysilicon 110, first oxygen 108 and first grid oxygen 109 constitute the grid of SCR-LDMOS1; 3rd N-type heavily doped region 113 and the 5th P type heavily doped region 114 constitute the anode of SCR-LDMOS2,4th N-type heavily doped region 115 and the 6th P type heavily doped region 116 constitute the negative electrode of SCR-LDMOS2, and the second polysilicon 119, second oxygen 117 and second gate oxygen 118 constitute the grid of SCR-LDMOS2; The anode of SCR-LDMOS1 meets VDD; the negative electrode of SCR-LDMOS1 is connected with the grid of SCR-LDMOS1; the negative electrode of SCR-LDMOS1 is connected with the anode of SCR-LDMOS2; the grid of SCR-LDMOS2 and the minus earth of SCR-LDMOS2, a P type heavily doped region, P type heavily doped region the 120, the 4th 121 and the 7th P type heavily doped region 122 are as guard ring ground connection.Although this stacked structure can improve ME for maintenance, also improve puncture voltage, too high puncture voltage just can not reach the object of available protecting internal pull-up circuit simultaneously.Therefore how the emphasis that puncture voltage is the research of stacking SCR-LDMOS high pressure SCR esd protection circuit is effectively reduced.
Summary of the invention
The present invention is directed to the defect that background technology exists; propose the high-voltage ESD protective circuit that a kind of LDMOS triggers stacking SCR-LDMOS; this circuit, by the stacking SCR-LDMOS of breakdown triggering of LDMOS, while not improving trigger voltage, adopts stacking SCR to improve ME for maintenance.
Technical scheme of the present invention is as follows:
The high-voltage ESD protective circuit of a kind of stacking SCR-LDMOS, comprise 1 NLDMOS, 1 resistance 232 and N number of SCR-LDMOS stackable unit, described SCR-LDMOS stackable unit comprises a SCR-LDMOS device and a trigger resistance, wherein N >=2, substrate also have N+2 P type heavily doped region as guard ring ground connection, the grid of described NLDMOS is by resistance 232 ground connection, in described SCR-LDMOS stackable unit, the anode of first SCR-LDMOS connects the drain electrode of NLDMOS and meets VDD, in described SCR-LDMOS stackable unit, the negative electrode of (n-1)th SCR-LDMOS connects the anode of the n-th SCR-LDMOS, wherein, n=2, 3, N, trigger resistance in described SCR-LDMOS stackable unit is connected between the grid of two adjacent SCR-LDMOS, in described SCR-LDMOS stackable unit, first trigger resistance 233 also connects source electrode and the substrate of NLDMOS, in described SCR-LDMOS stackable unit, N number of trigger resistance one end connects the grid of N number of SCR-LDMOS, the other end connects negative electrode and the ground of N number of SCR-LDMOS.
Further, described NLDMOS can also be PLDMOS, and now, the other end of the resistance 232 be connected with grid is connected the anode of first SCR-LDMOS, remaining connected mode with for identical during NLDMOS.
When the number N of described SCR-LDMOS stackable unit is 2, technical scheme of the present invention is:
NLDMOS triggers a high-voltage ESD protective circuit of stacking SCR-LDMOS, as Fig. 3, comprises P type substrate 201, first high-pressure N-shaped well region 202, second high-pressure N-shaped well region 203, third high pressure N-type well region 204, first P type trap zone 205, second P type trap zone 206, 3rd P type trap zone 207, one P type heavily doped region 208, 2nd P type heavily doped region 211, 3rd P type heavily doped region 212, 4th P type heavily doped region 214, 5th P type heavily doped region 216, 6th P type heavily doped region 217, 7th P type heavily doped region 219, 8th P type heavily doped region 221, 9th P type heavily doped region 222, first N-type heavily doped region 209, second N-type heavily doped region 210, 3rd N-type heavily doped region 213, 4th N-type heavily doped region 215, 5th N-type heavily doped region 218, 6th N-type heavily doped region 220, first oxygen 223, second oxygen 224, 3rd oxygen 225, first grid oxygen 229, second gate oxygen 230, 3rd grid oxygen 231, first polysilicon 226, second polysilicon 227, 3rd polysilicon 228, resistance 232, first trigger resistance 233, second trigger resistance 234,
One P type heavily doped region, P type heavily doped region the 217, the 9th, P type heavily doped region the 212, the 6th, P type heavily doped region the 208, the 3rd 222, the first high-pressure N-shaped well region 203 of high-pressure N-shaped well region 202, second and third high pressure N-type well region 204 are positioned on P type substrate 201; Wherein said first high-pressure N-shaped well region 202 is between the first P type heavily doped region 208 and the 3rd P type heavily doped region 212, second high-pressure N-shaped well region 203 is between the 3rd P type heavily doped region 212 and the 6th P type heavily doped region 217, and third high pressure N-type well region 204 is between the 6th P type heavily doped region 217 and the 9th P type heavily doped region 222;
First N-type heavily doped region 209 and the first P type trap zone 205 are positioned on the first high-pressure N-shaped well region 202, second N-type heavily doped region 210 and the 2nd P type heavily doped region 211 are positioned on the first P type trap zone 205, and the second N-type heavily doped region 210 is between the first N-type heavily doped region 209 and the 2nd P type heavily doped region 211; 3rd N-type heavily doped region 213, the 4th P type heavily doped region 214 and the second P type trap zone 206 are positioned on the second high-pressure N-shaped well region 203,4th N-type heavily doped region 215 and the 5th P type heavily doped region 216 are positioned on the second P type trap zone 206,4th P type heavily doped region 214 is between the 3rd N-type heavily doped region 213 and the 4th N-type heavily doped region 215, and the 4th N-type heavily doped region 215 is between the 4th P type heavily doped region 214 and the 5th P type heavily doped region 216; 5th N-type heavily doped region 218, the 7th P type heavily doped region 219 and the 3rd P type trap zone 207 are positioned on third high pressure N-type well region 204,6th N-type heavily doped region 220 and the 8th P type heavily doped region 221 are positioned on the 3rd P type trap zone 207,7th P type heavily doped region 219 is between the 5th N-type heavily doped region 218 and the 6th N-type heavily doped region 220, and the 6th N-type heavily doped region 220 is between the 7th P type heavily doped region 219 and the 8th P type heavily doped region 221;
Wherein said first high-pressure N-shaped well region 202 and upper structure thereof constitute NLDMOS jointly, first N-type heavily doped region 209 is drain electrode, second N-type heavily doped region 210 is source electrode, 2nd P type heavily doped region 211 is substrate contact, first polysilicon 226, first oxygen 223 and first grid oxygen 229 constitute the grid of NLDMOS, and grid is by resistance 232 ground connection;
Second high-pressure N-shaped well region 203 and upper structure thereof constitute SCR-LDMOS1 jointly, 3rd N-type heavily doped region 213 and the 4th P type heavily doped region 214 form anode, 4th N-type heavily doped region 215 and the 5th P type heavily doped region 216 form negative electrode, and the second polysilicon 227, second oxygen 224 and second gate oxygen 230 constitute grid;
Third high pressure N-type well region 204 and upper structure thereof constitute SCR-LDMOS2 jointly, 5th N-type heavily doped region 218 and the 7th P type heavily doped region 219 form anode, 6th N-type heavily doped region 220 and the 8th P type heavily doped region 221 form negative electrode, and the 3rd polysilicon 228, the 3rd oxygen 225 and the 3rd grid oxygen 231 constitute grid;
The grid of NLDMOS is by resistance 232 ground connection, and the anode of SCR-LDMOS1 connects the drain electrode of NLDMOS and meets VDD, and the negative electrode of SCR-LDMOS1 connects the anode of SCR-LDMOS2; The grid of the source electrode of the first trigger resistance 233 1 termination NLDMOS and substrate, SCR-LDMOS1, the grid of another termination second trigger resistance 234 and SCR-LDMOS2; The other end of the second trigger resistance 234 and the minus earth of SCR-LDMOS2; One P type heavily doped region, P type heavily doped region the 212, the 6th, P type heavily doped region the 208, the 3rd 217 and the 9th P type heavily doped region 222 are as guard ring ground connection.
Further, described NLDMOS can also be PLDMOS, and now, the other end of the resistance 232 be connected with grid is connected the anode of SCR-LDMOS1, remaining connected mode with for identical during NLDMOS.
Beneficial effect of the present invention is:
1, the present invention puncture after LDMOS by resistance for the grid of stacking SCR-LDMOS provides voltage, thus trigger stacking SCR-LDMOS and do not increasing on the basis of trigger voltage, the ME for maintenance of stacking SCR-LDMOS significantly improves, thus effectively reduces the risk that latch-up occurs.
2, the ME for maintenance of protective circuit of the present invention is the ME for maintenance sum of stacking SCR-LDMOS; ME for maintenance is greatly improved; effectively reduce the risk that latch-up occurs; the most important thing is that the trigger voltage of this structure depends on the puncture voltage of LDMOS; can't be multiplied along with the increase of the number of series connection SCR-LDMOS, efficiently solve the problem that the puncture voltage that is too low and multiple series connection SCR-LDMOS device of single SCR-LDMOS device ME for maintenance in high pressure esd protection is too high again.
Accompanying drawing explanation
Fig. 1 is existing SCR-LDMOS ESD protective device generalized section;
Fig. 2 is the stacking SCR-LDMOS esd protection circuit structural representations of existing two SCR-LDMOS;
Fig. 3 is the electrical block diagram of the embodiment of the present invention 1;
Fig. 4 is the equivalent circuit diagram of the embodiment of the present invention 1;
Fig. 5 is the equivalent circuit diagram of the embodiment of the present invention 2;
Fig. 6 is the equivalent circuit diagram that LDMOS provided by the invention triggers the high-voltage ESD protective circuit of stacking SCR-LDMOS.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:
The invention provides the high-voltage ESD protective circuit that a kind of LDMOS triggers stacking SCR-LDMOS.This circuit, by the stacking SCR-LDMOS of breakdown triggering of LDMOS, is not improving on the basis of trigger voltage, adopts stacking SCR-LDMOS to improve ME for maintenance.
Embodiment 1:
Fig. 3 triggers the structural representation of the high-voltage ESD protective circuit of stacking SCR-LDMOS for NLDMOS that the present embodiment provides, comprises P type substrate 201, first high-pressure N-shaped well region 202, second high-pressure N-shaped well region 203, third high pressure N-type well region 204, first P type trap zone 205, second P type trap zone 206, 3rd P type trap zone 207, one P type heavily doped region 208, 2nd P type heavily doped region 211, 3rd P type heavily doped region 212, 4th P type heavily doped region 214, 5th P type heavily doped region 216, 6th P type heavily doped region 217, 7th P type heavily doped region 219, 8th P type heavily doped region 221, 9th P type heavily doped region 222, first N-type heavily doped region 209, second N-type heavily doped region 210, 3rd N-type heavily doped region 213, 4th N-type heavily doped region 215, 5th N-type heavily doped region 218, 6th N-type heavily doped region 220, first oxygen 223, second oxygen 224, 3rd oxygen 225, first grid oxygen 229, second gate oxygen 230, 3rd grid oxygen 231, first polysilicon 226, second polysilicon 227, 3rd polysilicon 228, resistance 232, first trigger resistance 233, second trigger resistance 234,
One P type heavily doped region, P type heavily doped region the 217, the 9th, P type heavily doped region the 212, the 6th, P type heavily doped region the 208, the 3rd 222, the first high-pressure N-shaped well region 203 of high-pressure N-shaped well region 202, second and third high pressure N-type well region 204 are positioned on P type substrate 201; Wherein said first high-pressure N-shaped well region 202 is between the first P type heavily doped region 208 and the 3rd P type heavily doped region 212, second high-pressure N-shaped well region 203 is between the 3rd P type heavily doped region 212 and the 6th P type heavily doped region 217, and third high pressure N-type well region 204 is between the 6th P type heavily doped region 217 and the 9th P type heavily doped region 222;
First N-type heavily doped region 209 and the first P type trap zone 205 are positioned on the first high-pressure N-shaped well region 202, second N-type heavily doped region 210 and the 2nd P type heavily doped region 211 are positioned on the first P type trap zone 205, and the second N-type heavily doped region 210 is between the first N-type heavily doped region 209 and the 2nd P type heavily doped region 211; 3rd N-type heavily doped region 213, the 4th P type heavily doped region 214 and the second P type trap zone 206 are positioned on the second high-pressure N-shaped well region 203,4th N-type heavily doped region 215 and the 5th P type heavily doped region 216 are positioned on the second P type trap zone 206,4th P type heavily doped region 214 is between the 3rd N-type heavily doped region 213 and the 4th N-type heavily doped region 215, and the 4th N-type heavily doped region 215 is between the 4th P type heavily doped region 214 and the 5th P type heavily doped region 216; 5th N-type heavily doped region 218, the 7th P type heavily doped region 219 and the 3rd P type trap zone 207 are positioned on third high pressure N-type well region 204,6th N-type heavily doped region 220 and the 8th P type heavily doped region 221 are positioned on the 3rd P type trap zone 207,7th P type heavily doped region 219 is between the 5th N-type heavily doped region 218 and the 6th N-type heavily doped region 220, and the 6th N-type heavily doped region 220 is between the 7th P type heavily doped region 219 and the 8th P type heavily doped region 221;
Wherein said first high-pressure N-shaped well region 202 and upper structure thereof constitute NLDMOS jointly, first N-type heavily doped region 209 is drain electrode, second N-type heavily doped region 210 is source electrode, 2nd P type heavily doped region 211 is substrate contact, first polysilicon 226, first oxygen 223 and first grid oxygen 229 constitute the grid of NLDMOS, and grid is by resistance 232 ground connection;
Second high-pressure N-shaped well region 203 and upper structure thereof constitute SCR-LDMOS1 jointly, 3rd N-type heavily doped region 213 and the 4th P type heavily doped region 214 form anode, 4th N-type heavily doped region 215 and the 5th P type heavily doped region 216 form negative electrode, and the second polysilicon 227, second oxygen 224 and second gate oxygen 230 constitute grid;
Third high pressure N-type well region 204 and upper structure thereof constitute SCR-LDMOS2 jointly, 5th N-type heavily doped region 218 and the 7th P type heavily doped region 219 form anode, 6th N-type heavily doped region 220 and the 8th P type heavily doped region 221 form negative electrode, and the 3rd polysilicon 228, the 3rd oxygen 225 and the 3rd grid oxygen 231 constitute grid;
The grid of NLDMOS is by resistance 232 ground connection, and the anode of SCR-LDMOS1 connects the drain electrode of NLDMOS and meets VDD, and the negative electrode of SCR-LDMOS1 connects the anode of SCR-LDMOS2; The grid of the source electrode of the first trigger resistance 233 1 termination NLDMOS and substrate, SCR-LDMOS1, the grid of another termination second trigger resistance 234 and SCR-LDMOS2; The other end of the second trigger resistance 234 and the minus earth of SCR-LDMOS2; One P type heavily doped region, P type heavily doped region the 212, the 6th, P type heavily doped region the 208, the 3rd 217 and the 9th P type heavily doped region 222 are as guard ring ground connection.
The operation principle that the NLDMOS that embodiment 1 provides triggers the high-voltage ESD protective circuit of stacking SCR-LDMOS is:
Fig. 4 is the equivalent circuit diagram that NLDMOS triggers two stacking SCR-LDMOS: comprise NLDMOS 305, resistance 232,233 and 234, dead resistance 301,302,303 and 304, parasitic transistor Q
3, Q
4, Q
5, Q
6, Q
7and Q
8.Wherein, dead resistance 301 is the second high-pressure N-shaped well region 203 equivalent resistance, and dead resistance 302 is the second P type trap zone 206 equivalent resistance, and dead resistance 303 is third high pressure N-type well region 204 equivalent resistance, and dead resistance 304 is the 3rd P type trap zone 207 equivalent resistance; Parasitic-PNP transistor Q
3be made up of the 4th high-pressure N-shaped well region 203 in P type heavily doped region 214, second and the second P type trap zone 206; Parasitic NPN transistor Q
4be made up of the 4th N-type heavily doped region 215, second P type trap zone 206 and the second high-pressure N-shaped well region 203; Parasitic LDMOS Q
5be made up of the 3rd N-type heavily doped region 213, the 4th N-type heavily doped region 215 and the second P type trap zone 206; Parasitic-PNP transistor Q
6n-type well region 204 and the 3rd P type trap zone 207 is pressed to form by the 7th P type heavily doped region 219, third high; Parasitic NPN transistor Q
7n-type well region 204 is pressed to form by the 6th N-type heavily doped region 220, the 3rd P type trap zone 207 and third high; Parasitic LDMOS Q
8be made up of the 5th N-type heavily doped region 218, the 6th N-type heavily doped region 220 and the 3rd P type trap zone 207.
As can be seen from Figure 4, NLDMOS 305 source electrode is connected with ground by resistance 233 and 234, and the take-off potential of NLDMOS 305 source is zero.Again because the grid of NLDMOS 305 passes through grounding through resistance, so when anode has esd pulse, due to the effect that resistance and grid capacitance are coupled, first NLDMOS 305 punctures, after NLDMOS 305 punctures, snapback phenomenon will be there is in I-V curve, electric current will flow through resistance 233 and 234, the pressure drop of resistance 233 and 234 will be added on the grid of parasitic LDMOS 306 and parasitic LDMOS 307 simultaneously respectively, then raceway groove is formed, and electric current will flow to negative electrode through resistance 301, parasitic LDMOS 306, resistance 303 and parasitic LDMOS 307.When the pressure drop on resistance 301 is more than Q
3during the voltage of emitter junction positively biased, Q
3open, when the pressure drop on resistance 303 is more than Q
5during the voltage of emitter junction positively biased, Q
5open, then electric current will through transistor Q
3, resistance 302, transistor Q
5negative electrode is flowed to resistance 304.When the pressure drop on resistance 302 is more than Q
4during the voltage of emitter junction positively biased, Q
4open, Q
3and Q
4form positive feedback, open first endoparasitic SCR of SCR-LDMOS.When the pressure drop on resistance 304 is more than Q
6during the voltage of emitter junction positively biased, Q
6open, Q
5and Q
6form positive feedback, second endoparasitic SCR of SCR-LDMOS opens.After two endoparasitic SCR open, will there is second time snapback phenomenon in I-V curve, now electric current mainly flows through from stacking SCR-LDMOS, ESD electric current of releasing, and voltage is clamped at the ME for maintenance of stacked structure, and NLDMOS is turned off.
The ME for maintenance of this protective circuit is the ME for maintenance sum of two stacking SCR-LDMOS; ME for maintenance is greatly improved; the effective risk reducing generation latch-up; and the most important thing is that the trigger voltage of this structure depends on the puncture voltage of NLDMOS; can't be multiplied along with the increase of the number of series connection SCR-LDMOS, efficiently solve the problem that the puncture voltage that is too low and multiple series connection SCR-LDMOS device of single SCR-LDMOS device ME for maintenance in high pressure esd protection is too high again.
Embodiment 2:
As shown in Figure 5, embodiment 2, on the basis of embodiment 1, replaces NLDMOS with PLDMOS, and now, the other end of the resistance 232 be connected with PLDMOS grid is connected the anode of SCR-LDMOS1, remaining connected mode with for identical during NLDMOS.The present embodiment is identical with the operation principle of embodiment 1.
Embodiment 2 adopts PLDMOS to replace NLDMOS to trigger stacking SCR-LDMOS structure, because PLDMOS has higher ME for maintenance, make the ME for maintenance after first time snapback higher, this also contributes to antinoise.
Fig. 6 is the equivalent circuit diagram that LDMOS provided by the invention triggers the high-voltage ESD protective circuit of stacking SCR-LDMOS.The present invention can, by stacking more SCR-LDMOS stackable unit 501, make ME for maintenance increase considerably, the more effective generation preventing latch-up.
Claims (4)
1. the high-voltage ESD protective circuit of a stacking SCR-LDMOS, comprise 1 NLDMOS, 1 resistance (232) and N number of SCR-LDMOS stackable unit, described SCR-LDMOS stackable unit comprises a SCR-LDMOS device and a trigger resistance, wherein N >=2, substrate also have N+2 P type heavily doped region as guard ring ground connection, the grid of described NLDMOS is by resistance (232) ground connection, in described SCR-LDMOS stackable unit, the anode of first SCR-LDMOS connects the drain electrode of NLDMOS and meets VDD, in described SCR-LDMOS stackable unit, the negative electrode of (n-1)th SCR-LDMOS connects the anode of the n-th SCR-LDMOS, wherein, n=2, 3, N, trigger resistance in described SCR-LDMOS stackable unit is connected between the grid of two adjacent SCR-LDMOS, in described SCR-LDMOS stackable unit, first trigger resistance (233) also connects source electrode and the substrate of NLDMOS, in described SCR-LDMOS stackable unit, N number of trigger resistance one end connects the grid of N number of SCR-LDMOS, the other end connects negative electrode and the ground of N number of SCR-LDMOS.
2. the high-voltage ESD protective circuit of stacking SCR-LDMOS according to claim 1, is characterized in that, described NLDMOS replaces with PLDMOS, and the other end of the resistance (232) be now connected with grid is connected the anode of first SCR-LDMOS.
3. the high-voltage ESD protective circuit of stacking SCR-LDMOS according to claim 1, is characterized in that, as N=2, the high-voltage ESD protective circuit of described stacking SCR-LDMOS comprises P type substrate (201), first high-pressure N-shaped well region (202), second high-pressure N-shaped well region (203), third high pressure N-type well region (204), first P type trap zone (205), second P type trap zone (206), 3rd P type trap zone (207), one P type heavily doped region (208), 2nd P type heavily doped region (211), 3rd P type heavily doped region (212), 4th P type heavily doped region (214), 5th P type heavily doped region (216), 6th P type heavily doped region (217), 7th P type heavily doped region (219), 8th P type heavily doped region (221), 9th P type heavily doped region (222), first N-type heavily doped region (209), second N-type heavily doped region (210), 3rd N-type heavily doped region (213), 4th N-type heavily doped region (215), 5th N-type heavily doped region (218), 6th N-type heavily doped region (220), first oxygen (223), second oxygen (224), 3rd oxygen (225), first grid oxygen (229), second gate oxygen (230), 3rd grid oxygen (231), first polysilicon (226), second polysilicon (227), 3rd polysilicon (228), resistance (232), first trigger resistance (233), second trigger resistance (234),
One P type heavily doped region (208), the 3rd P type heavily doped region (212), the 6th P type heavily doped region (217), the 9th P type heavily doped region (222), the first high-pressure N-shaped well region (202), the second high-pressure N-shaped well region (203) and third high pressure N-type well region (204) are positioned on P type substrate (201); Wherein said first high-pressure N-shaped well region (202) is positioned between a P type heavily doped region (208) and the 3rd P type heavily doped region (212), second high-pressure N-shaped well region (203) is positioned between the 3rd P type heavily doped region (212) and the 6th P type heavily doped region (217), and third high pressure N-type well region (204) is positioned between the 6th P type heavily doped region (217) and the 9th P type heavily doped region (222);
First N-type heavily doped region (209) and the first P type trap zone (205) are positioned on the first high-pressure N-shaped well region (202), second N-type heavily doped region (210) and the 2nd P type heavily doped region (211) are positioned on the first P type trap zone (205), and the second N-type heavily doped region (210) is positioned between the first N-type heavily doped region (209) and the 2nd P type heavily doped region (211), 3rd N-type heavily doped region (213), 4th P type heavily doped region (214) and the second P type trap zone (206) are positioned on the second high-pressure N-shaped well region (203), 4th N-type heavily doped region (215) and the 5th P type heavily doped region (216) are positioned on the second P type trap zone (206), 4th P type heavily doped region (214) is positioned between the 3rd N-type heavily doped region (213) and the 4th N-type heavily doped region (215), 4th N-type heavily doped region (215) is positioned between the 4th P type heavily doped region (214) and the 5th P type heavily doped region (216), 5th N-type heavily doped region (218), 7th P type heavily doped region (219) and the 3rd P type trap zone (207) are positioned on third high pressure N-type well region (204), 6th N-type heavily doped region (220) and the 8th P type heavily doped region (221) are positioned on the 3rd P type trap zone (207), 7th P type heavily doped region (219) is positioned between the 5th N-type heavily doped region (218) and the 6th N-type heavily doped region (220), 6th N-type heavily doped region (220) is positioned between the 7th P type heavily doped region (219) and the 8th P type heavily doped region (221),
Wherein said first high-pressure N-shaped well region (202) and upper structure thereof constitute NLDMOS jointly, first N-type heavily doped region (209) is drain electrode, second N-type heavily doped region (210) is source electrode, 2nd P type heavily doped region (211) is substrate contact, first polysilicon (226), first oxygen (223) and first grid oxygen (229) constitute the grid of NLDMOS, and grid is by resistance (232) ground connection;
Second high-pressure N-shaped well region (203) and upper structure thereof constitute SCR-LDMOS1 jointly, 3rd N-type heavily doped region (213) and the 4th P type heavily doped region (214) composition anode, 4th N-type heavily doped region (215) and the 5th P type heavily doped region (216) composition negative electrode, the second polysilicon (227), second oxygen (224) and second gate oxygen (230) constitute grid;
Third high pressure N-type well region (204) and upper structure thereof constitute SCR-LDMOS2 jointly, 5th N-type heavily doped region (218) and the 7th P type heavily doped region (219) composition anode, 6th N-type heavily doped region (220) and the 8th P type heavily doped region (221) composition negative electrode, the 3rd polysilicon (228), the 3rd oxygen (225) and the 3rd grid oxygen (231) constitute grid;
The grid of NLDMOS is by resistance (232) ground connection, and the anode of SCR-LDMOS1 connects the drain electrode of NLDMOS and meets VDD, and the negative electrode of SCR-LDMOS1 connects the anode of SCR-LDMOS2; The grid of the source electrode of the first trigger resistance (233) termination NLDMOS and substrate, SCR-LDMOS1, the grid of another termination second trigger resistance (234) and SCR-LDMOS2; The other end of the second trigger resistance (234) and the minus earth of SCR-LDMOS2; One P type heavily doped region (208), the 3rd P type heavily doped region (212), the 6th P type heavily doped region (217) and the 9th P type heavily doped region (222) are as guard ring ground connection.
4. the high-voltage ESD protective circuit of stacking SCR-LDMOS according to claim 3, is characterized in that, described NLDMOS replaces with PLDMOS, and the other end of the resistance (232) be now connected with grid is connected the anode of SCR-LDMOS1.
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| CN105633074A (en) * | 2016-03-10 | 2016-06-01 | 湖南静芯微电子技术有限公司 | Bidirectional silicon controlled rectifier triggered by reverse-biased diode |
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| CN112993959A (en) * | 2019-12-12 | 2021-06-18 | 美光科技公司 | Device with voltage protection mechanism |
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