CN117316947B - ESD protection device - Google Patents
ESD protection device Download PDFInfo
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- CN117316947B CN117316947B CN202311590076.XA CN202311590076A CN117316947B CN 117316947 B CN117316947 B CN 117316947B CN 202311590076 A CN202311590076 A CN 202311590076A CN 117316947 B CN117316947 B CN 117316947B
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- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000000576 coating method Methods 0.000 abstract description 4
- 238000009825 accumulation Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- OUXCBPLFCPMLQZ-WOPPDYDQSA-N 4-amino-1-[(2r,3s,4s,5r)-4-hydroxy-5-(hydroxymethyl)-3-methyloxolan-2-yl]-5-iodopyrimidin-2-one Chemical compound C[C@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C(=O)N=C(N)C(I)=C1 OUXCBPLFCPMLQZ-WOPPDYDQSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses an ESD protection device, which comprises at least one PIN junction; the PIN junction comprises an N well, a P substrate coating the N well and a P well coating the P substrate, wherein the N well is provided with an N well main body and two N well end parts which are respectively integrally connected with two ends of the N well main body, and the N well end parts form a connecting curved surface which is smoothly connected with the side surface of the N well main body. The invention can avoid the corner formation of the N well, and simultaneously, the minimum distance from the end part of the N well to the P well is gradually increased along the direction away from the N well main body, so that the charge accumulation at the edge of the N well is slowly increased, the voltage withstanding of the ESD protection device can be effectively improved, and the ESD protection effect of the ESD protection device is ensured.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly to an ESD protection device.
Background
Static electricity is an objectively occurring natural phenomenon, and electrostatic discharge (Electrostatic Discharge, ESD) is a key factor affecting the reliability of integrated circuit chips. In some applications of the integrated circuit chip, the ports of some integrated circuit chips need to be connected with an external device for providing high voltage signals, and for this purpose, ESD protection devices are disposed at the ports of the integrated circuit chips to prevent the ports of the integrated circuit chips from being damaged by static electricity, and the ESD protection devices can discharge static charges to protect the ports of the integrated circuit chips.
The current common ESD protection device mainly comprises an ESD diode, a grid grounding MOS tube and a silicon controlled rectifier; the N-well of the PIN junction of the existing ESD diode has a plurality of corners, and the corners collect more charges to affect the withstand voltage of the ESD diode, so that the withstand voltage of the existing ESD diode is not high enough.
In view of the above problems, it is necessary to study an ESD protection device having high withstand voltage.
Disclosure of Invention
The invention aims to provide an ESD protection device with high withstand voltage.
In order to achieve the above object, the solution of the present invention is:
An ESD protection device comprising at least one PIN junction; the PIN junction comprises an N well, a P substrate coating the N well and a P well coating the P substrate, wherein the N well is provided with an N well main body and two N well end parts which are respectively integrally connected with two ends of the N well main body, and the N well end parts form a connecting curved surface which is smoothly connected with the side surface of the N well main body.
The connecting curved surface comprises an outer connecting curved surface and an inner connecting curved surface with different curvatures, two sides of the outer connecting curved surface are respectively and smoothly connected with the side surface of the N well main body and the inner connecting curved surface, and the curvature of the inner connecting curved surface is larger than that of the outer connecting curved surface.
The minimum distance between the side surface of the N well main body and the P well is S1, the minimum distance between the junction of the outer junction surface and the inner junction surface and the P well is S2, and the minimum distance between the center of the inner junction surface and the P well is S3, wherein S1 is less than S2 is less than S3.
The connecting curved surface is a hemispherical surface, and the width of the N well main body is twice the curvature radius of the connecting curved surface.
The minimum distance between the side surface of the N well main body and the P well is S1, the minimum distance between the junction of the junction curved surface and the side surface of the N well main body and the P well is S2', and the minimum distance between the center of the junction curved surface and the P well is S3', wherein S1 is less than S2 'and is less than or equal to S3'.
And a P-well bulge part protruding towards the N-well main body is formed at the position, opposite to the N-well main body, of the P-well.
The ESD protection device comprises a plurality of PIN junctions, and the PIN junctions are arranged side by side and in parallel.
After the scheme is adopted, the N well end part of the N well of the PIN junction forms a joint curved surface which is smoothly jointed with the side surface of the N well main body, so that the N well is prevented from forming a corner, and meanwhile, the minimum distance from the N well end part to the P well is gradually increased along the direction away from the N well main body, so that the accumulation of charges at the edge of the N well is slowly increased, the withstand voltage of the ESD protection device can be effectively improved, and the ESD protection effect of the ESD protection device is ensured.
Drawings
Fig. 1 is a schematic structural diagram of a PIN junction according to a first embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a PIN junction according to a second embodiment of the present invention.
Fig. 3 is a graph of PIN junction breakdown voltage versus doping concentration and P substrate width.
Fig. 4 is a graph of the breakdown voltage of a PN junction versus doping concentration and radius of curvature of the PN junction.
Description of the reference numerals:
The PIN junction a is provided with a PIN,
N-well 1, N-well body 11, N-well end 12, junction surface 121, outer junction surface 1211, inner junction surface 1212,
A P-substrate 2 is provided which,
P-well 3, P-well bump 31.
Detailed Description
As shown in fig. 1 and 2, the present invention discloses an ESD protection device comprising at least one PIN junction a; the PIN junction A comprises an N well 1, a P substrate 2 wrapping the N well 1 and a P well 3 wrapping the P substrate 2, wherein the N well 1 is provided with an N well main body 11 and two N well end parts 12 integrally connected with two ends of the N well main body 11 respectively, and the N well end parts 12 form a connecting curved surface 121 which is smoothly connected with the side face of the N well main body 11.
In the invention, the N well end 12 of the N well 1 of the PIN junction forms a jointing curved surface 121 which is smoothly jointed with the side surface of the N well main body 11, so that the N well 1 is prevented from forming a corner, and meanwhile, the minimum distance from the N well end 12 to the P well 3 is gradually increased along the direction away from the N well main body 11, so that the accumulation of charges at the edge of the N well 1 is slowly increased, the withstand voltage of the ESD protection device of the invention can be effectively improved, and the ESD protection effect of the ESD protection device is ensured.
The ESD protection device can comprise a plurality of PIN junctions A, and the PIN junctions A are arranged side by side and in parallel, so that the discharging capability of the ESD protection device to electrostatic charges can be effectively improved.
In order to further explain the technical scheme of the invention, the invention is explained in detail by specific examples.
Embodiment one:
In the first embodiment of the present invention, the connecting curved surface 121 of the N-well 1 includes an outer connecting curved surface 1211 and an inner connecting curved surface 1212 with different curvatures, and two sides of the outer connecting curved surface 1211 are respectively and smoothly connected with the side surface of the N-well body 11 and the inner connecting curved surface 1212, and the curvature of the inner connecting curved surface 1212 is larger than that of the outer connecting curved surface 1211. Wherein, the minimum distance between the side surface of the N-well main body 11 and the P-well is S1, S1 is also the minimum width of the P-substrate 2, the minimum distance between the junction of the outer junction surface 1211 and the inner junction surface 1212 and the P-well is S2, the minimum distance between the center of the inner junction surface 1212 and the P-well is S3, and S1< S2< S3; the minimum value of S1 is determined by the voltage withstand design value of an ESD protection device of the present invention, the doping concentration of N-well 1, the doping concentration of P-substrate 2, and the doping concentration of P-well 3, and the radius of curvature of the inner junction surface 1212 is also determined by the voltage withstand design value of an ESD protection device of the present invention, the doping concentration of N-well 1, the doping concentration of P-substrate 2, and the doping concentration of P-well 3.
To facilitate understanding of the radius of curvature of the outer engagement surface 1211, the radius of curvature of the inner engagement surface 1212, and the design method of S1, S2, and S3 of the first embodiment of the present invention, the following is exemplified:
Taking a 0.11um CMOS process as an example, when the voltage withstand design value of the ESD protection device is required to be larger than 30V, if the doping concentration of the N well 1 and the doping concentration of the P well 3 are both 10 18/cm3, the doping concentration of the P substrate 2 is 10 15/cm3; as can be derived from fig. 3 (fig. 3 can be derived from fig.6.34 of page 200 of "PHYSICS AND Technology of Semiconductor Devices" published in 1967 by a.s. grove, wepi in fig. 3 is P substrate width), the breakdown voltage of the planar junction between the side surface of the N-well body 11 and the P-well 3 is 35V when S1 is 1um, so as to meet the design requirement; meanwhile, as can be obtained from fig. 4 (fig. 4 can be seen from page 197 of "PHYSICS AND Technology of Semiconductor Devices" published in 1967 by a.s. grove, X j in fig. 4 is a radius of curvature of a PN junction), the radius of curvature of the inner junction curved surface 1212 of the N well 1 is 1um, at this time, the breakdown voltage of the curved junction between the junction curved surface 121 of the N well 1 and the P well 3 can reach 44V, and design requirements are met; in view of the foregoing, the first embodiment of the present invention can be configured as follows: s1 is 1um, the curvature radius of the inner connecting curved surface 1212 of the N well 1 is 1um, the curvature radius of the outer connecting curved surface 1211 of the N well 1 is about 2um, S1< S2< S3; through the design, the withstand voltage of the ESD protection device is actually larger than 30V through the actual current sheet test (the current sheet process is the SMIC 110nm CMOS process), and the design requirement is met. By combining the above, the invention can obtain the lower limits of S1, S2 and S3 according to the voltage-withstanding requirement, and then obtain the upper limits of S1, S2 and S3 according to the ESD protection requirement, and further determine the usable ranges of S1, S2 and S3 of the high-voltage-withstanding ESD protection device.
Embodiment two:
In the second embodiment of the present invention, as shown in fig. 2, the connecting curved surface 121 of the N-well 1 is hemispherical, and the width of the N-well body 11 is twice the radius of curvature of the connecting curved surface 121, so as to ensure that the connecting curved surface 121 is smoothly connected with the side surface of the N-well body 11. The minimum distance between the side surface of the N-well body 11 and the P-well is S1, S1 is also the minimum width of the P-substrate 2, the minimum distance between the junction of the junction curved surface 121 and the side surface of the N-well body 11 and the P-well 3 is S2', the minimum distance between the center of the junction curved surface 121 and the P-well 3 is S3', and the value of S1< S2 '. Ltoreq.s 3', S1 is determined by the voltage withstand design value of the ESD protection device, the doping concentration of the N-well 1, the doping concentration of the P-substrate 2, and the doping concentration of the P-well 3 according to the present invention, and the radius of curvature of the junction curved surface 121 is also determined by the voltage withstand design value of the ESD protection device, the doping concentration of the N-well 1, the doping concentration of the P-substrate 2, and the doping concentration of the P-well 3 according to the present invention.
In the second embodiment of the present invention, the P-well 3 is opposite to the N-well body 11 to form a P-well protruding portion 31 protruding toward the N-well body, so that S1 can be effectively reduced, and S1< S2 '. Ltoreq.s3'.
Similarly, in the second embodiment, the lower limits of S1, S2, and S3 can be obtained according to the voltage withstanding requirement, and then the upper limits of S1, S2, and S3 can be obtained according to the ESD protection requirement, so that the usable ranges of S1, S2, and S3 of the high voltage tolerant ESD protection device of the present invention can be determined.
The above examples and drawings are not intended to limit the form or form of the present invention, and any suitable variations or modifications thereof by those skilled in the art should be construed as not departing from the scope of the present invention.
Claims (5)
1. An ESD protection device characterized in that: comprising at least one PIN junction; the PIN junction comprises an N well, a P substrate coated with the N well and a P well coated with the P substrate, wherein the N well is provided with an N well main body and two N well end parts which are respectively integrally connected with two ends of the N well main body, and the N well end parts form a connecting curved surface which is smoothly connected with the side surface of the N well main body;
The connecting curved surface comprises an outer connecting curved surface and an inner connecting curved surface with different curvatures, two sides of the outer connecting curved surface are respectively and smoothly connected with the side surface of the N well main body and the inner connecting curved surface, and the curvature of the inner connecting curved surface is larger than that of the outer connecting curved surface; the minimum distance between the side surface of the N well main body and the P well is S1, the minimum distance between the junction of the outer junction surface and the inner junction surface and the P well is S2, and the minimum distance between the center of the inner junction surface and the P well is S3, wherein S1 is less than S2 is less than S3.
2. An ESD protection device as defined in claim 1, wherein: the ESD protection device comprises a plurality of PIN junctions, and the PIN junctions are arranged side by side and in parallel.
3. An ESD protection device characterized in that: comprising at least one PIN junction; the PIN junction comprises an N well, a P substrate coated with the N well and a P well coated with the P substrate, wherein the N well is provided with an N well main body and two N well end parts which are respectively integrally connected with two ends of the N well main body, and the N well end parts form a connecting curved surface which is smoothly connected with the side surface of the N well main body;
The connecting curved surface is a hemispherical surface, and the width of the N well main body is twice the curvature radius of the connecting curved surface; the minimum distance between the side surface of the N well main body and the P well is S1, the minimum distance between the junction of the junction curved surface and the side surface of the N well main body and the P well is S2', and the minimum distance between the center of the junction curved surface and the P well is S3', wherein S1 is less than S2 'and is less than or equal to S3'.
4. An ESD protection device as defined in claim 3, wherein: and a P-well bulge part protruding towards the N-well main body is formed at the position, opposite to the N-well main body, of the P-well.
5. An ESD protection device as defined in claim 3, wherein: the ESD protection device comprises a plurality of PIN junctions, and the PIN junctions are arranged side by side and in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311590076.XA CN117316947B (en) | 2023-11-27 | 2023-11-27 | ESD protection device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311590076.XA CN117316947B (en) | 2023-11-27 | 2023-11-27 | ESD protection device |
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| CN117316947A CN117316947A (en) | 2023-12-29 |
| CN117316947B true CN117316947B (en) | 2024-05-24 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034814A (en) * | 2010-10-28 | 2011-04-27 | 浙江大学 | Electrostatic discharge protective device |
| CN102142440A (en) * | 2010-12-30 | 2011-08-03 | 浙江大学 | Thyristor device |
| US7999357B1 (en) * | 2008-05-12 | 2011-08-16 | Semiconductor Components Industries, Llc | Electrostatic discharge circuit using forward biased circular-arc shaped steering diodes |
| CN102522401A (en) * | 2011-11-09 | 2012-06-27 | 威盛电子股份有限公司 | Electrostatic discharge protection device |
| CN103928383A (en) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure, and semiconductor structure |
| CN111834358A (en) * | 2019-04-11 | 2020-10-27 | 富士电机株式会社 | Semiconductor integrated circuit having a plurality of transistors |
| CN115663022A (en) * | 2022-11-11 | 2023-01-31 | 湖南三安半导体有限责任公司 | Semiconductor structure and preparation method of semiconductor structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140131710A1 (en) * | 2012-11-15 | 2014-05-15 | Shine C. Chung | Structures and techniques for electro-static discharge (esd) protection using ring structured diodes |
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2023
- 2023-11-27 CN CN202311590076.XA patent/CN117316947B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7999357B1 (en) * | 2008-05-12 | 2011-08-16 | Semiconductor Components Industries, Llc | Electrostatic discharge circuit using forward biased circular-arc shaped steering diodes |
| CN102034814A (en) * | 2010-10-28 | 2011-04-27 | 浙江大学 | Electrostatic discharge protective device |
| CN102142440A (en) * | 2010-12-30 | 2011-08-03 | 浙江大学 | Thyristor device |
| CN102522401A (en) * | 2011-11-09 | 2012-06-27 | 威盛电子股份有限公司 | Electrostatic discharge protection device |
| CN103928383A (en) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure, and semiconductor structure |
| CN111834358A (en) * | 2019-04-11 | 2020-10-27 | 富士电机株式会社 | Semiconductor integrated circuit having a plurality of transistors |
| CN115663022A (en) * | 2022-11-11 | 2023-01-31 | 湖南三安半导体有限责任公司 | Semiconductor structure and preparation method of semiconductor structure |
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Denomination of invention: An ESD protection device Granted publication date: 20240524 Pledgee: Agricultural Bank of China Limited Xiamen Lianqian Branch Pledgor: XIAMEN KTD ELECTRONICS CO.,LTD. Registration number: Y2024980036913 |
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