CN102611093A - Static discharging circuit - Google Patents
Static discharging circuit Download PDFInfo
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- CN102611093A CN102611093A CN2012100750136A CN201210075013A CN102611093A CN 102611093 A CN102611093 A CN 102611093A CN 2012100750136 A CN2012100750136 A CN 2012100750136A CN 201210075013 A CN201210075013 A CN 201210075013A CN 102611093 A CN102611093 A CN 102611093A
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Abstract
The invention relates to a static discharging circuit, which comprises a voltage division circuit, a first N-channel metal oxide semiconductor (NMOS) tube and a second NMOS tube, wherein a positive electrode input end of the voltage division circuit is connected with a high-voltage input end, a negative electrode input end of the voltage division circuit is coupled with the ground, and an output end is connected with a grid electrode of the first NMOS tube and is used for outputting bias voltage conducting the first NMOS tube; a drain electrode of the first NMOS tube is connected with the high-voltage input end, and a source electrode is connected with a drain electrode of the second NMOS tube; and a source electrode of the second NMOS tube is grounded, and a grid electrode of the second NMOS tube is coupled with the ground. The static discharging circuit has the advantages that the circuit voltage resistant value is improved, and meanwhile, the static discharging performance of the static discharging circuit is also improved.
Description
Technical field
The present invention relates to the electronic circuit technology field, particularly a kind of electrostatic discharge circuit.
Background technology
Static discharge (Electrostatic Discharge; ESD) be to cause most of electronic building bricks or electronic system to receive excessively electrically stress (Electrical Overstress; EOS) principal element of destroying; This destruction can cause the nonvolatil damage of semiconductor device, thereby causes the inefficacy of integrate circuit function.Integrated circuit is main with CMOS (CMOS) mainly at present, receives the damage of ESD in order to prevent integrated circuit, usually design ESD circuit in circuit.
Fig. 1 shows the sketch map of the esd protection circuit of GGNMOS structure in the prior art.With reference to figure 1, the esd protection circuit of said GGNMOS (Gate Grounded NMOS, grounded-grid NMOS) structure comprises NMOS pipe N1.The equal ground connection GND of source electrode, grid and substrate of said NMOS pipe N1, drain electrode connects the PAD pad.
In the structure of said NMOS pipe N1, the N of its drain electrode
+Doped region, P type substrate and source electrode N
+Exist parasitic NPN type triode between the doped region, triode Q1 as shown in fig. 1; And P type substrate and the N of said NMOS pipe N1
+Exist the PN diode between the doped region, diode D1 as shown in fig. 1.
The operation principle of this esd protection circuit is: when being applied in the esd pulse of a forward in the drain electrode of said NMOS pipe N1; Its drain voltage raises; Between drain electrode and substrate, avalanche breakdown takes place, a large amount of holes pour into substrate from drain electrode, make underlayer voltage raise; When the voltage of substrate is enough big, make the base stage positively biased of parasitic NPN type triode Q1, thereby make parasitic NPN type triode Q1 open, so by said parasitic NPN type triode Q1 with the ESD current drain.Otherwise, when being applied in the esd pulse of a negative sense in the drain electrode of said NMOS pipe N1, said PN diode D1 conducting, thereby with the ESD current drain.
Fig. 2 shows the sketch map of the esd protection circuit of GCNMOS structure in the prior art.With reference to figure 2, the esd protection circuit of said GGNMOS (GateCoupled NMOS, gate coupled NMOS) structure comprises NMOS pipe N2, resistance R 1 and capacitor C 1.
The grid of said NMOS pipe N2 connects an end of capacitor C 1 and an end of resistance R 1, source electrode and substrate ground connection GND, and drain electrode connects the PAD pad; The other end of said capacitor C 1 connects the PAD pad; The other end ground connection GND of said resistance R 1.
The operation principle of this esd protection circuit is: in the esd event process, zooming voltage is coupled to energy on the capacitor C 1, thereby opens NMOS pipe N2, and then manages N2 with the ESD current drain by said NMOS.
Device in the esd protection circuit illustrated in figures 1 and 2 all adopts traditional cmos process to form; Usually only allow the withstand voltage of PAD pad end input can not surpass 20% of process voltage; When input voltage surpass process voltage 20% after; The ESD device itself is easy to burnt, thereby causes chip failure.
Can adopt high-pressure process or BCD technology to realize the high pressure resistant of device in the prior art.Normally, BCD technology can be passed through LDMOS (Lateral double-diffused metal-oxide semiconductor, lateral double diffusion metal oxide semiconductor) and realizes high pressure resistant and the ESD electric current of releasing.Yet with respect to common process, the complicacy on the processing procedure causes the cost of BCD technology very high; And the voltage endurance capability of withstand voltage ESD device is limited under the equal area, and for example under same area, HBM (Human Body Model, manikin) pattern can only reach 2000V～3000V.
A kind of mode of solution is to utilize the range upon range of metal-oxide-semiconductor of common process to realize that Fig. 3 promptly shows the sketch map of the esd protection circuit of range upon range of metal-oxide-semiconductor in the prior art in addition.With reference to figure 3, said esd protection circuit comprises NMOS pipe M1 and NMOS pipe M2.The grid of said NMOS pipe M1 connects bias voltage Vbias, and drain electrode connects the PAD pad, and source electrode connects the drain electrode of NMOS pipe M2; Grid and the source grounding GND of said NMOS pipe M2.
The mode of the range upon range of metal-oxide-semiconductor of employing common process can solve the problem of withstand voltage of ESD device, but because the ESD electric current is to discharge through parasitic NPN triode (parasitic NPN triode Q2 as shown in Figure 3), it has had a strong impact on the ability of maximum electrostatic discharge.
Therefore, the withstand voltage but also its that how not only improve the ESD circuit improve the ESD performance just becomes one of those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves provides a kind of electrostatic discharge circuit, when improving the circuit withstand voltage, has also improved its electrostatic discharge performance.
For addressing the above problem, the present invention provides a kind of electrostatic discharge circuit, comprising: bleeder circuit, NMOS pipe and the 2nd NMOS pipe;
The electrode input end of said bleeder circuit connects high voltage input terminal, and negative input is coupled to ground, and output connects the grid of said NMOS pipe, is used to export the bias voltage of conducting the one NMOS pipe;
The drain electrode of said NMOS pipe connects high voltage input terminal, and source electrode connects the drain electrode of said the 2nd NMOS pipe; The source ground of said the 2nd NMOS pipe, grid is coupled to ground.
Alternatively, said bleeder circuit comprises first capacitor element and second capacitor element, and an end of said first capacitor element connects high voltage input terminal, and the other end connects an end of second capacitor element, and as the output of said bleeder circuit; The other end of said second capacitor element is coupled to ground.
Alternatively, said first capacitor element comprises PMOS pipe, and said second capacitor element comprises the 2nd PMOS pipe, and the grid of said PMOS pipe connects high voltage input terminal, source electrode and the grid that drains and link to each other and all be connected the 2nd PMOS pipe; The source electrode of said the 2nd PMOS pipe links to each other with drain electrode and all is coupled to ground, and grid is as the output of said bleeder circuit.
Alternatively, the ratio of the capacitance of the capacitance of said first capacitor element and second capacitor element is in 1: 1～2: 1 scope.
Alternatively, said electrostatic discharge circuit also comprises first impedance component, and said first an impedor end connects the negative input of said bleeder circuit and the grid of the 2nd NMOS pipe, other end ground connection.
Alternatively, said first impedance component comprises first resistance.
Alternatively, said bleeder circuit comprises second impedance component and the 3rd impedance component, and the said second impedor end connects high voltage input terminal, and the other end connects the 3rd an impedor end and as the output of said bleeder circuit; The said the 3rd impedor other end is coupled to ground.
Alternatively, said second impedance component is second resistance; Said the 3rd impedance component is the 3rd resistance.
Compared with prior art, the present invention has the following advantages at least:
1) electrostatic discharge circuit of the present invention, bleeder circuit is coupled between high voltage input terminal and the ground, is used for the voltage dividing potential drop, and its output is that a NMOS tube grid provides suitable bias voltage; Said NMOS pipe and the conducting simultaneously in the esd event process of the 2nd NMOS pipe form leakage path.In this electrostatic discharge circuit, the ESD electric current is released through NMOS pipe and the 2nd NMOS pipe, and its ESD performance is superior to passing through in the prior art performance of parasitic NPN triode greatly.
On the other hand; After the voltage process bleeder circuit dividing potential drop of said high voltage input terminal; Make voltage difference and the voltage difference between the grid leak between the grid source of voltage difference and the voltage difference between the grid leak between the grid source of the NMOS pipe of winning, the 2nd NMOS pipe all less than the maximum withstand voltage of technology, thereby improved the maximum withstand voltage of this circuit.
2) in the possibility, said bleeder circuit comprises first capacitor element and second capacitor element, adopts capacitor element to carry out dividing potential drop and can avoid having leakage current in this electrostatic discharge circuit, thereby reduced the power consumption of this circuit.
3) in the possibility, said electrostatic discharge circuit also comprises first resistance, and an end of said first resistance connects the negative input of said bleeder circuit and the grid of the 2nd NMOS pipe, other end ground connection.In the esd event process, this first resistance can be so that the grid voltage of the 2nd NMOS pipe be raise fast, and said the 2nd NMOS pipe ON time is shortened, thereby has improved the ESD performance of this circuit further.
4) in the possibility, the ratio of the capacitance of the capacitance of said first capacitor element and second capacitor element is in 1: 1～2: 1 scope.Can improve the withstand voltage of this circuit to greatest extent through the capacitance that first capacitor element and second capacitor element suitably are set.
Description of drawings
Fig. 1 is the sketch map of the esd protection circuit of GGNMOS structure in the prior art;
Fig. 2 is the sketch map of the esd protection circuit of GCNMOS structure in the prior art;
Fig. 3 is the sketch map of the esd protection circuit of range upon range of metal-oxide-semiconductor in the prior art;
Fig. 4 is the structural representation of a kind of embodiment of electrostatic discharge circuit of the present invention;
Fig. 5 is the structural representation of a kind of embodiment of bleeder circuit among Fig. 4;
Fig. 6 is the equivalent circuit diagram of circuit shown in Figure 5.
Embodiment
Described in background technology; The high pressure resistant lifting of the device that available technology adopting high-pressure process or BCD technology form is limited; Though and the esd protection circuit of the range upon range of metal-oxide-semiconductor of employing common process has solved high pressure resistant problem; But it mainly discharges the ESD electric current through the parasitic NPN triode, thereby has had a strong impact on the ability of its static discharge.
Electrostatic discharge circuit of the present invention comprises bleeder circuit, NMOS pipe and the 2nd NMOS pipe, and said bleeder circuit is used for suitable bias voltage to NMOS pipe being provided, thereby makes the NMOS pipe of winning be in conducting state; The 2nd NMOS pipe also can be by quick unlatching in the esd event process, forms path with ESD electric current rapid release thereby managed with the 2nd NMOS by said NMOS pipe.At this circuit, the ESD electric current discharges through NMOS pipe and the 2nd NMOS pipe, and with the delivery mode of ESD electric current in the prior art through the parasitic NPN triode, the ESD performance of this circuit promotes greatly.
On the other hand, carry out after the dividing potential drop through bleeder circuit, the gate source voltage difference and the drain-to-gate voltage difference of said NMOS pipe and the 2nd NMOS pipe are all withstand voltage less than the technology maximum, thereby have guaranteed the withstand voltage properties of this circuit.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed embodiment.
Fig. 4 shows the structural representation of a kind of embodiment of electrostatic discharge circuit of the present invention, and with reference to figure 4, said electrostatic discharge circuit comprises: bleeder circuit 10, NMOS pipe M11 and the 2nd NMOS pipe M12.
The electrode input end of said bleeder circuit 10 connects high voltage input terminal, and negative input is coupled to ground GND, and output connects the grid of said NMOS pipe M11, is used to export the bias voltage of conducting the one NMOS pipe M11;
The drain electrode of said NMOS pipe M11 connects high voltage input terminal, and source electrode connects the drain electrode of said the 2nd NMOS pipe M12;
The source ground GND of said the 2nd NMOS pipe M12, grid is coupled to ground GND.
In the present embodiment, the grid of the output of said bleeder circuit 10 and the 2nd NMOS pipe M12 all couples with ground GND through first resistance R 11.Certainly in other embodiments, also can adopt other impedance component to realize that output, the 2nd NMOS of said bleeder circuit 10 manage the grid of M12 and coupling of ground GND.For example, can adopt the connected mode of resistance to replace first resistance R 11 in the present embodiment metal-oxide-semiconductor.The resistance connected mode of metal-oxide-semiconductor is well known to those skilled in the art, so repeat no more at this.
Need to prove that in other embodiments, said electrostatic discharge circuit also can not comprise said first resistance or other impedance component, it does not influence protection scope of the present invention.
In the present invention, said bleeder circuit 10 can adopt multiple circuit structure to realize, for example can be connected by resistive element and realize, also can be connected by capacitor element and realize.The structure of said bleeder circuit 10 does not limit protection scope of the present invention.
In one embodiment, said bleeder circuit 10 can comprise second impedance component and the 3rd impedance component, and the said second impedor end connects high voltage input terminal, and the other end connects the 3rd an impedor end and as the output of said bleeder circuit; The said the 3rd impedor other end is coupled to ground.
Need to prove that said second impedance component can also be substituted by MOS resistance for being common resistance device (as: second resistance); Likewise, said the 3rd impedance component can be common resistance device (as: the 3rd resistance), can also be substituted by MOS resistance.
Preferably; In the present embodiment, said bleeder circuit 10 can comprise first capacitor element and second capacitor element, and an end of said first capacitor element connects high voltage input terminal; The other end connects an end of second capacitor element, and as the output of said bleeder circuit 10; The other end of said second capacitor element is coupled to ground through said first resistance R 11.
When adopting capacity cell to carry out dividing potential drop, can in circuit, not produce leakage current, thereby can reduce the power consumption of circuit.
In addition, the inventor finds, the capacitance through said first capacitor element suitably is set and the capacitance of second capacitor element can improve the withstand voltage of electrostatic discharge circuit effectively.Particularly, in the present embodiment, the ratio of the capacitance of the capacitance of said first capacitor element and second capacitor element is in 1: 1～2: 1 scope.
Said first capacitor element and second capacitor element can be capacitor of the prior art, also can adopt mos capacitance to realize.The type of said first capacitor element and second capacitor element does not influence protection scope of the present invention.
Fig. 5 shows the structural representation of a kind of embodiment of bleeder circuit of the present invention, and is as shown in Figure 5, and said bleeder circuit 10 comprises PMOS pipe M13 and the 2nd PMOS pipe M14.
The grid of said PMOS pipe M13 connects high voltage input terminal, and source electrode links to each other with drain electrode and all is connected the grid that the 2nd PMOS manages M14; Said PMOS pipe M13 forms first capacitor element.
The source electrode of said the 2nd PMOS pipe M14 links to each other with drain electrode and all is coupled to ground GND, and grid is as the output of said bleeder circuit; Said PMOS pipe M14 forms second capacitor element.
In the present embodiment, the source electrode of said the 2nd PMOS pipe M14 is coupled to ground GND with drain electrode through first resistance R 11.
Fig. 6 is the equivalent circuit diagram of circuit shown in Figure 5.Below in conjunction with Fig. 6 the operation principle of electrostatic discharge circuit of the present invention is elaborated.
For convenience of description, the magnitude of voltage of supposing high voltage input terminal is VIN; The capacitance of supposing first capacitor element is C3, and the capacitance of second capacitor element is C4, and C3 equals C4.
With reference to figure 6; The voltage VIN that first electric capacity and second electric capacity are connected to high voltage input terminal carries out dividing potential drop, voltage after partial value
When C3=C4, voltage after partial value
the i.e. grid voltage Vg of NMOS pipe M11 is
For the MOS device that adopts common process to form, the voltage difference of its maximum withstand voltage voltage difference (Vgs) that will guarantee its grid and source electrode and grid and drain electrode (Vgd) is all withstand voltage less than the technology maximum.For example, technology is maximum withstand voltage when be 5V, manages M11 for a NMOS, and the voltage difference of voltage difference of its grid and source electrode (Vg1s1) and grid and drain electrode (Vg1d1) all should be less than 5V.For the 2nd NMOS pipe M12, the voltage difference (Vg2d2) of the voltage difference of its grid and source electrode (Vg2s2) and grid and drain electrode also all should be less than 5V.
For nmos device,, must guarantee that its grid voltage (Vg) is greater than source voltage (Vs) if there is electric current to flow through.
So in the present embodiment, for NMOS pipe M11,
And
The actual voltage that bears of said NMOS pipe M11 institute is less than or equal to half of high voltage input terminal voltage; In other words; The voltage that said NMOS pipe M11 can bear can promote 2 times into former high voltage input terminal voltage, and promptly said NMOS pipe M11 can tolerate the process voltage of twice.
For the 2nd NMOS pipe M12; The actual voltage that bears of said the 2nd NMOS of
pipe M12 institute is half the less than high voltage input terminal voltage, and said the 2nd NMOS manages the process voltage that M12 can tolerate twice equally.
Can know that by above analysis in the electrostatic discharge circuit of the present invention, said NMOS pipe M11 and the 2nd NMOS pipe M12 can tolerate the process voltage of twice, thereby have promoted the withstand voltage properties of circuit greatly.
Need to prove; Above data are merely and illustrate; In other embodiments; Can also the capacitance C4 of the capacitance C3 of first capacitor element and second capacitor element be done other setting, for example the ratio of C3 and C4 is 1.5: 1 or 2: 1 or the like, and it should not limit protection scope of the present invention.Can make circuit of the present invention bear different processes voltage through suitable setting to C3 and C4 ratio.
In addition, can also realize different voltage after partial value V1, and then can adjust the operating state of the 2nd NMOS pipe M12 flexibly, improve its electrostatic discharge capacity through suitable setting to C3 and C4 ratio.
Continuation is with reference to figure 6, and when esd event arrived, the voltage VIN of high voltage input terminal can moment rising Δ V.The grid voltage Vg2 of said the 2nd NMOS pipe M12 is by lifting rapidly, and satisfies formula Vg2=[1-e (t/RC)] * Δ V.R in this formula refers to the resistance of first resistance R 11; C refers to the capacitance sum of the first capacitor element M13 and the second capacitor element M14.In other words; The said first capacitor element M13, the second capacitor element M14 and first resistance R 11 are when the voltage VIN of high voltage input terminal moment rising Δ V; Form an integrating circuit, thereby make the grid voltage of the 2nd NMOS pipe M12 satisfy formula Vg2=[1-e (t/RC)] * Δ V.After the difference (Vg2s2) of its grid voltage Vg2 and its source electrode Vs2 is greater than threshold voltage, said the 2nd NMOS pipe M12 conducting.
For NMOS pipe M11; Because the pressure reduction at electric capacity two ends can not suddenly change; According to the dividing potential drop relation of capacitor C 3, C4, the grid voltage Vg1 of said NMOS pipe M11 is approximately
thereby guarantees NMOS pipe M11 conducting again.
This moment the one NMOS pipe M11 and equal conducting of the 2nd NMOS pipe M12, thus make the ESD energy to be discharged into ground GND through these two metal-oxide-semiconductors rapidly.Because the conducting of NMOS pipe M11 and the 2nd NMOS pipe M12; ESD releases very rapidly; Thereby make inside circuit high pressure can not occur; Therefore, electrostatic discharge circuit of the present invention can very fall the ESD current drain effectively, and its performance is superior to relying in the prior art circuit performance of parasitic NPN triode.
Need to prove; In the present embodiment, the effect of said first resistance R 11 is when esd event arrives, and raises the grid voltage of the 2nd NMOS pipe M12 fast; Thereby make said the 2nd NMOS pipe M12 by conducting rapidly, further improved the ESD performance of circuit.
Certainly; In other embodiments, said electrostatic discharge circuit also can not comprise said first resistance R 11, only relies on the dead resistance among NMOS pipe M11 and the 2nd NMOS pipe M12 to come conducting the 2nd NMOS pipe; At this moment, the conducting speed of said the 2nd NMOS pipe is slightly slow.But it should not limit protection scope of the present invention.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (8)
1. an electrostatic discharge circuit is characterized in that, comprising: bleeder circuit, NMOS pipe and the 2nd NMOS pipe;
The electrode input end of said bleeder circuit connects high voltage input terminal, and negative input is coupled to ground, and output connects the grid of said NMOS pipe, is used to export the bias voltage of conducting the one NMOS pipe;
The drain electrode of said NMOS pipe connects high voltage input terminal, and source electrode connects the drain electrode of said the 2nd NMOS pipe; The source ground of said the 2nd NMOS pipe, grid is coupled to ground.
2. electrostatic discharge circuit as claimed in claim 1; It is characterized in that; Said bleeder circuit comprises first capacitor element and second capacitor element; One end of said first capacitor element connects high voltage input terminal, and the other end connects an end of second capacitor element, and as the output of said bleeder circuit; The other end of said second capacitor element is coupled to ground.
3. electrostatic discharge circuit as claimed in claim 2; It is characterized in that; Said first capacitor element comprises PMOS pipe; Said second capacitor element comprises the 2nd PMOS pipe, and the grid of said PMOS pipe connects high voltage input terminal, source electrode and the grid that drains and link to each other and all be connected the 2nd PMOS pipe; The source electrode of said the 2nd PMOS pipe links to each other with drain electrode and all is coupled to ground, and grid is as the output of said bleeder circuit.
4. electrostatic discharge circuit as claimed in claim 2 is characterized in that, the ratio of the capacitance of the capacitance of said first capacitor element and second capacitor element is in 1: 1～2: 1 scope.
5. electrostatic discharge circuit as claimed in claim 1 is characterized in that said electrostatic discharge circuit also comprises first impedance component, and said first an impedor end connects the negative input of said bleeder circuit and the grid of the 2nd NMOS pipe, other end ground connection.
6. electrostatic discharge circuit as claimed in claim 5 is characterized in that, said first impedance component comprises first resistance.
7. electrostatic discharge circuit as claimed in claim 1; It is characterized in that; Said bleeder circuit comprises second impedance component and the 3rd impedance component, and the said second impedor end connects high voltage input terminal, and the other end connects the 3rd an impedor end and as the output of said bleeder circuit; The said the 3rd impedor other end is coupled to ground.
8. electrostatic discharge circuit as claimed in claim 7 is characterized in that, said second impedance component is second resistance; Said the 3rd impedance component is the 3rd resistance.
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| CN2012100750136A CN102611093A (en) | 2012-03-20 | 2012-03-20 | Static discharging circuit |
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| CN2012100750136A CN102611093A (en) | 2012-03-20 | 2012-03-20 | Static discharging circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106292823A (en) * | 2016-08-31 | 2017-01-04 | 苏州纳芯微电子股份有限公司 | A kind of high-low pressure converts integrated circuit |
| CN106356823A (en) * | 2016-09-18 | 2017-01-25 | 无锡力芯微电子股份有限公司 | Surge protection circuit integrated in chip |
| CN108321781A (en) * | 2018-04-17 | 2018-07-24 | 江苏卓胜微电子股份有限公司 | A kind of esd protection circuit and the integration module based on GaAs PHEMT techniques |
| CN109449156A (en) * | 2018-12-20 | 2019-03-08 | 上海艾为电子技术股份有限公司 | A kind of port static release protection circuit |
| US20190165572A1 (en) * | 2017-11-24 | 2019-05-30 | Ememory Technology Inc. | Electrostatic discharge protection circuit with a high turn-on speed |
| CN117748432A (en) * | 2023-12-25 | 2024-03-22 | 河北美泰电子科技有限公司 | Protection circuit of ASIC chip of automobile micro-electromechanical system and micro-electromechanical system |
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| US6556398B1 (en) * | 1999-10-05 | 2003-04-29 | Winbond Electronics Corporation | Voltage tolerance ESD protection circuit |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106292823A (en) * | 2016-08-31 | 2017-01-04 | 苏州纳芯微电子股份有限公司 | A kind of high-low pressure converts integrated circuit |
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| CN106356823A (en) * | 2016-09-18 | 2017-01-25 | 无锡力芯微电子股份有限公司 | Surge protection circuit integrated in chip |
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| US20190165572A1 (en) * | 2017-11-24 | 2019-05-30 | Ememory Technology Inc. | Electrostatic discharge protection circuit with a high turn-on speed |
| CN109842103A (en) * | 2017-11-24 | 2019-06-04 | 力旺电子股份有限公司 | ESD protection circuit |
| CN108321781A (en) * | 2018-04-17 | 2018-07-24 | 江苏卓胜微电子股份有限公司 | A kind of esd protection circuit and the integration module based on GaAs PHEMT techniques |
| CN109449156A (en) * | 2018-12-20 | 2019-03-08 | 上海艾为电子技术股份有限公司 | A kind of port static release protection circuit |
| CN109449156B (en) * | 2018-12-20 | 2024-03-22 | 上海艾为电子技术股份有限公司 | Port electrostatic discharge protection circuit |
| CN117748432A (en) * | 2023-12-25 | 2024-03-22 | 河北美泰电子科技有限公司 | Protection circuit of ASIC chip of automobile micro-electromechanical system and micro-electromechanical system |
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