CN102148499A - CDM (Charged Device Model) ESD (Electro-Static Discharge) protection circuit - Google Patents
CDM (Charged Device Model) ESD (Electro-Static Discharge) protection circuit Download PDFInfo
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Abstract
The invention provides a CDM (Charged Device Model) ESD (Electro-Static Discharge) protection circuit which is used for protecting a functional unit. The CDM ESD protection circuit comprises a first stage of ESD protection unit, a low voltage trigger protection unit, a second stage of ESD protection unit and a local ESD protection unit, wherein the first end of the low voltage trigger protection unit is coupled to the input/output pin, and the second end of the low voltage trigger protection unit is coupled to the substrate. When the electric potential of the substrate is smaller than that of the input/output pin and exceeds a second specific voltage, the low voltage trigger protection unit operates. Therefore, the performance of the CDM ESD protection circuit is improved.
Description
Technical field
The present invention relates to the Electrostatic Discharge circuit, particularly a kind of CDM esd protection circuit.
Background technology
Integrated circuit (IC) make, assembling and test or in final application, be easy to be subjected to make or use in destructive Electrostatic Discharge, thereby make integrated circuit be subjected to the damage of static.
ESD is usually by high-voltage potential (for example several kilovolts) discharge generation, and causes the pulse of short duration (for example 100ns) high electric current.ESD is divided three classes usually, and the first kind is that the ESD of common corresponding the type can make the esd protection circuit of HBM (human body model) type because the people contacts generation with IC; Second class is owing to plant equipment produces with contacting of IC, and the ESD of common corresponding the type can make the esd protection circuit of MM (machine model) type; The 3rd class is owing to the charged of IC self produces, and its discharge can take place by the single pin of IC, and the esd protection circuit that such ESD can make CDM (charged-device-model) type carries out discharge prevention.
The esd protection circuit of the first kind and second type realizes by the discharge circuit that couples with IC I/O pin usually, thereby the static on the IC I/O pin is discharged, and reduces the damage of IC static to the functional unit of inside.
And for the 3rd type ESD, electric charge accumulates in the substrate usually, so the CDM esd protection circuit need discharge electric charge in substrate.In order to protect IC to avoid the damage of CDM ESD; in the prior art; usually will between substrate and the I/O pin discharge channel be set; this discharge channel is not worked in the IC normal work period, promptly shows low the leakage, i.e. high resistivity; during esd discharge, work; promptly show low-resistivity, form discharge path, thereby the electric charge in the substrate is discharged.Fig. 1 is the schematic diagram of a kind of existing C DM esd protection circuit and protected function unit; Fig. 2 is the generalized section of circuit shown in Figure 1; as depicted in figs. 1 and 2; existing CDM esd protection circuit is to realize by esd protection unit 101 (for example can be MOS transistor); but along with reducing of process; the grid oxygen of the MOS transistor of functional unit is more and more thinner; although for defencive function unit 102; for substrate is provided with discharge channel; but because the voltage of ESD is too high; time is too short, that the grid oxygen of the MOS transistor of functional unit 102 is very easy to is breakdown (the discharging current I shown in Fig. 2 for example
ESD), thereby make functional unit be damaged.
In order to seek better solution, the patent No. is that the american documentation literature of US6885529B2 discloses a kind of CDM ESD structure of using deep trap structure to solve the CDM threat, functional unit is positioned at isolates among the N trap, thereby significantly reduce the electrostatic charge in the residing P well region of functional unit, although but the quantity of electric charge reduces, still can puncture the grid oxide layer of functional unit metal-oxide-semiconductor, it is destroyed.
Summary of the invention
The technical problem that the present invention solves provides a kind of CDM esd protection circuit, thereby has improved the performance of CDM esd protection circuit.
In order to address the above problem, the invention provides a kind of CDM esd protection circuit, comprise power line, substrate and I/O pin, be used for functional unit is protected; Functional unit couples by resistance and described I/O pin;
The CDM esd protection circuit also comprises:
First order esd protection unit, its first end is coupled to described I/O pin, and second end is coupled to power line, when the current potential of described power line during than high first specific voltage of the current potential of described I/O pin, then described first order esd protection cell operation;
Low-voltage trigger protection unit, its first end is coupled to described I/O pin, second end is coupled to described substrate, when the current potential of described substrate surpasses second specific voltage less than the current potential of described I/O pin, and then described low-voltage trigger protection cell operation;
Esd protection unit, the second level, its first end is coupled to described I/O pin by resistance, second end is coupled to described power line, the 3rd end is coupled to described substrate, when the current potential of described power line during than high the 3rd specific voltage of the current potential of described I/O pin, when perhaps the current potential of described substrate is than low the 4th specific voltage of the current potential of described I/O pin, then described second level esd protection cell operation;
The local ESD protected location; its first end is coupled to described I/O pin by described resistance; second end is coupled to described power line; the 3rd end is coupled to described substrate; when the current potential of described power line during than high the 5th specific voltage of the current potential of described I/O pin; when perhaps the current potential of described substrate is than low the 6th specific voltage of the current potential of described I/O pin, then described local ESD protected location work.
Preferably, described low-voltage trigger protection unit is when the high 0.7V of voltage of the described I/O pin of the voltage ratio of described substrate and work when above.
Preferably, described first order esd protection unit, low-voltage trigger protection unit, esd protection unit, the second level and/or local ESD protected location are clamp circuit.
Preferably, the threshold voltage of described low-voltage trigger protection unit is less than the MOS transistor grid oxide layer puncture voltage in the esd protection circuit.
Preferably, the threshold voltage of described low-voltage trigger protection unit is less than the threshold voltage of the MOS transistor of minimum feature size under the same technology characteristics size.
Preferably, described low-voltage trigger protection unit is SCR.
Preferably, described SCR is:
Electric capacity, its first end is coupled to described input and output pin, and second end is coupled to first node;
First resistance, its first end is coupled to described substrate, and second end is coupled to first node;
The PNP pipe, its emitter is coupled to described I/O pin, and base stage is coupled to described first node, and collector electrode is coupled to Section Point;
The NPN pipe, its emitter is coupled to described substrate, and collector electrode is coupled to the I/O pin by second resistance, and base stage is coupled to Section Point;
The 3rd resistance, its first end is coupled to described substrate, and second end is coupled to described Section Point.
Preferably, described SCR is:
Electric capacity, its first end is coupled to described substrate, and second end is coupled to first node;
First resistance, its first end is coupled to described I/O pin, and second end is coupled to first node;
Nmos pass transistor, its grid is coupled to first node, and source electrode is coupled to substrate;
The PNP pipe, its emitter is coupled to described I/O pin, and base stage is coupled to the drain electrode of described nmos pass transistor, and collector electrode is coupled to Section Point;
The NPN pipe, its emitter is coupled to described substrate, and collector electrode is coupled to the I/O pin by second resistance, and base stage is coupled to Section Point;
The 3rd resistance, its first end is coupled to described substrate, and second end is coupled to described Section Point.
Preferably, described SCR comprises: parasitic diode, its positive pole are coupled to described I/O pin, and negative pole is coupled to described substrate.
Preferably, described first order esd protection unit comprises:
The PMOS transistor, its grid couples described first order esd protection unit second end by resistance, and source electrode couples described electrion subelement second end, and drain electrode couples described first order esd protection unit first end.
Preferably, esd protection unit, the described second level comprises:
Electrion subelement, its first end couple esd protection unit, the described second level first end, and its second end couples esd protection unit, the described second level second end;
Low pressure discharge subelement, its first end couple esd protection unit, the described second level first end, and its second end couples esd protection unit, the described second level the 3rd end.
Preferably, described electrion subelement comprises:
The PMOS transistor, its grid is couple to described electrion subelement second end by resistance, and source electrode couples described electrion subelement second end, and drain electrode couples described electrion subelement first end.
Preferably, described low pressure discharge subelement comprises:
Nmos pass transistor, its grid is couple to described low pressure discharge subelement second end by resistance, and source electrode couples described low pressure discharge subelement second end, and drain electrode couples described low pressure discharge subelement first end.
Preferably, described local ESD protected location comprises:
Electrion subelement, its first end couple esd protection unit, the described second level first end, and its second end couples esd protection unit, the described second level second end;
Low pressure discharge subelement, its first end couple esd protection unit, the described second level first end, and its second end couples esd protection unit, the described second level the 3rd end.
Preferably, described electrion subelement comprises:
PMOS transistor, its grid are couple to described electrion subelement second end, and source electrode couples described electrion subelement second end, and drain electrode couples described electrion subelement first end.
Preferably, described low pressure discharge subelement comprises:
Nmos pass transistor, its grid are couple to described low pressure discharge subelement second end, and source electrode couples described low pressure discharge subelement second end, and drain electrode couples described low pressure discharge subelement first end.
Preferably, described substrate is the P type, and described local ESD protected location is positioned at the N trap.
Compared with prior art, the present invention mainly has the following advantages:
The present invention is by being provided with first order esd protection unit in the CDM esd protection circuit; low-voltage trigger protection unit; esd protection unit, the second level and local esd protection unit be the level Four discharge circuit altogether; thereby make under the situation of IC I/O pin ground connection; because the existence of electric charge makes and has potential difference between substrate and the IC I/O pin in the substrate; thereby the cell operation of above-mentioned protection; promptly show as low-resistivity; the level Four discharge channel that passes through that electric charge in the substrate can be very fast discharges like this; avoided because static makes that the MOS transistor grid oxide layer in the functional unit is breakdown; and the problem that the functional unit that causes lost efficacy; therefore CDM ESD circuit of the present invention is more stable, and performance is better.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 to Fig. 2 is existing a kind of CDM esd protection circuit and protected function cell schematics;
Fig. 3 to Fig. 5 is the CDM esd protection circuit and the protected function cell schematics of the embodiment of the invention;
Fig. 6 is the CDM esd protection circuit and the protected function cell schematics of another embodiment of the present invention.
Embodiment
By background technology as can be known; conventional semiconductor technology is along with process reduces; the grid oxide layer of the MOS transistor of functional unit is more and more thinner; although be that substrate is provided with discharge channel therefore for the defencive function unit; but because the voltage of ESD is too high; time is too short, so the grid oxide layer of the MOS transistor of functional unit is very easy breakdown, thereby makes functional unit be damaged.Although there are some new technical schemes to solve the CDM ESD structure that CDM threatens by using deep trap structure, functional unit is positioned at isolates among the N trap, thereby significantly reduce the electrostatic charge in the P trap at functional unit place, although but the quantity of electric charge reduces, still can puncture the grid oxide layer of functional unit metal-oxide-semiconductor, it is destroyed.
And the present invention is by being provided with first order esd protection unit in the CDM esd protection circuit; low-voltage trigger protection unit; esd protection unit, the second level and local esd protection unit be the level Four discharge circuit altogether; thereby make under the situation of IC I/O pin ground connection; because the existence of electric charge makes and has potential difference between substrate and the IC I/O pin in the substrate; thereby the cell operation of above-mentioned protection; promptly show as low-resistivity; the level Four discharge channel that passes through that electric charge in the substrate can be very fast discharges like this; avoided because static makes that the MOS transistor grid oxide layer in the functional unit is breakdown; and the problem that the functional unit that causes lost efficacy; therefore CDM ESD circuit of the present invention is more stable, and performance is better.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
First embodiment
Fig. 3 is the CDM esd protection circuit and the protected function cell schematics of the embodiment of the invention.Below in conjunction with Fig. 3 the CDM esd protection circuit of the embodiment of the invention is described, Fig. 3 mainly comprises: power line 103 (input voltage is VDD), substrate S ub and I/O pin (I/Opad) 105, functional unit 110, first order esd protection unit 120, low-voltage trigger protection unit 130, esd protection unit, the second level 140 and local esd protection unit 150.
Wherein, functional unit 110 couples by resistance R 0 with described I/O pin (I/Opad) 105, and described functional unit 110 is the core cell of CDM esd protection circuit, is used to realize the function of circuit.
First order esd protection unit 120 first ends are coupled to described I/O pin 105; second end is coupled to power line 103; when the current potential of described power line 103 during than high first specific voltage of the current potential of described I/O pin I/Opad, 120 work (promptly showing as low-resistivity) of then described first order esd protection unit.Power line 103 can be coupled the N trap in the functional unit 110 in use; thereby the positive charge that accumulates in the N trap acquires a certain degree; for example I/O pin 105 ground connection the time; current potential is 0V; when the N trap potential is higher than 0V first specific voltage; then first order esd protection unit 120 work discharge the electric charge in the N trap.For example first order esd protection unit 120 can be clamp circuit.Wherein first specific voltage can be provided with according to the requirement of product to static, for example can be set to 10V, 20V...
Low-voltage trigger protection unit 130; its first end is coupled to described I/O pin 105; second end is coupled to described substrate S ub, when the current potential of described substrate S ub during than low second specific voltage of the current potential of described I/O pin 105, and 130 work of then described low-voltage trigger protection unit.The negative electrical charge that accumulates in the P type substrate acquires a certain degree in use; for example I/O pin 105 ground connection the time; current potential is 0V; when the current potential of described substrate S ub during than low second specific voltage of 0V voltage; then low-voltage trigger protection unit 130 work discharge the electric charge in the P type substrate by I/O pin 105.For example low-voltage trigger protection unit 130 can be clamp circuit.For example all right, described low-voltage trigger protection unit 130 when the current potential of described substrate S ub than the high 0.7V of current potential of described I/O pin I/Opad and conducting when above, can in time the positive charge in the substrate be discharged like this.Preferably, the threshold voltage (minimum voltage of promptly starting working) of described low-voltage trigger protection unit 130 can be protected the MOS transistor in the esd protection circuit like this less than the MOS transistor grid oxide layer puncture voltage in the esd protection circuit.Wherein second specific voltage can be provided with according to the requirement of product to static, for example can be set to 6V, 7V...
Esd protection unit, the second level 140; its first end is coupled to described I/O pin 105 by resistance R 0; second end is coupled to described power line 103; the 3rd end is coupled to described substrate S ub; when the current potential of described power line 103 during than high the 3rd specific voltage of the current potential of described I/O pin 105; when perhaps the current potential of described substrate S ub was than low the 4th specific voltage of the current potential of described I/O pin 105, esd protection unit, the then described second level 140 is group altogether.Power line 103 can be coupled to the N trap in the functional unit 110 in use, thereby the positive charge that accumulates in the N trap acquires a certain degree, when for example current potential was higher than 0V current potential the 3rd specific voltage, then second level esd protection unit 140 work discharged the electric charge in the N trap; Or the negative electrical charge that accumulates in substrate acquires a certain degree; for example I/O pin 105 ground connection the time; current potential is 0V; when the current potential of described substrate S ub during than low the 4th specific voltage of 0V voltage; then second level esd protection unit 140 work, for example second level esd protection unit 140 can be clamp circuit.Wherein the 3rd specific voltage and the 4th specific voltage can be provided with according to the requirement of product to static, for example can be set to 10V, 20V...
Local ESD protected location 150; its first end is coupled to described I/O pin 105 by resistance R 0; second end is coupled to described power line 103; the 3rd end is coupled to described substrate S ub; when the current potential of described power line 103 during than high the 5th specific voltage of the current potential of described I/O pin 105; when perhaps the current potential of described substrate S ub is than low the 6th specific voltage of the current potential of described I/O pin 105,150 work of esd protection unit, the then described second level.Power line 103 can be coupled the N trap in the functional unit 110 in use, thereby the positive charge that accumulates in the N trap acquires a certain degree, when for example current potential was higher than 0V current potential the 5th specific voltage, then local ESD protected location 150 work discharged the electric charge in the N trap; Or the negative electrical charge that accumulates in substrate acquires a certain degree; for example current potential is 0V I/O pin 105 ground connection the time; when the current potential of described substrate S ub during than low the 6th specific voltage of 0V voltage; then local ESD protected location 150 work, for example local ESD protected location 150 can be clamp circuit.Wherein the 5th specific voltage and the 6th specific voltage can be provided with according to the requirement of product to static, for example can be set to 10V, 20V...
Fig. 4 is CDM esd protection circuit of the present invention and protected function cell schematics; with reference to figure 4; in a specific implementation; described first order esd protection unit 120 can comprise: PMOS transistor M0; its grid couples described first order esd protection unit second end (being power line 103) by resistance R 10; source electrode couples described first order esd protection unit second end (being power line 103), and drain electrode couples described first order esd protection unit first end (being I/O pin 105).Wherein, the requirement that those skilled in the art can make the requirement of static and circuit design and technology according to product is provided with according to the parameter of conventional method pair pmos transistor M0 and resistance R 10.
With reference to figure 4, in a specific implementation, described low-voltage trigger protection unit is SCR.Described SCR is: capacitor C 1, its first end couple described input and output pin 105, the second ends and couple first node 10; First resistance R 1, its first end is coupled to described substrate, and second end couples first node 10; PNP manages P1, and its emitter is coupled to described I/O pin 105, and base stage is coupled to described first node 10, and collector electrode is coupled to Section Point 20; NPN manages N1, and its emitter is coupled to described substrate S ub, and collector electrode is coupled to I/O pin 105 by second resistance R 3, and base stage is coupled to Section Point 20; The 3rd resistance R 3, its first end is coupled to described substrate S ub, and second end is coupled to described Section Point 20.The threshold voltage of above-mentioned low-voltage trigger protection unit 130 is less than the threshold voltage of the MOS transistor of minimum dimension under the same technology characteristics size; for example under 0.18um technology; the resistance that can be by regulating first resistance R 1 and the electric capacity of capacitor C 1, make when the current potential of substrate S ub during than low second specific voltage (second specific voltage is the threshold voltage of the MOS transistor of 0.18um less than characteristic size) of the current potential of described I/O pin 105 then low-voltage trigger protection unit 130 work.
For example; the resistance of first resistance R 1 is 18k to 22k ohm; when electric capacity is 0.8pf to 1.2pf; 0.18um CMOS technology for standard; employing standard operation voltage is that the device of 3.3V constitutes described CDM esd protection circuit; when I/O pin 105 ground connection, then the voltage of described substrate S ub reach-4V to-when 6V is following (second specific voltage is 4V to 6V), then work in low-voltage trigger protection unit 130.If having accumulated negative electrical charge in the substrate reached-during 4V, current potential is 0V when I/O pin 105 ground connection, it (is first node 10 that capacitor C 1 begins charging, the base stage of PNP pipe P1 begins charging), then PNP pipe P1 opens when charging reaches the threshold voltage of PNP pipe P1, the current potential of Section Point 20 raises, when the emitter potential difference of the current potential of Section Point 20 and NPN pipe N1 reaches the threshold voltage of NPN pipe N1, then NPN pipe N1 opens, thereby between substrate and I/O pin 105, formed two discharge channels, can effectively the negative electrical charge in the substrate have been discharged.
The work trigger voltage of common esd protection circuit is all greater than 6V in the prior art; just, substrate reaches-could trigger esd protection circuit when 6V is following when accumulating negative electrical charge; the present invention utilizes the SCR circuit to reduce the trigger voltage of esd protection circuit, thereby has increased the protection to functional unit.
In the present embodiment, described SCR comprises: parasitic diode, its positive pole couple described I/O pin 105, and negative pole couples described substrate S ub.This parasitic diode is inoperative when substrate stored negative electrical charge, and this parasitic diode forward conduction discharges positive charge when substrate stored positive charge.
With reference to figure 4, in a specific implementation, esd protection unit, the described second level can comprise:
Electrion subelement 140a, its first end couple esd protection unit, the described second level first end 1401, and its second end couples esd protection unit, the described second level second end 1402; Low pressure discharge subelement 140b, its first end couple esd protection unit, the described second level first end 1401, and its second end couples esd protection unit, the described second level the 3rd end 1403.
With reference to figure 4, in a specific implementation, described electrion subelement can comprise:
PMOS transistor M1, its grid couples described electrion subelement second end (being power line 103) by resistance R 11, source electrode couples described electrion subelement second end (being power line 103), and drain electrode couples described electrion subelement first end (promptly coupling I/O pin 105 by resistance R 0).Wherein, the requirement that those skilled in the art can make the requirement of static and circuit design and technology according to product is provided with according to the parameter of conventional method pair pmos transistor M1 and resistance R 11.
With reference to figure 4, in a specific implementation, described low pressure discharge subelement can comprise:
Nmos pass transistor M2, its grid is couple to described low pressure discharge subelement second end (being substrate S ub) by resistance R 12, source electrode couples described low pressure discharge subelement second end (being substrate S ub), and drain electrode couples described low pressure discharge subelement first end (promptly coupling I/O pin 105 by resistance R 0).Wherein, the requirement that those skilled in the art can make the requirement of static and circuit design and technology according to product is provided with according to the parameter of conventional method pair nmos transistor M2 and resistance R 12.
With reference to figure 4, in the present embodiment, described local ESD protected location comprises: electrion subelement, its first end couple esd protection unit, the described second level first end, and its second end couples esd protection unit, the described second level second end; Low pressure discharge subelement, its first end couple esd protection unit, the described second level first end, and its second end couples esd protection unit, the described second level the 3rd end.。
In the present embodiment, described electrion subelement comprises:
PMOS transistor M3, its grid couples described electrion subelement second end (being power line 103), source electrode couples described electrion subelement second end (being power line 103), and drain electrode couples described electrion subelement first end (promptly coupling I/O pin 105 by resistance R 0).Wherein, the requirement that those skilled in the art can make the requirement of static and circuit design and technology according to product is provided with according to the parameter of conventional method pair pmos transistor M3 and resistance R 0.
In the present embodiment, described low pressure discharge subelement comprises:
Nmos pass transistor M4, its grid couples described low pressure discharge subelement second end (being substrate S ub), source electrode couples described low pressure discharge subelement second end (being substrate S ub), and drain electrode couples described low pressure discharge subelement first end (promptly coupling I/O pin 105 by resistance R 0).Wherein, the requirement that those skilled in the art can make the requirement of static and circuit design and technology according to product is provided with according to the parameter of conventional method pair nmos transistor M4 and resistance R 0.
With reference to figure 4, in the present embodiment, described functional unit is the CMOS transistor, except coupling with I/O pin 105, also has end idol to connect power line 103, and other end idol meets electronegative potential VSS.
From the cross-section structure aspect of this circuit, the present invention will be described in detail below.Cut open because profile is the P trap along NMOS place in the CDM esd protection circuit, therefore can only see nmos pass transistor and bipolar tube and resistance, and can't see the PMOS pipe.
As shown in Figure 5, described substrate is the P type, is aligned in sequence with low-voltage trigger protection unit, esd protection unit, the second level, local ESD protected location and functional unit on substrate.
The frame of broken lines that is positioned at Fig. 5 leftmost side is low-voltage trigger protection unit 130, and it comprises and is positioned on the P type substrate N trap 410 and the P trap of arranging back-to-back 420.Be aligned in sequence with a N type that is positioned at the N trap in the doped region that N trap 410 and P trap 420 constitute and mix 412; A P type that is positioned at the N trap mixes 414; The 2nd N type 416, the two N types that mix 416 parts of mixing are positioned at N trap 410, and remainder is positioned at P trap 420; The 2nd P type that is positioned at the P trap mixes 422; The 3rd N type that is positioned at the P trap mixes 424; The 3rd P type that is positioned at the P trap mixes 426.
Wherein, N type doping the 412 and the one P type doping 414 is coupled to I/O pin 105; The 2nd P type mixes and 422 to be coupled to I/O pin 105 by capacitor C 1; The 3rd N type doping the 424 and the 3rd P type doping 426 is coupled to the I/O pin of substrate.The I/O pin VSS-IO of substrate and the 2nd P type mix and are coupled with first resistance R 1 between 422.
Wherein, P trap 420, N trap 410, N type doping the 412, the 2nd P type doping the 422 and the 3rd P type doping 426 constitute PNP pipe P1; P trap 420, N trap 410, N type doping the 412, the 3rd P type doping the 426 and the 3rd N type doping 424 constitute NPN pipe N1.The volume resistance of well region forms dead resistance second resistance R 2 and the 3rd resistance R 3.
As shown in Figure 5; the isolated area that is positioned at N moldeed depth trap of esd protection unit, the second level and functional unit; functional unit is just protected by N moldeed depth trap like this; make the negative electrical charge in the substrate be not easy to arrive, significantly reduced the interior negative electrical charge of P trap at the NMOS place in esd protection unit, the second level and the functional unit.
When the negative electrical charge of described substrate make substrate electric potential less than described I/O pin surpass second specific voltage for (for example pin ground connection) time, then PNP pipe P1 and all conductings of NPN pipe N1 constitute two discharge channels.
When described substrate accumulated positive charge, then the diode of the parasitism of P trap and N trap formation can discharge, and makes positive charge be released by the voltage (for example pin ground connection) of described I/O pin.Simultaneously because power line and N trap couple so electrion subelement conducting of the first order, the second level and local esd protection unit, thereby the positive charge in the release liners.
Second embodiment
Fig. 6 is the CDM esd protection circuit schematic diagram of second embodiment of the invention.The CDM esd protection circuit of second embodiment of the invention is described and the something in common of first embodiment repeats no more below in conjunction with Fig. 6, difference is:
In the present embodiment, described SCR comprises:
Electric capacity, its first end is coupled to described input and output pin, and second end is coupled to first node;
The present invention is by being provided with first order esd protection unit in the CDM esd protection circuit; low-voltage trigger protection unit; esd protection unit, the second level and local esd protection unit be the level Four discharge circuit altogether; thereby make under the situation of IC I/O pin ground connection; because the existence of electric charge makes and has potential difference between substrate and the IC I/O pin in the substrate; thereby the cell operation of above-mentioned protection; promptly show as low-resistivity; the level Four discharge channel that passes through that electric charge in the substrate can be very fast discharges like this; and therein under the situation that damaging appears in the first class of protection circuit; the present invention still can regular picture; avoided because static makes that the MOS transistor grid oxide layer in the functional unit is breakdown; and the problem that the functional unit that causes lost efficacy; therefore CDM ESD circuit of the present invention is more stable, and performance is better.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (17)
1. a CDM esd protection circuit comprises power line, substrate and I/O pin, is used for functional unit is protected; Functional unit couples by resistance and described I/O pin;
It is characterized in that the CDM esd protection circuit also comprises:
First order esd protection unit, its first end is coupled to described I/O pin, and second end is coupled to power line, when the current potential of described power line during than high first specific voltage of the current potential of described I/O pin, then described first order esd protection cell operation;
Low-voltage trigger protection unit, its first end is coupled to described I/O pin, second end is coupled to described substrate, when the current potential of described substrate surpasses second specific voltage less than the current potential of described I/O pin, and then described low-voltage trigger protection cell operation;
Esd protection unit, the second level, its first end is coupled to described I/O pin by resistance, second end is coupled to described power line, the 3rd end is coupled to described substrate, when the current potential of described power line during than high the 3rd specific voltage of the current potential of described I/O pin, when perhaps the current potential of described substrate is than low the 4th specific voltage of the current potential of described I/O pin, then described second level esd protection cell operation;
The local ESD protected location; its first end is coupled to described I/O pin by described resistance; second end is coupled to described power line; the 3rd end is coupled to described substrate; when the current potential of described power line during than high the 5th specific voltage of the current potential of described I/O pin; when perhaps the current potential of described substrate is than low the 6th specific voltage of the current potential of described I/O pin, then described local ESD protected location work.
2. CDM esd protection circuit according to claim 1 is characterized in that, described low-voltage trigger protection unit is when the high 0.7V of voltage of the described I/O pin of the voltage ratio of described substrate and work when above.
3. CDM esd protection circuit according to claim 1 is characterized in that, described first order esd protection unit, low-voltage trigger protection unit, esd protection unit, the second level and/or local ESD protected location are clamp circuit.
4. CDM esd protection circuit according to claim 1 is characterized in that, the threshold voltage of described low-voltage trigger protection unit is less than the MOS transistor grid oxide layer puncture voltage in the esd protection circuit.
5. CDM esd protection circuit according to claim 1 is characterized in that, the threshold voltage of described low-voltage trigger protection unit is less than the threshold voltage of the MOS transistor of minimum feature size under the same technology characteristics size.
6. CDM esd protection circuit according to claim 1 is characterized in that, described low-voltage trigger protection unit is SCR.
7. CDM esd protection circuit according to claim 6 is characterized in that, described SCR is:
Electric capacity, its first end is coupled to described input and output pin, and second end is coupled to first node;
First resistance, its first end is coupled to described substrate, and second end is coupled to first node;
The PNP pipe, its emitter is coupled to described I/O pin, and base stage is coupled to described first node, and collector electrode is coupled to Section Point;
The NPN pipe, its emitter is coupled to described substrate, and collector electrode is coupled to the I/O pin by second resistance, and base stage is coupled to Section Point;
The 3rd resistance, its first end is coupled to described substrate, and second end is coupled to described Section Point.
8. CDM esd protection circuit according to claim 6 is characterized in that, described SCR is:
Electric capacity, its first end is coupled to described substrate, and second end is coupled to first node;
First resistance, its first end is coupled to described I/O pin, and second end is coupled to first node;
Nmos pass transistor, its grid is coupled to first node, and source electrode is coupled to substrate;
The PNP pipe, its emitter is coupled to described I/O pin, and base stage is coupled to the drain electrode of described nmos pass transistor, and collector electrode is coupled to Section Point;
The NPN pipe, its emitter is coupled to described substrate, and collector electrode is coupled to the I/O pin by second resistance, and base stage is coupled to Section Point;
The 3rd resistance, its first end is coupled to described substrate, and second end is coupled to described Section Point.
9. according to claim 7 or 8 described CDM esd protection circuits, it is characterized in that described SCR comprises: parasitic diode, its positive pole are coupled to described I/O pin, and negative pole is coupled to described substrate.
10. CDM esd protection circuit according to claim 1 is characterized in that, described first order esd protection unit comprises:
The PMOS transistor, its grid couples described first order esd protection unit second end by resistance, and source electrode couples described electrion subelement second end, and drain electrode couples described first order esd protection unit first end.
11. CDM esd protection circuit according to claim 1 is characterized in that, esd protection unit, the described second level comprises:
Electrion subelement, its first end couple esd protection unit, the described second level first end, and its second end couples esd protection unit, the described second level second end;
Low pressure discharge subelement, its first end couple esd protection unit, the described second level first end, and its second end couples esd protection unit, the described second level the 3rd end.
12. CDM esd protection circuit according to claim 11 is characterized in that, described electrion subelement comprises:
The PMOS transistor, its grid is couple to described electrion subelement second end by resistance, and source electrode couples described electrion subelement second end, and drain electrode couples described electrion subelement first end.
13. CDM esd protection circuit according to claim 11 is characterized in that, described low pressure discharge subelement comprises:
Nmos pass transistor, its grid is couple to described low pressure discharge subelement second end by resistance, and source electrode couples described low pressure discharge subelement second end, and drain electrode couples described low pressure discharge subelement first end.
14. CDM esd protection circuit according to claim 1 is characterized in that, described local ESD protected location comprises:
Electrion subelement, its first end couple esd protection unit, the described second level first end, and its second end couples esd protection unit, the described second level second end;
Low pressure discharge subelement, its first end couple esd protection unit, the described second level first end, and its second end couples esd protection unit, the described second level the 3rd end.
15. CDM esd protection circuit according to claim 14 is characterized in that, described electrion subelement comprises:
PMOS transistor, its grid are couple to described electrion subelement second end, and source electrode couples described electrion subelement second end, and drain electrode couples described electrion subelement first end.
16. CDM esd protection circuit according to claim 14 is characterized in that, described low pressure discharge subelement comprises:
Nmos pass transistor, its grid are couple to described low pressure discharge subelement second end, and source electrode couples described low pressure discharge subelement second end, and drain electrode couples described low pressure discharge subelement first end.
17. CDM esd protection circuit according to claim 1 is characterized in that, described substrate is the P type, and described local ESD protected location is positioned at the N trap.
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| CN201010111101.8A CN102148499B (en) | 2010-02-10 | 2010-02-10 | CDM (Charged Device Model) ESD (Electro-Static Discharge) protection circuit |
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| CN103972227A (en) * | 2013-01-31 | 2014-08-06 | 台湾积体电路制造股份有限公司 | Method and apparatus for forming an integrated circuit with a metalized resistor in a standard cell configuration |
| CN104319271A (en) * | 2014-10-17 | 2015-01-28 | 武汉新芯集成电路制造有限公司 | CDM (Charged-Device-Model) electrostatic protection circuit |
| CN104517957A (en) * | 2013-09-26 | 2015-04-15 | 特里奎恩特半导体公司 | Electrostatic discharge (ESD) circuitry |
| CN107204326A (en) * | 2016-03-17 | 2017-09-26 | 电信科学技术研究院 | A kind of static discharge ESD protective circuit applied to integrated circuit |
| CN107230673A (en) * | 2016-03-24 | 2017-10-03 | 恩智浦有限公司 | Use the electrostatic discharge (ESD) protection of zone of protection |
| CN107482004A (en) * | 2017-07-06 | 2017-12-15 | 北京时代民芯科技有限公司 | Multi-power source voltage integrated circuit ESD protects network under a kind of epitaxy technique |
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| CN104517957A (en) * | 2013-09-26 | 2015-04-15 | 特里奎恩特半导体公司 | Electrostatic discharge (ESD) circuitry |
| CN104319271A (en) * | 2014-10-17 | 2015-01-28 | 武汉新芯集成电路制造有限公司 | CDM (Charged-Device-Model) electrostatic protection circuit |
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| CN107230673B (en) * | 2016-03-24 | 2023-08-22 | 恩智浦有限公司 | Electrostatic discharge protection apparatus and method using a protection region |
| CN108666997A (en) * | 2017-03-28 | 2018-10-16 | 恩智浦有限公司 | Static discharge（ESD）Protective device and method for operating Esd protection device |
| CN108666997B (en) * | 2017-03-28 | 2022-02-25 | 恩智浦有限公司 | Electrostatic discharge (ESD) protection device and method for operating an ESD protection device |
| CN107482004A (en) * | 2017-07-06 | 2017-12-15 | 北京时代民芯科技有限公司 | Multi-power source voltage integrated circuit ESD protects network under a kind of epitaxy technique |
| CN109830478A (en) * | 2019-02-19 | 2019-05-31 | 杭州晶华微电子有限公司 | A kind of chip input pin esd protection circuit framework of ultralow leakage current |
| CN109830478B (en) * | 2019-02-19 | 2021-05-04 | 杭州晶华微电子股份有限公司 | ESD protection circuit framework of chip input pin with ultra-low leakage current |
| CN110470409A (en) * | 2019-08-02 | 2019-11-19 | 上海申矽凌微电子科技有限公司 | The distal temperature measuring system being easily integrated |
| CN113839374A (en) * | 2021-11-29 | 2021-12-24 | 珠海市杰理科技股份有限公司 | ESD power protection circuit, working power supply and chip |
| CN113839374B (en) * | 2021-11-29 | 2022-03-04 | 珠海市杰理科技股份有限公司 | ESD power protection circuit, working power supply and chip |
| CN114678853A (en) * | 2022-05-30 | 2022-06-28 | 芯耀辉科技有限公司 | CDM ESD protection circuit |
| CN117977518A (en) * | 2024-03-27 | 2024-05-03 | 杭州芯正微电子有限公司 | Substrate triggering type ESD protection circuit |
| CN117977518B (en) * | 2024-03-27 | 2024-06-04 | 杭州芯正微电子有限公司 | Substrate triggering type ESD protection circuit |
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