CN109830478B - ESD protection circuit framework of chip input pin with ultra-low leakage current - Google Patents
ESD protection circuit framework of chip input pin with ultra-low leakage current Download PDFInfo
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- CN109830478B CN109830478B CN201910124713.1A CN201910124713A CN109830478B CN 109830478 B CN109830478 B CN 109830478B CN 201910124713 A CN201910124713 A CN 201910124713A CN 109830478 B CN109830478 B CN 109830478B
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Abstract
The invention discloses an ESD protection circuit framework of a chip input pin with ultra-low leakage current, which comprises a power ground ESD clamper, a first-stage ESD protection module, a second-stage ESD protection module and a leakage current transfer absorption buffer. The first-stage ESD protection module comprises a first PMOS transistor, a second PMOS transistor and a first voltage input end; the second-stage ESD protection module comprises a third PMOS transistor, a fourth PMOS transistor, a third resistor, a second voltage input end and a high-resistance input end; the leakage current transfer absorption buffer comprises a first resistor, a second resistor and an amplifier, and is used for intercepting leakage current originally flowing to the input pin so as to realize zero leakage current of the input pin; the power ground ESD clamp has a positive terminal and a negative terminal and has electrostatic discharge capability to ESD positive and negative pulses between a power source and ground. The invention can be integrated in an SOC chip to realize the ESD protection of the input pin with ultrahigh input impedance.
Description
Technical Field
The invention relates to the field of electronics, in particular to an input pin ESD protection circuit architecture which is integrated in an SOC chip and can realize ultrahigh input impedance.
Background
With the rapid development of the internet of things in recent years, the types of sensors required to be acquired by a system-on-chip (SOC) are more and more, the internal resistance of some sensors is larger (such as PIR sensors), the front-end signal acquisition input end of the SOC is required to have ultrahigh input impedance (which may need to reach 1010 orders of magnitude), while the input pin of the traditional chip has an ESD protection device, and the large-size ESD protection device has a certain leakage current, especially under a high-temperature condition, the leakage current can reach 10-9 to 10-8 orders of magnitude, and the ultrahigh input impedance requirement of the sensor cannot be met, and if the ESD protection device of the input pin is removed, the chip is easy to have ESD damage failure, so the existing scheme generally needs to adopt special secondary processing packaging for the high-internal-resistance sensor and the ultrahigh input impedance buffer device, and finally reduces the output impedance to avoid the high-impedance requirement for, and chip ESD reliability is ensured. However, the scheme not only increases the secondary processing cost of the sensor, but also brings extra device noise on a signal acquisition channel, is not beneficial to high integration of the system, and limits the high integration and low-cost development of the application of the internet of things.
Disclosure of Invention
The invention aims to provide an input pin ESD protection circuit framework which is integrated in an SOC chip and can realize ultrahigh input impedance, so that the ultrahigh impedance characteristic of the input pin of the chip is realized, good ESD protection performance is kept, and necessary conditions are provided for realizing low cost, high integration and high reliability of the application of signal acquisition and processing of a high internal resistance sensor.
In order to achieve the purpose, the invention adopts the technical scheme that: the ESD protection circuit architecture comprises a power ground ESD clamp, a first-stage ESD protection module, a second-stage ESD protection module and a leakage current transfer absorption buffer.
The first-stage ESD protection module comprises a first PMOS transistor, a second PMOS transistor and a first voltage input end; the second-stage ESD protection module comprises a third PMOS transistor, a fourth PMOS transistor, a third resistor, a second voltage input end and a high-resistance input end; the leakage current transfer absorption buffer comprises a first resistor, a second resistor and an amplifier; the power ground ESD clamp has a positive terminal and a negative terminal and has electrostatic discharge capability to ESD positive and negative pulses between a power source and ground.
The source electrode, the grid electrode and the N well of the second PMOS transistor of the first-stage ESD protection module are connected with the power supply, the source electrode, the N well of the first PMOS transistor and the drain electrode of the second PMOS transistor are connected with the first voltage input end in a shared mode, and the drain electrode of the first PMOS transistor is connected with the chip input pin.
And the source electrode, the grid electrode and the N well of a fourth PMOS transistor of the second-stage ESD protection module and the grid electrode of a third PMOS transistor are connected with a power supply, the source electrode, the N well and the drain electrode of the third PMOS transistor are connected with a second voltage input end in a shared mode, the drain electrode of the third PMOS transistor and one end of a third resistor are connected with a high-resistance input end, and the other end of the third resistor is connected with a chip input pin.
One end of a first resistor and one end of a second resistor of the leakage current transfer absorption buffer are connected to the output end of the amplifier in common, the other end of the first resistor is connected to the first voltage input end of the first-stage ESD protection module, the other end of the second resistor is connected to the second voltage input end of the second-stage ESD protection module, the negative input end of the amplifier is connected to the output end of the amplifier, and the positive input end of the amplifier is connected to the high-resistance input end of the second-stage ESD protection module.
The positive end of the power ground ESD clamp is connected with a power supply, and the negative end of the power ground ESD clamp is grounded. The sizes of the first PMOS transistor and the second PMOS transistor are far larger than the sizes of the third PMOS transistor and the fourth PMOS transistor.
The invention has the beneficial effects that the ultra-low leakage current chip input pin ESD protection circuit provided by the invention is integrated in the SOC chip, so that the chip input pin has ultra-high input impedance performance under the condition of ESD electrostatic protection guarantee, and the SOC chip can directly acquire high internal resistance sensor signals, thereby realizing high-level collection, high reliability and low-cost application of the sensor signal acquisition and processing system.
Drawings
FIG. 1 is a schematic structural diagram of an embodiment of the invention.
Fig. 2 shows a leakage current diagram for the presence of a PMOS transistor.
Detailed Description
The technical scheme of the invention is further specifically described by the following embodiments and the accompanying drawings.
Example (b):
as shown in fig. 1, the present invention is an input pin ESD protection circuit architecture that can be integrated in an SOC chip to realize ultra-high input impedance, and includes a power ground ESD clamp 201, a first stage ESD protection module 202, a second stage ESD protection module 203, and a leakage current transfer absorption buffer 204.
The power ground ESD clamp 201 monitors electrostatic pulses between a chip power supply and the ground in real time, can discharge positive and negative electrostatic pulses between the power supply and the ground in time, clamps the voltage between the power supply and the ground to a safe voltage range which can be borne by internal devices of the chip, and when no electrostatic pulse exists between the power supply and the ground, the power ground ESD clamp 201 does not influence the power ground power supply of the chip.
The first-stage ESD protection module 202 forms a ggMOS electrostatic protection device through the PMOS transistors M1 and M2, and provides an electrostatic discharge path for electrostatic pulses on the input pin PAD, thereby implementing first-stage electrostatic protection.
The second-stage ESD protection module 203 jointly implements second-stage electrostatic protection of the input PAD through a ggMOS device formed by the current-limiting isolation resistor R3 and the PMOS transistors M3 and M4, and because the sizes of M3 and M4 are much smaller than M1 and M2, and the drain widths of M1 and M2 are larger than those of M3 and M4, the electrostatic protection trigger voltage of the first-stage ESD protection module 202 is larger than that of the second-stage ESD protection module 203, when an electrostatic pulse occurs on the input PAD, the second-stage ESD protection module 203 is triggered to be turned on in advance, and a corresponding electrostatic current is generated to flow through the resistor R3, so that the voltage on the PAD is quickly raised or pulled down to reach the electrostatic trigger voltage of the first-stage ESD protection module 202, and then a low-resistance electrostatic discharge path is opened to discharge the electrostatic charge on the input PAD pin VIN, thereby protecting an input point inside.
As shown in fig. 2, in the case that the gate G and the source S are at the same potential, the drain D of the PMOS transistor has a leakage current mainly including a source S to drain D leakage current ISD _ LEAK and an N-well backing B to drain D leakage current IBD _ LEAK of the reverse biased parasitic diode, and both ISD _ LEAK and IBD _ LEAK are proportional to the voltage difference between the two terminals, and the leakage current is more serious especially in the submicron process.
The leakage current transfer absorption buffer 204 is composed of resistors R1 and R2 and an amplifier Amp, wherein the amplifier Amp is connected in a one-time amplification mode, and buffers and outputs a useful low-frequency signal on an input pin PAD to a first voltage input terminal V1 of the first-stage ESD protection module and a second voltage input terminal V2 of the second-stage ESD protection module through resistors R1 and R2, respectively.
The bandwidth of the amplifier Amp is much larger than the useful signal frequency on the PAD, if the offset voltage of the amplifier Amp is neglected, (V1-PAD) = 0V, (V2-VIN) = 0V, zero leakage of V1 to PAD and zero leakage of V2 to VIN are realized, and the leakage of VDD through M2 to V1 and the leakage of VDD through M4 to V2 are absorbed and transferred to the leakage current transfer absorption buffer 204.
The bandwidth of the amplifier Amp is much smaller than the frequency of the ESD electrostatic pulse, so the leakage current transfer absorption buffer 204 does not affect the normal electrostatic protection operation of the first stage ESD protection module 202 and the second stage ESD protection module 203 of the input pin.
In the embodiment of the present invention, whether the amplifier Amp adopts a Rail-to-Rail Input/output architecture can be determined according to whether the Input pin signal is Rail-to-Rail Input (Rail-to-Rail Input); for the first-stage ESD protection module 202 and the second-stage ESD protection module 203, it should be understood by those skilled in the art that other ESD protection device structures such as gcMOS may be used instead of the ggMOS structure to perform similar ESD protection functions.
According to the invention, the leakage current transfer absorption buffer 204 is adopted, so that the voltage difference of the input pin PAD relative to V1 and V2 is nearly zero, the leakage current flowing through V1 and V2 is transferred and absorbed, the zero leakage current on the input pin PAD is realized, the ultrahigh input impedance characteristic is achieved, and meanwhile, the ESD performance of the input pin PAD is ensured through the system-level electrostatic protection formed by the first-level ESD protection module 202, the second-level ESD protection module 203 and the power ground clamp 201.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (5)
1. An ESD protection circuit architecture of a chip input pin with ultra-low leakage current comprises a power ground ESD clamp, a first-stage ESD protection module, a second-stage ESD protection module and a leakage current transfer absorption buffer, wherein the first-stage ESD protection module comprises a first PMOS transistor, a second PMOS transistor and a first voltage input end;
the second-stage ESD protection module comprises a third PMOS transistor, a fourth PMOS transistor, a third resistor, a second voltage input end and a high-resistance input end;
the leakage current transfer absorption buffer comprises a first resistor, a second resistor and an amplifier;
the power ground ESD clamp is provided with a positive end and a negative end and has electrostatic discharge capacity to ESD positive and negative pulses between a power supply and the ground;
one end of a first resistor and one end of a second resistor of the leakage current transfer absorption buffer are connected to the output end of the amplifier in common, the other end of the first resistor is connected to the first voltage input end of the first-stage ESD protection module, the other end of the second resistor is connected to the second voltage input end of the second-stage ESD protection module, the negative input end of the amplifier is connected to the output end of the amplifier, and the positive input end of the amplifier is connected to the high-resistance input end of the second-stage ESD protection module.
2. The ESD protection circuit architecture for chip input pin with ultra-low leakage current of claim 1, wherein the source, gate and N-well of the second PMOS transistor of the first stage ESD protection module and the gate of the first PMOS transistor are connected to the power supply, the source, N-well of the first PMOS transistor and the drain of the second PMOS transistor are connected to the first voltage input terminal, and the drain of the first PMOS transistor is connected to the chip input pin.
3. The ESD protection circuit architecture for chip input pin with ultra-low leakage current of claim 1, wherein the source, gate and N-well of the fourth PMOS transistor of the second stage ESD protection module and the gate of the third PMOS transistor are connected to the power supply, the source, N-well of the third PMOS transistor and the drain of the fourth PMOS transistor are connected to the second voltage input terminal in common, the drain of the third PMOS transistor and one end of the third resistor are connected to the high impedance input terminal, and the other end of the third resistor is connected to the chip input pin.
4. The ESD protection circuit architecture for chip input pins with ultra-low leakage current of claim 1, wherein the positive terminal of the power ground ESD clamp is connected to the power supply and the negative terminal is connected to the ground.
5. The ESD protection circuit architecture for an ultra-low leakage current chip input pin of claim 1, wherein the first and second PMOS transistors are larger in size than the third and fourth PMOS transistors.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910124713.1A CN109830478B (en) | 2019-02-19 | 2019-02-19 | ESD protection circuit framework of chip input pin with ultra-low leakage current |
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| CN201910124713.1A CN109830478B (en) | 2019-02-19 | 2019-02-19 | ESD protection circuit framework of chip input pin with ultra-low leakage current |
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| CN109830478B true CN109830478B (en) | 2021-05-04 |
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| CN117498845A (en) * | 2023-11-23 | 2024-02-02 | 上海类比半导体技术有限公司 | Low leakage switch and chip |
| CN117613834A (en) * | 2023-11-23 | 2024-02-27 | 上海类比半导体技术有限公司 | Ultra-low leakage ESD protection circuit and chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102148499A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | CDM (Charged Device Model) ESD (Electro-Static Discharge) protection circuit |
| CN104319271A (en) * | 2014-10-17 | 2015-01-28 | 武汉新芯集成电路制造有限公司 | CDM (Charged-Device-Model) electrostatic protection circuit |
| CN105556666A (en) * | 2013-09-12 | 2016-05-04 | 高通股份有限公司 | Electro-static discharge protection for integrated circuits |
| CN106486990A (en) * | 2016-12-16 | 2017-03-08 | 江苏理工学院 | Fine measuring instrument port overcurrent-overvoltage protecting circuit |
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2019
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102148499A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | CDM (Charged Device Model) ESD (Electro-Static Discharge) protection circuit |
| CN105556666A (en) * | 2013-09-12 | 2016-05-04 | 高通股份有限公司 | Electro-static discharge protection for integrated circuits |
| CN104319271A (en) * | 2014-10-17 | 2015-01-28 | 武汉新芯集成电路制造有限公司 | CDM (Charged-Device-Model) electrostatic protection circuit |
| CN106486990A (en) * | 2016-12-16 | 2017-03-08 | 江苏理工学院 | Fine measuring instrument port overcurrent-overvoltage protecting circuit |
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