CN112290522A

CN112290522A - Electrostatic protection circuit for 5G communication

Info

Publication number: CN112290522A
Application number: CN201910668782.9A
Authority: CN
Inventors: 陈磊
Original assignee: Hangzhou Lingxin Microelectronics Co ltd
Current assignee: Hangzhou Lingxin Microelectronics Co ltd
Priority date: 2019-07-23
Filing date: 2019-07-23
Publication date: 2021-01-29

Abstract

The invention discloses an electrostatic protection circuit used in 5G communication, comprising: a detection circuit, a buffer circuit, and a bleeder circuit. The cache circuit is composed of three phase inverters, two NMOS tubes, two PMOS tubes, a resistor and a capacitor. When the chip works normally, the electrostatic protection circuit does not work, and when an electrostatic event occurs, the electrostatic protection circuit can generate longer time to discharge current generated by static electricity to the drain pipe, so that the chip can have better antistatic performance.

Description

Electrostatic protection circuit for 5G communication

Technical Field

The invention relates to the field of electrostatic protection, in particular to a power supply clamping electrostatic protection circuit.

Background

In recent years, with the rapid development of integrated circuit processes, the line width of a MOS transistor is narrower, the junction depth is shallower, and the thickness of a gate oxide layer is thinner, which all accelerate the requirement of a circuit design for electrostatic discharge (ESD). When the line width is 1 [ mu ] m, the influence of an ESD event on a circuit is small, when the era of 0.18 [ mu ] m and 0.13 [ mu ] m, particularly the era below 90 nanometers, ESD becomes an irresistible problem, and the level of antistatic is improved when communication and the era of 5G are carried out at present, so that the reliability of the chip is further improved.

General ESD is classified into an HBM (Human body model) mode, an MM (machine model) mode, and a CDM (Charged device model) mode. The HBM and MM modes are external discharging to the chip, and are far from sufficient by means of an ESD protection circuit of an input/output port, and an ESD protection circuit (power clamp ESD circuit) needs to be added between a power supply and ground, so that current can be discharged more quickly, and the ESD performance of the whole chip is guaranteed.

Referring to fig. 1, a conventional power clamp ESD circuit includes a detection circuit, a buffer circuit, and a bleed circuit.

The detection circuit consists of a resistor R1 and a capacitor C1, the RC delay time of the detection circuit determines the time of current leakage, and the larger the delay time is, the more the current leakage time is. The detection circuit is used for detecting the ESD pulse and correctly distinguishing the ESD pulse from a normal power supply power-on pulse. When the power supply is normally powered on, the detection circuit ensures that the power supply clamp ESD circuit is not started, and when an ESD event occurs, the detection circuit can quickly detect an ESD pulse and guide the power supply clamp ESD circuit to work, so that current is discharged, and an internal circuit of the chip is protected.

And the buffer circuit consists of three inverters INV 1-INV 3 connected in series and is used for amplifying the output of the detection circuit and providing driving capability for the discharge circuit so as to drive the discharge tube to work.

The discharge circuit consists of an NMOS transistor M1 and is used for discharging ESD current, and when an ESD event occurs, the discharge circuit can be normally opened to discharge the ESD current; when the circuit is operating normally, the bleeding circuit is closed. Since the current is in the order of amperes when an ESD event occurs, the NMOS transistors of the bleeder circuits are large in size.

The power supply is normally powered up for a period of time typically around 1ms, while the ESD event occurs for a period of time on the order of tens of nanoseconds. The detection circuit not only needs to correctly distinguish the ESD pulse from the normal power-on pulse of the power supply, but also needs to increase the delay time as much as possible, so that the time for discharging the ESD current is increased. The detection circuit in fig. 1 is designed with a time delay by using an RC circuit, and if the RC time is long, the effect of the leakage current is better.

However, for a chip powered up quickly, false triggering can be caused, and the quick power supply is powered up mistakenly to be an ESD event, so that the normal operation of the chip is affected. If the circuit diagram of fig. 1 is adopted, the RC time constant cannot be designed to be long, otherwise the power-on of the chip is affected. But if the RC time attempt is not long enough, the ESD performance of the chip may be affected.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide an electrostatic protection circuit, which is to ensure that an ESD circuit is in a closed state when a chip is quickly powered on, so as not to trigger the ESD circuit to work by mistake, and to discharge ESD current as much as possible when an ESD event occurs.

To solve the above technical problem, an electrostatic protection circuit according to the present invention includes:

the detection circuit consists of a first resistor R1 and a first capacitor C1; the buffer circuit is composed of a first inverter INV1, a second inverter INV2, a third inverter INV3, a second resistor R2, a second capacitor C2, a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1 and a second PMOS transistor PM 2; and the bleeder circuit consists of a third NMOS transistor NM 3.

The invention is characterized in that: in the detection circuit, a first capacitor C1 and a first resistor R1 are connected in series and then serve as an output end of the detection circuit, the other end of the capacitor C1 is connected with the ground, and the other end of the resistor R1 is connected with a power supply VDD; the output end of the detection circuit, the input end of the first inverter INV1 and the input end of the third inverter INV3 are connected together, the output end of the first inverter INV1 is connected with the input end of the second inverter INV2, the output end of the second inverter INV2 is connected with the gate of the second PMOS transistor PM2, the output end of INV3 is connected with the gate of the first NMOS 1, the source of the NM1 is grounded, the drain of the NM1, one end of the second capacitor C2, one end of the second resistor R2 and the gate of the second NMOS transistor NM2 are connected together, the other end of the capacitor C2 is grounded, the other end of the resistor R2 is connected with the drain of the first PMOS transistor PM1, the source VDD of the PM1 is connected, the source of the NM2 is grounded, the drain of the NM2, the gate of the PM1 transistor, the drain of the PM2 and the gate of the third NMOS transistor NM3 are connected together; the source of the bleeder circuit, the third NMOS transistor NM3 is connected to ground, and the drain of the NM3 is connected to VDD.

Compared with the existing electrostatic protection circuit, the ESD protection circuit has the advantages that when an ESD event occurs, the ESD current can be discharged for more time through the design of the delay circuit and the feedback network, and the overall ESD protection performance is better.

Drawings

FIG. 1 is a schematic diagram of a conventional electrostatic protection circuit;

fig. 2 is a schematic diagram of an electrostatic protection circuit according to an embodiment of the present invention.

Detailed Description

The invention will be described in further detail with reference to the following detailed description and accompanying drawings:

referring to fig. 2, in the following embodiments, the electrostatic protection circuit of the present invention includes:

The resistor R1 and the capacitor C1 form a detection circuit, for example, the RC delay time is designed to be about 150ns, the occurrence time of ESD events is generally dozens of ns, when ESD events occur, the detection circuit can correctly detect the ESD events, and when a chip is quickly powered on (more than 200 ns), false triggering is avoided.

When the chip is normally powered on, the output end of the detection circuit is at a high level, the output end of the inverter INV2 is at a high level, the PM2 transistor is closed, and the bleeder current tube NM3 is in a closed state.

When an ESD event occurs, the output end of the detection circuit is at a low level, the output end of the inverter INV1 is at a high level, the output end of the inverter INV2 is at a low level, the PM2 tube is turned on, the NM3 tube starts to discharge current, the PM1 tube is in a constant off state at this time, due to the existence of the delay circuit and the feedback network, the time for turning off the NM2 tube is longer, the grid of the NM3 tube can last longer and have higher voltage, the NM3 tube can discharge ESD current more sufficiently, and finally the antistatic performance of the circuit is better.

In simulation, for the same high-voltage pulse of 50ns, simulation data show that the grid of the bleeder in the background art can only last for a high-voltage time of 22ns, while the grid of the bleeder in the invention can last for a high-voltage time of 52ns, so by contrast, the bleeder in the invention has more sufficient time to discharge ESD current.

In this embodiment, the resistance of the resistor R1 is 100k ohms, the capacitor C1 is 10pF, the resistor R2 is 100k ohms, the capacitor C2 is 5pF, the size of the PM1 tube is 100um/1um, the size of the NM1 tube is 50um/1um, the size of the PM2 tube is 200um/1um, the size of the NM2 tube is 100um/1um, the size of the NM3 tube is 600um/0.5um, and the size of the NM3 tube can be further increased according to requirements; the P pipe size in the three phase inverter all is 50um/0.5um, and the N pipe size in the three phase inverter all is 25um/0.5um, and wherein NM3 pipe needs to walk the heavy current, therefore the metal of source electrode and drain electrode is walked the width and is all needed to be greater than 40 um.

Although the present invention has been described with reference to specific examples, the description of the examples does not limit the scope of the present invention. Various modifications and combinations of the embodiments will be readily apparent to those skilled in the art, by reference to the description of the invention, without departing from the spirit and scope of the invention.

Claims

1. An electrostatic protection circuit for 5G communication, comprising: the detection circuit consists of a first resistor R1 and a first capacitor C1; the buffer circuit is composed of a first inverter INV1, a second inverter INV2, a third inverter INV3, a second resistor R2, a second capacitor C2, a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1 and a second PMOS transistor PM 2; and the bleeder circuit consists of a third NMOS transistor NM 3.

2. As described in claim 1, wherein: in the detection circuit, a first capacitor C1 and a first resistor R1 are connected in series and then serve as an output end of the detection circuit, the other end of the capacitor C1 is connected with the ground, and the other end of the resistor R1 is connected with a power supply VDD; the output end of the detection circuit, the input end of the first inverter INV1 and the input end of the third inverter INV3 are connected together, the output end of the first inverter INV1 is connected with the input end of the second inverter INV2, the output end of the second inverter INV2 is connected with the gate of the second PMOS transistor PM2, the output end of INV3 is connected with the gate of the first NMOS 1, the source of the NM1 is grounded, the drain of the NM1, one end of the second capacitor C2, one end of the second resistor R2 and the gate of the second NMOS transistor NM2 are connected together, the other end of the capacitor C2 is grounded, the other end of the resistor R2 is connected with the drain of the first PMOS transistor PM1, the source VDD of the PM1 is connected, the source of the NM2 is grounded, the drain of the NM2, the gate of the PM1 transistor, the drain of the PM2 and the gate of the third NMOS transistor NM3 are connected together; the source of the bleeder circuit, the third NMOS transistor NM3 is connected to ground, and the drain of the NM3 is connected to VDD.