CN101421896A - ESD clamp control by detection of power state - Google Patents

Abstract

The present invention provides an improvement on ESD protection circuitry by controlling the trigger circuit to prevent the unwanted triggering of the device. The circuitry includes an ESD clamp with a trigger circuit coupled to the clamp. Both the clamp and the trigger circuit are coupled to a first reference potential. The circuitry also includes a control line coupled to the trigger circuit. The control line is coupled to a second reference potential to further control the behavior of the trigger circuit such that when the power is supplied to the second reference potential, the control line disables the trigger circuit, and when power is not supplied to the second reference potential, the control line enables the trigger circuit.

Description

ESD clamp control by power state detection

Cross reference to related application

The application requires the U.S. Provisional Application No.60/794 that submits on April 21st, 2006, and 078 and the U.S. Provisional Application No.60/794 that submits on April 21st, 2006,297 right, the full content of these two applications is hereby incorporated by.

Technical field

Present invention relates in general to Electrostatic Discharge protective circuit field, more specifically, relate to improvement the circuits for triggering in the protective circuit of control integrated circuit (IC).

Background technology

In order to protect the sensitive node among the IC not to be subjected to the ESD stress influence, the ESD clamp circuit need be placed on point specific in the circuit.A pith of ESD clamp circuit is a trigger device.This trigger device will detect esd event and open the ESD clamp circuit.This trigger device can be used in combination with any ESD clamp circuit of for example MOS, SCR or other ESD clamp circuit.

For setting up trigger device, there are many different topological structures.As illustrated in fig. 1, such example is shown in the existing techniques in realizing mode of the circuit 100 of the power protection clamp circuit that triggers based on the RC time constant.Circuit 100 comprises the ESD clamp circuit, and it is the MOS transistor MP102 that is used for conduction current under enable mode (active mode).This big MOS device MP 102 is connected (drain-source) between first voltage 104 and second voltage 106, first voltage 104 Vdd power line preferably wherein, and second voltage 106 Vss power line preferably.This big MOS device 102 or above-mentioned combination are called as main ESD clamp circuit or protection component.Resistor (R1) 108 is connected between the grid and first voltage 104 of ESD MOS device 102.Circuit 100 also comprises another MOS device (MN) 110, and its source electrode is connected to the gate terminal of ESD MOS device 102.Circuits for triggering are included in capacitor C 112 and the resistor R 2 114 that the gate terminal place of ESD MOS clamp circuit 102 and MOS device 110 provides.So, mos gate utmost point signal is generally directly or indirectly from comprising (MOS) electric capacity 112 and (MOS) the RC timer circuit derivation of resistor 114.

The time constant that is used for this RC filter configuration depends on the actual value of R 110 and C108 element.The existing techniques in realizing mode generally has the time constant of the 50ns-5us order of magnitude.The main thought of this method is when the voltage on the vdd line road 104 rises enough soon (scope than 50ns-5us is fast), makes esd protection clamp circuit 102 be in conduction mode in the ESD stress path.This guarantees good esd protection in chip processing and the transportation.

When chip (being esd protection clamp circuit 102), MOS device 112 and resistance R (20) 114 at line on the pcb board and when in system, powering up; capacitor C 112 chargings and MOS clamp circuit 110 from the RC filter disconnect, and the OFF signal arrives main ESD clamp circuit 102.When fast voltage/current pulses is injected on the power line in the chip on-state process, voltage on the capacitor C 112 can change, this can cause being used for the ON signal of MOS clamp circuit device 110 and this can make main ESD clamp circuit 102 enter conducting state, thereby the short time is reduced supply voltage.Therefore, these fast-pulses can be toggled to conducting state with power supply clamp 102, and this is undesirable in normal course of operation, as below with reference to Fig. 2 and 3 illustrated.

With reference to figure 2, show the existing techniques in realizing mode of the circuit 100 of Fig. 1, comprise the load variations of being seen by output driver 202 201, wherein output driver 202 is by being placed into circuit definition that chip 206 o pads (pad) 204 (inner or outside) locate.When load variations 201 when a value changes to another value, electric current will flow through output driver 202, so power supply Vdd104 will be no longer constant, and will be promptly no longer stable, and introduce some spikings (spike) at power supply.If power supply Vdd 104 is no longer stable, then the triggering element of the ESD clamp circuit 102 of circuit 100 (C 112 and R 114) is regarded it quick incident as and is defined as esd event thus.Trigger element and will make main ESD clamp circuit 102 enter on-state, guide current flows through ESD clamp circuit 102.This electric current is unexpected and non-hope for normal operation.Fig. 2 A shows the picture specification based on the voltage and current pulse of the load variations of Fig. 2.

With reference to figure 3, show the existing techniques in realizing mode of Fig. 1 circuit 100, wherein there is electric current to flow through output driver 202 equally, cause the instability of VDD power line 104, but electric current is to be introduced by the switching of output driver 202 now.Similar with Fig. 2, the change of Drive Status will cause that leakage current flows in the ESD MOS clamp circuit 102 under the normal condition.Fig. 3 A shows based on the picture specification by the voltage and current pulse of internal switch 302 load variations that causes of Fig. 3.More than also can occur in the driver that is in chip internal fully in the influence described in Fig. 2 and 3, but because the current capacity of these drivers is much smaller, so possibility is less.

Although attempted in the past reducing time constant, but still exist in the undesirably danger of trigger device in the normal power source tape electricity running by different circuit engineerings.

Description of drawings

Fig. 1 shows the circuit diagram explanation of the existing techniques in realizing mode of the power protection clamp circuit that triggers based on the RC time constant.

Fig. 2 shows the circuit diagram explanation of the existing techniques in realizing mode of load variations.

Fig. 2 A shows the picture specification based on the voltage and current pulse of the load variations of Fig. 2.

Fig. 3 shows the circuit diagram explanation of the existing techniques in realizing mode of load variations.

Fig. 3 A shows the picture specification based on the voltage and current pulse of the load variations of Fig. 3.

Fig. 4 shows the block diagram illustrations according to one embodiment of the present invention ESD clamp/trigger element control in a voltage domain.

Fig. 5 shows the block diagram illustrations that according to the present invention another execution mode is used for the power protection clamp circuit of two voltage domains.

Fig. 6 shows the block diagram illustrations of the circuits for triggering of Fig. 5.

Fig. 7 shows the circuit diagram explanation of the circuits for triggering of Fig. 5.

Fig. 8 shows the circuit diagram explanation of the power protection clamp circuit of employed Fig. 7 in simulation.

Fig. 8 A shows the chart of analog result of the 200fF capacitor of key diagram 8.

Fig. 8 B shows the chart of analog result of the 250fF capacitor of key diagram 8.

Fig. 8 C shows the chart of analog result of capacitor of all size of key diagram 8.

Fig. 9 shows the circuit diagram explanation of power protection clamp circuit block diagram that according to the present invention another execution mode is used for Fig. 5 of low voltage domain.

Figure 10 shows the circuit diagram explanation according to the power supply anti-noise active clamping circuir of one embodiment of the present invention.

Figure 11 shows the circuit diagram explanation of the power supply anti-noise active clamping circuir of another execution mode according to the present invention.

Figure 12 shows the circuit diagram explanation of the power supply anti-noise active clamping circuir with cut-off switch transient control of another execution mode according to the present invention.

Figure 12 A shows the chart of the voltage behavior that the circuit that adds Figure 15 in the electric process is described.

Figure 12 B shows the chart of the electric current behavior that the circuit that adds Figure 15 in the electric process is described.

Figure 12 C shows the chart of the behavior of the circuit of Figure 15 in the explanation HBM event procedure.

Figure 13 shows the circuit diagram explanation according to the power supply anti-noise active clamping circuir with the control of cut-off switch minimum voltage of alternative embodiment of the present invention.

Figure 14 shows the circuit diagram explanation of the power supply anti-noise active clamping circuir with the control of cut-off switch maximum voltage of another optional execution mode according to the present invention.

Figure 15 shows that another execution mode utilizes another voltage domain state to control the circuit diagram explanation of the power supply anti-noise active clamping circuir of cut-off switch according to the present invention.

Summary of the invention

The invention provides the esd protection circuit that comprises the ESD clamp circuit and be coupled to the circuits for triggering of this clamp circuit.Clamp circuit and circuits for triggering all are coupled to first reference potential.This circuit also comprises the control line that is coupled to circuits for triggering.This control line is coupled to second reference potential.Therefore, when electricity is provided to second reference potential, control line forbidding circuits for triggering, and when electricity was not provided to second reference potential, control line enabled circuits for triggering.

Embodiment

With reference to figure 4, disclose according to the block diagram 400 of one embodiment of the present invention by the general view of the ESD clamp/trigger element of control line control.ESD clamp circuit 402 is coupled to trigger circuit/element 404, they are coupling between first reference potential and second reference potential together, and wherein first reference potential is power line Vdd 406, and it is a positive voltage, and second reference potential is power line Vss 408, and it preferably.In addition, control line 410 adds trigger circuit/trigger element 404 to, so that control this circuits for triggering.Preferably, control line is coupled to second source line/power supply (not shown).Should be pointed out that under this specific situation because circuits for triggering 404 are the low resistance path between second source and the main ESD clamp circuit 402, so this is enough to trigger ESD clamp circuit 402.But, in the described ordinary circumstance of Fig. 4, if second source tape electricity, promptly (" on-state ") voltage applies by control line 410 in normal course of operation, then control line 410 sends signal and makes circuits for triggering 404 disconnections, and this can forbid ESD clamp circuit 402 again.This will prevent that electric current from flowing, i.e. ESD electric current is at normal in service becoming " connection " state.If there is noise the input, this can induce transient noise to the first power line Vdd 406, and then because trigger is placed to another power line (noise ratio there is less), so ESD clamp circuit 402 will can not trigger.But when not powering up (" disconnection " state), circuits for triggering 404 are opened, and this makes ESD clamp circuit 402 be in enable mode again or can trigger in the esd event process.This method makes the ESD of esd protection clamp circuit can be used for the very little and even negative design window in specific voltage territory.For very little and even negative design window,, reach the ESD element that specific voltage (trigger voltage) is just opened if therefore be difficult to use because design window is too little.When the second source line disconnected, circuits for triggering were in low-down voltage triggered.

Should be pointed out that in one embodiment of the invention the circuits for triggering 404 of Fig. 4 preferably include at least one MOS device.If the voltage at control line 410 places for example is lower than the threshold voltage of this MOS, then circuits for triggering 404 enable ESD clamp circuit 402.If the voltage at control line 410 places is higher than the threshold voltage of this MOS, then circuits for triggering 404 are forbidden ESD clamp circuits 402.

For the IC with a plurality of voltage domains, the order that different voltage domains power up can preferably be specified in normal course of operation.Preferably, the state of the voltage domain that need at first power up can be used to open or disconnect esd protection clamp circuit about other voltage domain of IC.Similarly, second voltage domain that powers up can be used to open or disconnect esd protection clamp circuit about other voltage domain of the IC except that first voltage domain that powers up, or the like.Common version with a plurality of voltage domains comprises that IC goes up the little circuit that enables or forbid esd protection clamp circuit in the specific voltage territory according to the current status of other voltage domain.The example of this generic block circuit (block circuit) 500 illustrates in Fig. 5, it has two different voltage domains, promptly comprises the Vdd1-Vss1 (Vdd1 voltage domain) 502 and the Vdd2-Vss2 (Vdd2 voltage domain) 504 that comprises Vdd2 504a and Vss2 504b of Vdd1 502a and Vss1 502b.In this example, Vdd1 voltage domain 502 is appointed as in normal course of operation and is at first powered up, and Vdd2 voltage domain 504 is powering up thereafter.Therefore, the voltage level on the Vdd1 voltage domain 502 is used for defining the state of Vdd2 voltage domain 504 ESD clamp circuits.Generic block circuit 500 mainly comprises three parts, detects the power sense circuit 506 whether Vdd1 voltage domain 502 powers up.Power sense circuit 506 the simplest forms are the short circuits between Vdd1 502a and circuits for triggering 404 inputs.Circuits for triggering piece 404 is coupled to power sense circuit 506, and wherein circuits for triggering piece 404 uses the signal from power detection 506 to allow or do not allow ESD clamp circuit 402 to open.Be exactly that this ESD clamp circuit 402 will consume actual ESD energy.In brief, the situation whether particular power source voltage is applied to Vdd1 voltage domain 502 prevents the ESD clamp circuit 402 that circuits for triggering 404 trigger on the Vdd2 voltage domain 504, perhaps in other words is to disconnect ESD clamp circuit 402.

Under a kind of state, not in normal course of operation, when outage, promptly the first voltage domain Vdd1 502 (between Vdd1 502a and the Vdd2 502b) is in 0 voltage, at the second voltage domain Vdd2 504 (between Vdd2 504 and the Vss2 504b) esd event is arranged.In this state, power sense circuit 506 also will be exported 0 voltage, and this voltage is the input of circuits for triggering 404.These circuits for triggering 404 be designed to when control line 410 be input as 0 voltage the time search the esd event at the second voltage domain Vdd, 504 places.This will make circuits for triggering 404 become " connection " state, thereby provide high voltage in output, and this high voltage is the triggering signal that triggers ESD clamp circuit 402.

At another state, when power connection, for example the first voltage domain Vdd1,502 places are 1.2 volts, at the second voltage domain Vdd2 504 esd event are arranged, its for example about 1.8 volts.The output of power sense circuit 506 has high voltage, and promptly 1.2 volts, this voltage is the input of circuits for triggering 404, and circuits for triggering 404 will provide low-voltage in its output again, thereby disconnects ESD clamp circuit 402.Should be pointed out that this is the example that high output is provided at circuits for triggering 404 places, can be created in circuits for triggering 404 and provide high output so that disconnect other implementation of main ESD clamp circuit 402.And, when receiving high input, provide the circuits for triggering 404 of low output preferably can comprise at least one inverter (not shown).Described circuits for triggering 404 can be preferably will can not detect at the short circuit (not shown) of the esd event at second voltage domain, 504 places or preferably based on the circuits for triggering (not shown) at the esd event at the second voltage domain place of can detecting of RC.In addition, circuits for triggering preferably can also comprise the combination of inverter etc.Therefore, many different circuits for triggering execution modes will more specifically be described below.

A kind of execution mode of power sense circuit 506 illustrates in Fig. 6.In Fig. 6, power sense circuit 506 is embodied as from Vdd1 502a to circuits for triggering 404 connection, and ESD clamp circuit 402 is embodied as SCR 602.Circuits for triggering 404 among Fig. 6 are shown and comprise two parts, and ESD is fed current to the PMOS 604 of ESD clamp circuit 602 and the flight data recorder 606 of control trigger PMOS 604 grids.In the ESD process, when Vdd1 502a and Vdd2 504a place did not have electricity, PMOS 604 was in conducting state, and power sense circuit 506 provides the output of 0 voltage, and this output is the input of flight data recorder 606.This grid voltage that makes flight data recorder 606 will arrive PMOS 604 in the ESD process remains low level.The low level at PMOS 604 grid places makes can trigger clamp circuit 602 in the ESD process.Charged and when at Vdd2 504a place esd event being arranged, power sense circuit 506 provides high voltage output as normal Vdd line 502a in service, this output is the input of flight data recorder 606.This makes flight data recorder 606 keep high voltage at the grid of PMOS 604, and it is become off state and forbids ESD clamp circuit 602 thus.Therefore, flight data recorder 606 can preferably become appropriate voltage with the voltage transitions from its input so that certain inverter circuit at least of control PMOS 604.

Fig. 7 shows the circuit diagram explanation of the circuits for triggering 404 of Fig. 5 in a preferred embodiment of this invention.In this drawing, power sense circuit 506 also is embodied as the control line 410 that is connected to circuits for triggering 404 from Vdd1 502a.Circuits for triggering 404 are the combination of capacitor 710, logic sum gate 702 and inverter 704 basically, and wherein the output of logic sum gate 702 feeds back to an one input.As shown in Figure 7, logic sum gate 702 comprises transistor M1, M2, M3 and M4, and inverter 704 comprises transistor M5 and M6.Node 1 706 is shown the output of transistor M1 drain electrode, and this node 1 provides the signal that enters inverter 704.Node 2708 is the output of inverter 704, and this node 2 provides the triggering signal that enters ESD clamp circuit 402.

Normally in service, if apply voltage in Vdd1 territory 502, then Vdd1 502a is in " connection " state, and promptly voltage at first is applied to Vdd1 502a, and this will turn-on transistor M1 and turn-offs transistor M2.This will make the drain voltage of M1 node 1 706 is pulled to 0 volt Vss2.Therefore, node 1 706 is subjected to the voltage control at Vdd1 502a place.The voltage signal of node 1706 is the inputs to inverter 704, because node 2 708 is the output of inverter 704, so inverter 704 is pulled to node 2 708 Vdd2 504a voltage, i.e. high voltage again.The high voltage at node 2 708 places will send the signal that disconnects ESD clamp circuit 402 and clamp circuit 402 is not triggered.Should be pointed out that if Vdd1-Vss1 is a low voltage domain and Vdd2-Vss2 is a high voltage domain, then low-voltag transistor type and high voltage type can be used for input transistors M1 and M2 the two.And, if Vdd1-Vss1 is a high voltage domain and Vdd2-Vss2 is a low voltage domain, then high voltage transistor type and lower-voltage type can be used for input transistors M1 and M2 the two.

In the ESD process, at first voltage domain, i.e. Vdd1 502a, all electricity have all broken, and ESD stress is applied to the second voltage domain Vdd2 504a now, and promptly Vdd2 504a is in " connection " state, because transistor M1 turn-offs, so this makes node 1 706 no longer be subjected to the control of Vdd1502a.But the voltage at Vdd2 504a place is increasing and will continue increase.Because the cause of electric capacity 710, node 2 will be pulled to Vss2 504b at first, M3 will turn-off and M4 with conducting.The charging of electric capacity will than the rising of voltage on the VDD2 504a line slowly many.This will make the voltage of node 2 be lower than the switched voltage of another inverter that is formed by M3 and M4.This will provide high voltage at node 1 place.Because node 2 is to be the output of the inverter 704 of input with node 1, so this output will be low-voltage.This low-voltage makes that opening ESD clamp circuit 402 in the ESD process becomes possibility.Should be pointed out that node 2 will remain on low-voltage owing to feed back the cause that connects.

Fig. 8 shows the circuit diagram explanation of it being carried out Fig. 7 power protection clamp circuit of simulation.This circuit diagram and Fig. 7 are similar, and wherein ESD clamp circuit 402 is shown second inverter in preferred implementation of the present invention.But because this first voltage domain is considered to uncharged as shown in Figure 8, the control line 410 that therefore is connected to Vdd1 502a usually as shown in Figure 7 is connected to Vss2 504a, i.e. ground connection now.In addition, Vdd1 bus 502a (not shown) is coupled to control line 410 and Vss1 502b (not shown) is coupled to Vss2 504b, so Vdd1 bus 502a (not shown) is coupled to ground by capacitor C1 710, and wherein C1 710 simulates by short circuit.

Analog result is shown in Fig. 8 A and Fig. 8 B.Fig. 8 A shows the chart of analog result of the 200fF capacitor C1 710 of key diagram 8.Fig. 8 B shows the chart of analog result of the 250fF capacitor C1 710 of key diagram 8.Two simulations all are that the signal that the oblique line on the Vdd2 with fast rise time rises is carried out, thereby simulate esd discharge on the Vdd2 with respect to Vss.

The figure of Fig. 8 A illustrates that initial node 1 rises, but has been dragged down after a while, makes node 2 uprise.Because this is the situation that ESD clamp circuit 402 does not trigger, this situation is undesirable.Therefore, as mentioned above, inverter (M5 and M6) 706 is put into the back of node 2, so that the signal on amplification and the monitor node 2, this signal can be used to drive esd protection.The output of this inverter is shown as " output " signal.The conclusion that draws from this simulation is that to have the capacitor C1 710 of value of 200fF too little, enables suitable triggering to such an extent as to can not simulate having in the process of the esd event on the Vdd2 of rise time.

The figure of Fig. 8 B has illustrated the wherein enough big simulation of capacitance of C1, and promptly capacitance is 250fF.In the oblique line uphill process of Vdd2 signal, node 2 will rise, but the pulse in the input of transistor M3 and M4 is slowed down.At specific point, inverter 704 (M5 and M6) will switch, and its output node 2708 is with step-down.Node 1 706 will be drawn high again.Output as second inverter of ESD clamp circuit 402 will also will become height (being shown " output " in the drawings) thus now from output node 2708 receiving inputted signals.This is the situation that esd protection was triggered and voltage on the Vdd2 504a was clamped to safety value.

Fig. 8 C shows the chart of analog result of capacitor C1 of all size of key diagram 8.In the chart of Fig. 8 C, be three comparisons that different capacitances are 200fF, 250fF, 500fF to C1.Can see that electric capacity is big more, output signal is clamped to Vdd2 and fast more unlatching esd protection more soon.But,, on performance, can't see very big difference for surpassing 250fF.For these simulations, to normal operation electric capacity become too low critical value 200 and 250fF between certain position.For other technology, this value can be different.Therefore, the preferred value of capacitor C1 is 250fF.But, should be pointed out that for different technologies or transistor size this value can be different.

Fig. 9 shows the circuit diagram explanation of power protection clamp circuit block diagram of Fig. 5 of another execution mode according to the present invention, and wherein the power protection clamp circuit is as the power line protection of the low voltage domain of IC.In this embodiment, first voltage domain, promptly Vdd1 502, be in high voltage (HV) territory, and the second voltage domain Vdd2 504 are in low-voltage (LV) territory.ESD clamp circuit among Fig. 9 of this execution mode preferably comprises the SCR of PNP transistor 402a and NPN transistor 402b.Power detection 506 comprises that short circuit or the resistance between the input of Vdd1 and circuits for triggering 404 connects.Circuits for triggering 404 itself are the short circuits between its input and the G2 of SCR402.Therefore, because circuits for triggering 404 only are short circuits in this embodiment,, and there are not the circuits for triggering of physics so ESD clamp circuit 402 is connected to power sense circuit 506.Therefore, the G2 trigger tap is connected to the Vdd1 line 502a of the first voltage domain Vdd2 502, and the first voltage domain Vdd2 502 is high voltage domain in this embodiment.High voltage domain 502 is designated as when normal operation and at first powers up.Therefore, in normal course of operation, promptly in not having the process of esd event, electricity will at first be applied to Vdd1 502a (high voltage domain).The voltage at the voltage ratio Vdd1 502a place at Vdd2 502b place is much lower, and therefore, the voltage difference between Vdd2 502b and the Vdd1 502a is a negative value.Therefore, because in order to allow SCR 402 trigger, the grid voltage at G2 place must be 0.7 volt at least, so SCR 402 will can not trigger.If the voltage on the A node, promptly the voltage tied of the Vdd2-G2 of SCR 402 is greater than 0.7V, and then PNP 402a conducting and the electric current that enters NPN 402b will cause the feedback of the ESD operation of starter.If this voltage reduces, then not conducting of PNP 402a and therefore not SCR 402 operations of starter.Since chip capacity will keep Vdd1502a near the voltage of Vss1 502b and since the voltage rising (esd event) of Vdd2 504a above 0.7 volt, therefore the difference between the voltage at 402a and G2 place also will be above 0.7 volt, thereby trigger device provides sufficient clamp thus with the SCR mode operation between Vdd2 504a and Vss2 504b.Inverse parallel diode 508 is placed under the ESD situation at two Vss lines, promptly connects between Vss1 502b and the Vss2 504b.This is because because the voltage difference in the normal course of operation is very little, diode just is enough to ESD is provided the path, so need esd protection between the Vss line.Therefore, two diodes 508 that are configured to back-to-back configuration as shown in Figure 9 will provide two-way esd protection.

When esd discharge from Vdd2 504a when Vss1 504b takes place, the voltage at Vdd2 504a place is 0 volt for the voltage at height Vdd1 502a place.As shown in Figure 9, G2 is coupled to Vdd1502a, and thus owing to chip capacity 510 is coupled to Vss1 502b.

With reference to Figure 10, show the circuit diagram explanation of block diagram of the power protection clamp circuit 1000 of Fig. 5.The circuit diagram of Figure 10 has illustrated according to the present invention the power supply anti-noise active clamping circuir circuit 1000 of another execution mode.As shown in figure 10, ESD clamp circuit 402 preferably is embodied as MOS device 1002 and circuits for triggering 404 preferably are embodied as RC transient detector 1006.Although MOS device 1002 is shown PMOS among the figure, also may use this technology to NMOS.The RC transient detector comprises resistor (R) 1007 and capacitor (C) 1008 and is connected to the switch 1009 of C1008 that switch 1009 control power line Vdd are to the connection of C1008.As shown in the figure, control line preferably is connected to switch 1009.In this embodiment, the power supply noise problem can prevent by utilize switch 1009 isolating capacitor C1008 and power line under the chip belt electricity condition.

ESD occurs between Vdd line 406 and the Vss line 408, perhaps also can occur between IO (not shown) and the Vss408 for IO protection or between Vdd 406 and the IO (not shown).In the ESD process, switch 1009 closures promptly are in conducting state, and capacitor 1008 is connected in the RC filter 1006, produce the RC time constant that is used for power supply clamp resembling in the prior art.But, in normal course of operation, there is not esd event, electric capacity 1008 utilizes switching device 1009 and RC filter 1006 to disconnect.When the fast transient situation appears on the power line, in the time of promptly on the Vdd line 406, condenser charge/voltage can not change again.Because the quick change of power supply potential, capacitor C 1008 will prevent circuits for triggering from this disconnection of Vdd line 406, i.e. the triggering of RC detector 1006.Therefore, switch 1009 is also referred to as " cut-off switch " usually.This name is in order to illustrate, rather than will limit by any way.For many noisy application, resemble automobile application, power governor, big display driver, to use but be not limited to these, switching device 1009 is very useful.In most of the cases, this switch is the active device by other circuit control on the chip.

Although should be pointed out that ESD clamp circuit 402 is shown MOS transistor 1002 in Figure 10, the ESD clamp circuit preferably can also comprise bipolar transistor, SCR, diode or any other device.In order further to explain the operation principle of the invention of this execution mode, more many cases is below described, these examples do not limit the scope of the invention, and only are for illustrative purposes.

Figure 11 shows the circuit diagram explanation 1100 of the power supply anti-noise active clamping circuir of another execution mode according to the present invention.Figure 11 and Figure 10 are similar, and switch 1009 is embodied as SCR 1102.Triggering SCR 1102 can carry out in many ways.In normal course of operation, SCR 1102 will not trigger, and this will disconnect capacitor 1008.In the ESD process, SCR 1102 opens and capacitor 1008 is connected to the grid (perhaps generally speaking being to be connected to ESD clamp circuit 402) of PMOS 1002.Should be pointed out that because the negative electrode of SCR 1102 is coupled to capacitor C 1008, so SCR 1102 can not produce any locking danger again.In this example, SCR 1102 is that G2 triggers.Other triggering configuration that for example two triggerings or G1 trigger also can be used.The triggering that another interested fact is SCR 1102 is unwanted for the device as the work of esd protection device.But if SCR 1102 does not trigger in the ESD process, then because its parasitic capacitance must be enough big, so device widths must be enough big.If SCR 1102 triggers in the ESD process, then the SCR size can be done smallerly, because it can be modeled as diode (resistor in the small signal equivalent) in this case.

Figure 12 shows the circuit diagram explanation 1200 of the power supply anti-noise active clamping circuir of another execution mode according to the present invention.Figure 12 and Figure 11 are similar, and cut-off switch 1009 is embodied as a PMOS device 1202.Therefore in this embodiment, circuits for triggering are first timing circuits 1204 that comprise R 1007, C 1008 and a PMOS device 1202.In order to control the grid of cut-off switch, promptly there is multiple possibility in the grid of a PMOS device 1202.Add transient control, i.e. second timing circuit 1206, and be connected to the control line identical with ESD switch 1202.Second timing circuit 1206 is a kind of preferred implementations of the power sense circuit 506 of Fig. 5.Use this circuit that many advantages are arranged.At first, second timing circuit 1206 can carry out tuning to the time constant different with first timing circuit 1204.Secondly, in other words the different place that the connection of second timing circuit 1206 can be on Vdd line 406, can have big bus resistance Rbus 1208 as shown in the figure between two timing circuits.This has been avoided because the triggering of the ESD clamp circuit PMOS 1002 that the local noise incident causes.When normal operation period is switched on, there is not esd event, second timing circuit will detect the high voltage in the Vdd line 406 and will remember to switch on.Then, this second timing circuit 1206 will turn-off or forbid the PMOS device 1202 in first timing circuit 1204, and this PMOS device 1202 will be to the ESD clamp circuit, and PMOS 1002, and triggering signal is provided.When outage, in the esd event process, the voltage at Vdd line 406 places is 0 volt, and second timing circuit 1206 can not detect this 0 volt in the Vdd line 406.Therefore, first timing circuit 1204 will detect this esd event, and with conducting the one PMOS device 1202, so that to the ESD clamp circuit, promptly PMOS 1002, and triggering signal is provided.Note that cut-off switch also can preferably add in second timing circuit, and the cut-off switch that the control of this cut-off switch will be similar in first timing circuit is used.

Of the present invention functional in order to prove, the circuit of the above Figure 12 has been carried out some simulations.Figure 12 A shows in the explanation power up or the chart of the voltage behavior of the circuit of Figure 12 under the on-state.Therefore, when switching in normal course of operation, promptly Vdd voltage is applied to IC, ESD device then, and promptly a PMOS 1202 rests on off state.This means the current potential at a PMOS 1202 grid places must be as far as possible near the current potential of power line.Therefore, in adding electric process, this grid potential must change with Vdd circuit 406.If the difference between two voltage becomes too big, then a PMOS 1202 begins to conduct some electric currents.In the drawings, dotted line is represented the current potential on the Vdd line 406.Dashed curve is represented simulation behavior of the present invention.Solid line is represented the simulation behavior of traditional prior art power supply clamp.Solid line and dotted line are presented at and add the voltage that is sent to ESD clamp circuit (being PMOS1002 in this example) in the electric process.Very clear, grid of the present invention, i.e. dotted line changes with the behavior as the power supply of dotted line (Vdd line).Voltage on PMOS 1002 source electrodes and the grid will be very little, thereby keep PMOS 1002 to be in off state.If we see the conventional method of solid line as, this voltage is no longer little.This will be in normal course of operation (in this simulation is to power up) conducting PMOS.

Figure 12 B shows the chart that explanation adds Figure 12 circuital current behavior in the electric process.Resemble that you can see, shown by dashed lines, by power supply clamp of the present invention (promptly, the entire circuit of Figure 12 comprises PMOS 1002, first timing circuit 1204 and second timing circuit 1206) electric current in adding electric process than much smaller by the electric current of the old technology of utilization shown in the solid line.

Figure 13 shows the circuit diagram explanation 1300 of the power supply anti-noise active clamping circuir of the minimum voltage control with cut-off switch.Except second timing circuit, Figure 13 and Figure 12 are similar.Figure 13 comprises the V-detector (voltage detector) 1302 that detects Vdd 406 states (on/off) in the voltage domain, and the state (off/on) of Vdd 406 in second timing circuit territory detection time of Figure 12.V-detector 1302 detects the magnitude of voltage at Vdd line 406 places, if this value is higher than specific value, then capacitor 1008 connections and a PMOS device 1202 can conductings.If the voltage at Vdd line 406 places is lower than this specific value, then capacitor 1008 disconnections and a PMOS 1202 can keep turn-offing.If might Vdd line 406 be lower than specific value capacitor 1008 disconnect then capacitor 1008 connects that Vdd circuits 406 are higher than specific value if should be pointed out that also.This value can be for example greater than the value of normal operation power supply, thereby makes and can avoid erroneous trigger in normal course of operation.

Figure 14 shows the circuit diagram explanation 1400 of block diagram of the power protection clamp circuit of Fig. 5.Particularly, Figure 14 shows the circuit diagram explanation of the power supply anti-noise active clamping circuir with the control of cut-off switch maximum voltage.If the Vdd voltage of HV territory 406a surpasses specific value, cut-off switch then, a PMOS 1202 will turn-off.This value is lower than normal operation supply voltage.This has stoped the triggering in the normal course of operation once more.Should be pointed out that in this case, the ESD clamp circuit, promptly PMOS 1002, must be in the voltage triggered that is lower than selected cut-off switch off voltage.Although this sounds and create ESD clamp circuit 1002 so that not trigger at high voltage be contradiction, this is a process useful of being avoided lockout issue, and esd protection still can produce simultaneously.Because the grid of a PMOS 1202 must be higher than its source electrode (promptly, Vdd406a " and Vss 406b " between the source electrode of a PMOS 1202), to disconnect capacitor C 1008, so gate driver circuit must comprise the device that has than in the low voltage domain of high power supply voltage.Therefore, when in the illustrated same chip of Figure 14, having two voltage domains, simple solution is arranged.Vdd 406a in the low voltage domain " and Vss406b " between the clamping voltage of PMOS device 1002 must be lower than the switched voltage of first inverter 1402 in the HV territory.If clamping voltage is higher than switched voltage, Vdd 406a then " and Vss 406b " between the core circuit (not shown) will obtain most of electric current because it is the most low-resistance path.If clamping voltage is lower than switched voltage, ESD clamp circuit then, promptly PMOS 1002, will obtain most of electric current and prevent the puncture of core circuit (not shown).In addition, as shown in figure 14, second inverter 1404 is with the Vdd 406a of LV " be coupled to control line 410.Therefore, as Vdd 406a " when being in low-voltage or 0 volt, first inverter 1402 will convert it to high voltage, be input to second inverter 1404.Second inverter 1404 is changed back low-voltage with high voltage now, and this will make a PMOS 1202 trigger the ESD clamp circuit, and promptly PMOS 1002.But, as Vdd 406b " and when being in high voltage, first inverter 1402 will convert it to low-voltage, be input to second inverter 1404.Second inverter 1404 returns low voltage transition to high voltage now, and this will make a PMOS 1202 forbidding ESD clamp circuit, i.e. PMOS1002.

Because ESD comprises high electric current, therefore might create the cut-off switch that needs high electric current to open.The cut-off switch (not shown) that the high electric current of this needs is opened can preferably add among Figure 14, combines with voltage controlled disconnection switch.

In addition, implementation shown in Figure 14 for example can be preferably incorporated in adds RC time circuit (not shown) in the HV territory, so that postpone the switching of first inverter.

Figure 15 shows the power supply anti-noise active clamping circuir 1500 that the state that utilizes another voltage domain is controlled cut-off switch.In the figure of this simplification, suppose that the power supply from low voltage domain can drive the HV PMOS of off state.If power supply clamp 1500 realizes that in the LV territory then the current potential Vdd 406 ' from the HV territory can be used for disconnecting capacitor 1008 when two power supplys are all connected.HV the one PMOS device 1202 is preferably used for preventing because the too high gate problems generation that causes of grid voltage on the PMOS device 1202.If power supply clamp 1500 realizes in the HV territory, then from the current potential Vdd 406 in LV territory " can be used for when two power supplys are all connected, disconnecting capacitor 1008.HV the one PMOS device 1202 is preferably used for preventing because the gate problems that overtension causes on the drain and gate on the PMOS device 1202 takes place.

Illustrate and made detailed description at this although combine the various execution modes of the present invention instruction, those skilled in the art are easy to design many other the different execution modes that still comprise these instructions not deviating under the situation of purport of the present invention and scope.

Claims (21)

1, a kind of esd protection circuit comprises:

The ESD clamp circuit;

Be coupled to the circuits for triggering of described clamp circuit, wherein said clamp circuit and described circuits for triggering are coupled to first reference potential; And

Be coupled to the control line of described circuits for triggering; Described control line is coupled to second reference potential;

Wherein when electricity was provided to described second reference potential, control line was forbidden described circuits for triggering, and when electricity was not provided to described second reference potential, control line enabled circuits for triggering.

2, esd protection circuit as claimed in claim 1, wherein first reference potential is coupled to second reference potential.

3, esd protection circuit as claimed in claim 1, wherein control line is coupled to second reference potential by power sense circuit.

4, esd protection circuit as claimed in claim 1, wherein said ESD clamp circuit comprise at least a in SCR, MOS transistor, bipolar transistor and the diode.

5, esd protection circuit as claimed in claim 1, wherein said circuits for triggering comprise logic sum gate and inverter, described logic sum gate has input and output, the input that its output feeds back to described input and enters inverter.

6, esd protection circuit as claimed in claim 5, the ESD clamp circuit is coupled in the output of wherein said inverter, so that do not provide triggering signal to described clamp circuit when the neutralization of ESD process has electricity to be provided to first reference potential.

7, esd protection circuit as claimed in claim 5 also comprises the capacitor that is coupled to the inverter input.

8, esd protection circuit as claimed in claim 3, wherein said power sense circuit comprises at least one impedance.

9, esd protection circuit as claimed in claim 8, wherein said impedance comprises resistor.

10, esd protection circuit as claimed in claim 1, wherein said circuits for triggering comprise impedance circuit.

11, esd protection circuit as claimed in claim 10, wherein said impedance circuit comprises resistor.

12, esd protection circuit as claimed in claim 10, wherein said impedance circuit comprises being connected in series of resistor, capacitor and switch.

13, esd protection circuit as claimed in claim 12, wherein switch is coupled to control line.

14, esd protection circuit as claimed in claim 12, wherein switch is the MOS device.

15, esd protection circuit as claimed in claim 14; the wherein source electrode of MOS device and drain electrode and resistor and capacitors in series coupling; so that form first timing circuit; the described gate coupled of described MOS device is to control line, and resistor, capacitor are coupled to the ESD clamp circuit with being connected of switch.

16, esd protection circuit as claimed in claim 15, wherein switch comprises SCR.

17, esd protection circuit as claimed in claim 1 also comprises second timing circuit that is coupled to control line and is coupled to second reference potential.

18, esd protection circuit as claimed in claim 17, wherein said second timing circuit comprises resistor and the capacitor that is connected in series.

19, esd protection circuit as claimed in claim 17, wherein said second timing circuit comprises resistor and the voltage detector that is connected in series.

20, esd protection circuit as claimed in claim 1; wherein said circuits for triggering comprise at least one MOS device; if and the voltage at control line place is lower than the threshold voltage of described MOS device then control line forbidding circuits for triggering, then control line enables circuits for triggering when this voltage is higher than described threshold voltage.

21, esd protection circuit as claimed in claim 3, wherein said power sense circuit comprises at least one inverter, the input of described inverter is connected to first reference potential.

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