CN104638622A - Electrostatic discharge protection circuit - Google Patents

Electrostatic discharge protection circuit Download PDF

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Publication number
CN104638622A
CN104638622A CN201310565459.1A CN201310565459A CN104638622A CN 104638622 A CN104638622 A CN 104638622A CN 201310565459 A CN201310565459 A CN 201310565459A CN 104638622 A CN104638622 A CN 104638622A
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CN
China
Prior art keywords
unit
coupled
switch
protection circuit
driver
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Application number
CN201310565459.1A
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Chinese (zh)
Inventor
曹太和
颜承正
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瑞昱半导体股份有限公司
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Priority to CN201310565459.1A priority Critical patent/CN104638622A/en
Publication of CN104638622A publication Critical patent/CN104638622A/en

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Abstract

The invention provides an ESD (electrostatic discharge) protection circuit. The ESD protection circuit comprises a clamping unit, a driving unit, a resistance unit, a switch unit and a capacitance unit. The clamping unit is coupled between a first power source and a second power source; the driving unit is coupled between the clamping unit and a reference node; the resistance unit is coupled between the first power source and the reference node; the switch unit is coupled to the driving unit through the reference node; the capacitance unit is coupled between the switch unit and the second power source. Under a normal operation condition, the driving unit controls the switch unit to be in an off state; under an ESD condition, the driving unit controls the switch unit to be in an on state.

Description

ESD protection circuit

Technical field

The present invention relates to a kind of ESD protection circuit, relate to the ESD protection circuit can eliminating grid leakage current particularly.

Background technology

Please refer to Fig. 1; it is the schematic block diagram of the simplification of a traditional ESD protection circuit 100; wherein ESD protection circuit 100 is one based on the ESD (Electrostatic Discharge) clamp circuit (RC-based power-rail ESD clamp circuit) of the conductor rail of resistance capacitance; ESD protection circuit 100 comprises: strangulation unit 102, driver element 104, resistance unit 106 and a capacitor cell 110; wherein strangulation unit 102 is a N-type metal oxide semiconductor transistor (NMOS), and driver element 104 is an inverter.Under a normal circuit operation condition, the input of this inverter is high-voltage level, and therefore, the output of this inverter is low voltage level, and strangulation unit 102(that is this NMOS) be closed.In addition, under a static discharge condition, due to the delay that resistance unit 106 and capacitor cell 120 cause, the input of this inverter has just started to have the low voltage level lower relative to the first power vd D.Therefore, the output of this inverter can produce a high-voltage level, starts strangulation unit 102(that is this NMOS whereby), the low impedance path between providing from the first power vd D to second source VSS, to get rid of ESD electric current.In addition; please refer to Fig. 2; it is the schematic block diagram of the simplification of another traditional ESD protection circuit 200; wherein ESD protection circuit 200 is one based on the ESD (Electrostatic Discharge) clamp circuit (CR-based power-rail ESD clamp circuit) of capacitance-resistance conductor rail; ESD protection circuit 200 comprises: strangulation unit 202, driver element 204, resistance unit 206 and a capacitor cell 220; wherein strangulation unit 202 is a P-type mos transistor (PMOS), and driver element 204 is an inverter.Under a normal circuit operation condition, the input of this inverter is low voltage level, and therefore, the output of this inverter is high-voltage level, and strangulation unit 202(that is this PMOS) be closed.In addition, under a static discharge condition, due to the delay that resistance unit 206 and capacitor cell 220 cause, the input of this inverter has just started to have the high-voltage level higher relative to second source VSS.Therefore, the output of this inverter can produce a low voltage level, starts strangulation unit 202(that is this PMOS whereby), the low impedance path between providing from the first power vd D to second source VSS, to get rid of ESD electric current.

But, in the CMOS technology technology of advanced person, although use the area shared by MOS capacitor of thinner gate oxidation layer process less, but thinner grid oxic horizon can cause larger electric leakage of the grid flow valuve, therefore, when above-mentioned traditional ESD protection circuit 100 and the capacitor cell 110 in ESD protection circuit 200, 210 for having the MOS capacitor of thin gate oxide time, capacitor cell 110, the 210 larger grid leakage currents produced cause above-mentioned traditional ESD protection circuit 100 cannot normal operation with other circuit in ESD protection circuit 200 or chip possibly.

Summary of the invention

In view of this, main purpose of the present invention is to provide a kind of ESD protection circuit, and it can reduce or eliminate the grid leakage current of capacitor cell, and the problem avoiding grid leakage current to cause.

According to claim of the present invention, which disclose a kind of ESD protection circuit, this ESD protection circuit comprises: a strangulation unit, a driver element, a resistance unit, a switch element and a capacitor cell.This strangulation unit is coupled between one first power supply and a second source; This driver element is coupled between this strangulation unit and a reference node; This resistance unit is coupled between this first power supply and this reference node; This switch element is coupled to this driver element via this reference node; And this capacitor cell is coupled between this switch element and this second source; Wherein under a normal operating condition, this driver element controls the state that this switch element is in not conducting, and under a static discharge condition, this driver element controls the state that this switch element is in conducting.

According to claim of the present invention, which disclose a kind of ESD protection circuit, this ESD protection circuit comprises: a strangulation unit, a driver element, a resistance unit, a switch element and a capacitor cell.This strangulation unit is coupled between one first power supply and a second source; This driver element is coupled between this strangulation unit and a reference node; This resistance unit is coupled between this first power supply and this reference node; This switch element is coupled to this driver element; And this capacitor cell is coupled between this switch element and this second source; Wherein this switch element is coupled between this resistance unit and this capacitor cell, and under a normal operating condition, this driver element controls the state that this switch element is in not conducting, and under a static discharge condition, this driver element controls this switch element and is in conducting state.

In sum; compared with prior art; ESD protection circuit disclosed by the present invention can control the state that this switch element is in not conducting in normal operation condition; to make this capacitor cell not have electric current process, so the problem that the present invention can avoid grid leakage current to cause.

Accompanying drawing explanation

Illustrated in fig. 1 is the schematic block diagram of the simplification of a traditional ESD protection circuit.

Illustrated in fig. 2 is the schematic block diagram of the simplification of another traditional ESD protection circuit.

Illustrated in fig. 3 is the schematic block diagram of the simplification of ESD protection circuit according to one first embodiment of the present invention.

Illustrated in fig. 4 is the schematic block diagram of the simplification of ESD protection circuit according to one second embodiment of the present invention.

Illustrated in fig. 5 is the schematic block diagram of the simplification of ESD protection circuit according to of the present invention 1 the 3rd embodiment.

Illustrated in fig. 6 is the schematic block diagram of the simplification of ESD protection circuit according to of the present invention 1 the 4th embodiment.

Illustrated in fig. 7 is the schematic block diagram of the simplification of ESD protection circuit according to of the present invention 1 the 5th embodiment.

Illustrated in fig. 8 is the schematic block diagram of the simplification of ESD protection circuit according to of the present invention 1 the 6th embodiment.

Illustrated in fig. 9 is the schematic block diagram of the simplification of ESD protection circuit according to of the present invention 1 the 7th embodiment.

Illustrated in fig. 10 is the schematic block diagram of the simplification of ESD protection circuit according to of the present invention 1 the 8th embodiment.

Illustrated in fig. 11 is the schematic block diagram of the simplification of ESD protection circuit according to of the present invention 1 the 9th embodiment.

Illustrated in fig. 12 is the schematic block diagram of the simplification of ESD protection circuit according to of the present invention 1 the tenth embodiment.

[the symbol simple declaration of figure]:

300: electrostatic storage deflection (ESD) protection circuit

302: strangulation unit

304: driver element

306: resistance unit

308: switch element

310: capacitor cell

A: reference point

Embodiment

Please refer to Fig. 3; it is the schematic block diagram of the simplification of ESD protection circuit 300 according to one first embodiment of the present invention; wherein ESD protection circuit 300 is one based on the ESD (Electrostatic Discharge) clamp circuit (RC-based power-rail ESD clamp circuit) of the conductor rail of resistance capacitance, and ESD protection circuit 300 comprises: strangulation unit 302, driver element 304, resistance unit 306, switch element 308 and a capacitor cell 310.Strangulation unit 302 is coupled between one first power vd D and a second source VSS, and driver element 304 is coupled between strangulation unit 302 and a reference node A, and wherein driver element 304 can comprise multiple rp unit.Resistance unit 306 is coupled between the first power vd D and reference node A, and switch element 308 is coupled to driver element 304 via reference node A, wherein switch element 308 can be a N-type metal oxide semiconductor transistor (NMOS), a P-type mos transistor (PMOS) or a transmission gate (transmission gate).Capacitor cell 310 is coupled between switch element 308 and second source VSS, and wherein capacitor cell 310 can be a MOS capacitor with thin gate oxide.Wherein, preferably, switch element 308 is coupled between resistance unit 306 and capacitor cell 310.Wherein, under a normal operating condition, driver element 304 meeting control switch unit 308 is in the state of not conducting, do not have electric current to make capacitor cell 310 to pass through, so the present invention can reduce or eliminate the grid leakage current of capacitor cell 310, and problem avoiding grid leakage current to cause.In addition, under a static discharge condition, driver element 304 control switch unit 308 is in the state of conducting, has normal electrostatic discharge protection to make ESD protection circuit 300.

In addition, please note at this, the above embodiments only illustrate as of the present invention, instead of restrictive condition of the present invention, for example, please refer to Fig. 4, it is the schematic block diagram of the simplification of ESD protection circuit 400 according to one second embodiment of the present invention, wherein ESD protection circuit 400 is one based on the ESD (Electrostatic Discharge) clamp circuit (RC-based power-rail ESD clamp circuit) of the conductor rail of resistance capacitance, ESD protection circuit 400 comprises: a strangulation unit 402, one driver element 404, one resistance unit 406, one switch element 408, one capacitor cell 410 and two buffer cells 412, 414.

Please refer to Fig. 5; it is the schematic block diagram of the simplification of ESD protection circuit 500 according to of the present invention 1 the 3rd embodiment; wherein ESD protection circuit 500 is one based on the ESD (Electrostatic Discharge) clamp circuit (RC-based power-rail ESD clamp circuit) of the conductor rail of resistance capacitance, and ESD protection circuit 500 comprises: strangulation unit 502, driver element 504, resistance unit 506, switch element 508 and a capacitor cell 510.Strangulation unit 502 is coupled between one first power vd D and a second source VSS, wherein strangulation unit 502 is a N-type metal oxide semiconductor transistor (NMOS), and driver element 504 is coupled between strangulation unit 502 and a reference node A, and wherein driver element 504 comprises 3 rp units 512,514,516.Resistance unit 506 is coupled between the first power vd D and reference node A, and switch element 508 is coupled to driver element 504 via reference node A, wherein switch element 508 is a N-type metal oxide semiconductor transistor (NMOS), and the grid of this NMOS is coupled to the output of rp unit 512, the drain electrode of this NMOS is coupled to reference node A, and the source electrode of this NMOS is coupled to capacitor cell 510.Capacitor cell 510 is coupled between switch element 508 and second source VSS, and wherein capacitor cell 510 can be a MOS capacitor with thin gate oxide.Wherein, under a normal operating condition, the input of reference node A(that is rp unit 516) be a high-voltage level, therefore, the output of rp unit 512 can produce a low voltage level, so switch element 508(that is this NMOS) and strangulation unit 502(that is this NMOS) all can be closed respectively.In other words, under this normal operating condition, driver element 504 meeting control switch unit 508 is in the state of not conducting, do not have electric current to make capacitor cell 510 to pass through, so the present invention can reduce or eliminate the grid leakage current of capacitor cell 510, and problem avoiding grid leakage current to cause.In addition, under a static discharge condition, the input of reference node A(that is rp unit 516) just start to have the low voltage level relative to the first power vd D.Therefore, the output of rp unit 512 can produce a high-voltage level, respectively starting switch unit 508(that is this NMOS whereby) and strangulation unit 502(that is this NMOS), the low impedance path between providing from the first power vd D to second source VSS, to get rid of ESD electric current.In other words; under this static discharge condition; driver element 504 control switch unit 508 is in the state (namely switch element 508 can trigger the state into conducting because of static discharge) of conducting, has normal electrostatic discharge protection to make ESD protection circuit 500.In addition, note that the above embodiments only illustrate as of the present invention at this, instead of restrictive condition of the present invention, for example, the quantity of rp unit can change according to the demand of different circuit design.

Please refer to Fig. 6; it is the schematic block diagram of the simplification of ESD protection circuit 600 according to of the present invention 1 the 4th embodiment; wherein ESD protection circuit 600 is one based on the ESD (Electrostatic Discharge) clamp circuit (RC-based power-rail ESD clamp circuit) of the conductor rail of resistance capacitance, and ESD protection circuit 600 comprises: strangulation unit 602, driver element 604, resistance unit 606, switch element 608 and a capacitor cell 610.Strangulation unit 602 is coupled between one first power vd D and a second source VSS, wherein strangulation unit 602 is a N-type metal oxide semiconductor transistor (NMOS), and driver element 604 is coupled between strangulation unit 602 and a reference node A, and wherein driver element 604 comprises 3 rp units 612,614,616.Resistance unit 606 is coupled between the first power vd D and reference node A, and switch element 608 is coupled to driver element 604 via reference node A, wherein switch element 608 is a P-type mos transistor (PMOS), and the grid of this PMOS is coupled to the output of rp unit 614, the source electrode of this PMOS is coupled to reference node A, and the drain electrode of this PMOS is coupled to capacitor cell 610.Capacitor cell 610 is coupled between switch element 608 and second source VSS, and wherein capacitor cell 610 can be a MOS capacitor with thin gate oxide.Wherein, under a normal operating condition, the input of reference node A(that is rp unit 616) be a high-voltage level, therefore, the output that the output of rp unit 614 can produce a high-voltage level and rp unit 612 can produce a low voltage level, so switch element 608(that is this PMOS) and strangulation unit 602(that is this NMOS) all can be closed respectively.In other words, under this normal operating condition, driver element 604 meeting control switch unit 608 is in the state of not conducting, do not have electric current to make capacitor cell 610 to pass through, so the present invention can reduce or eliminate the grid leakage current of capacitor cell 610, and problem avoiding grid leakage current to cause.In addition, under a static discharge condition, the input of reference node A(that is rp unit 616) just start to have the low voltage level relative to the first power vd D.Therefore, the output that the output of rp unit 614 can produce a low voltage level and rp unit 612 can produce a high-voltage level, respectively starting switch unit 608(that is this PMOS whereby) and strangulation unit 602(that is this NMOS), low impedance path between providing from the first power vd D to second source VSS, to get rid of ESD electric current.In other words; under this static discharge condition; driver element 604 control switch unit 608 is in the state (namely switch element 608 can trigger the state into conducting because of static discharge) of conducting, has normal electrostatic discharge protection to make ESD protection circuit 600.In addition, note that the above embodiments only illustrate as of the present invention at this, instead of restrictive condition of the present invention, for example, the quantity of rp unit can change according to the demand of different circuit design.

Please refer to Fig. 7, it is the schematic block diagram of the simplification of ESD protection circuit 700 according to of the present invention 1 the 5th embodiment, wherein ESD protection circuit 700 is one based on the ESD (Electrostatic Discharge) clamp circuit (RC-based power-rail ESD clamp circuit) of the conductor rail of resistance capacitance, wherein ESD protection circuit 700 is one based on the ESD (Electrostatic Discharge) clamp circuit (RC-based power-rail ESD clamp circuit) of the conductor rail of resistance capacitance, ESD protection circuit 700 comprises: a strangulation unit 702, one driver element 704, one resistance unit 706, one switch element 708 and a capacitor cell 710.Strangulation unit 702 is coupled between one first power vd D and a second source VSS, wherein strangulation unit 702 is a N-type metal oxide semiconductor transistor (NMOS), and driver element 704 is coupled between strangulation unit 702 and a reference node A, and wherein driver element 704 comprises 3 rp units 712,714,716.Resistance unit 706 is coupled between the first power vd D and reference node A, and switch element 708 is coupled to driver element 704 via reference node A, and wherein switch element 708 is a transmission gate (transmission gate).Capacitor cell 710 is coupled between switch element 708 and second source VSS, and wherein capacitor cell 710 can be a MOS capacitor with thin gate oxide.Wherein, under a normal operating condition, the input of reference node A(that is rp unit 716) be a high-voltage level, therefore, the output that the output of rp unit 714 can produce a high-voltage level and rp unit 712 can produce a low voltage level, so switch element 708(that is this transmission gate) and strangulation unit 702(that is this NMOS) all can be closed respectively.In other words, under this normal operating condition, driver element 704 meeting control switch unit 708 is in the state of not conducting, do not have electric current to make capacitor cell 710 to pass through, so the present invention can reduce or eliminate the grid leakage current of capacitor cell 710, and problem avoiding grid leakage current to cause.In addition, under a static discharge condition, the input of reference node A(that is rp unit 716) just start to have the low voltage level relative to the first power vd D.Therefore, the output that the output of rp unit 714 can produce a low voltage level and rp unit 712 can produce a high-voltage level, respectively starting switch unit 708(that is this transmission gate whereby) and strangulation unit 702(that is this NMOS), low impedance path between providing from the first power vd D to second source VSS, to get rid of ESD electric current.In other words; under this static discharge condition; driver element 704 control switch unit 708 is in the state (namely switch element 708 can trigger the state into conducting because of static discharge) of conducting, has normal electrostatic discharge protection to make ESD protection circuit 700.In addition, note that the above embodiments only illustrate as of the present invention at this, instead of restrictive condition of the present invention, for example, the quantity of rp unit can change according to the demand of different circuit design.

Please refer to Fig. 8; it is the schematic block diagram of the simplification of ESD protection circuit 800 according to of the present invention 1 the 6th embodiment; wherein ESD protection circuit 800 is one based on the ESD (Electrostatic Discharge) clamp circuit (CR-based power-rail ESD clamp circuit) of capacitance-resistance conductor rail, and ESD protection circuit 800 comprises: strangulation unit 802, driver element 804, resistance unit 806, switch element 808 and a capacitor cell 810.Strangulation unit 802 is coupled between one first power supply VSS and a second source VDD, and driver element 804 is coupled between strangulation unit 802 and a reference node A, and wherein driver element 804 can comprise multiple rp unit.Resistance unit 806 is coupled between the first power supply VSS and reference node A, and switch element 808 is coupled to driver element 804 via reference node A, wherein switch element 808 can be a N-type metal oxide semiconductor transistor (NMOS), a P-type mos transistor (PMOS) or a transmission gate (transmission gate).Capacitor cell 810 is coupled between switch element 808 and second source VDD, and wherein capacitor cell 810 can be a MOS capacitor with thin gate oxide.Wherein, under a normal operating condition, driver element 804 meeting control switch unit 808 is in the state of not conducting, do not have electric current to make capacitor cell 810 to pass through, so the present invention can reduce or eliminate the grid leakage current of capacitor cell 810, and problem avoiding grid leakage current to cause.In addition; under a static discharge condition; driver element 804 meeting control switch unit 808 is in the state (namely switch element 808 can trigger the state into conducting because of static discharge) of conducting, has normal electrostatic discharge protection to make ESD protection circuit 800.

In addition, please note at this, the above embodiments only illustrate as of the present invention, instead of restrictive condition of the present invention, for example, please refer to Fig. 9, it is the schematic block diagram of the simplification of ESD protection circuit 900 according to of the present invention 1 the 7th embodiment, wherein ESD protection circuit 900 is one based on the ESD (Electrostatic Discharge) clamp circuit (CR-based power-rail ESD clamp circuit) of capacitance-resistance conductor rail, ESD protection circuit 900 comprises: a strangulation unit 902, one driver element 909, one resistance unit 906, one switch element 908, one capacitor cell 910 and two buffer cells 912, 914.

Please refer to Figure 10; it is the schematic block diagram of the simplification of ESD protection circuit 1000 according to of the present invention 1 the 8th embodiment; wherein ESD protection circuit 1000 is one based on the ESD (Electrostatic Discharge) clamp circuit (CR-based power-rail ESD clamp circuit) of capacitance-resistance conductor rail, and ESD protection circuit 1000 comprises: strangulation unit 1002, driver element 1004, resistance unit 1006, switch element 1008 and a capacitor cell 1010.Strangulation unit 1002 is coupled between one first power supply VSS and a second source VDD, wherein strangulation unit 1002 is a P-type mos transistor (PMOS), and driver element 1004 is coupled between strangulation unit 1002 and a reference node A, and wherein driver element 1004 comprises 3 rp units 1012,1014,1016.Resistance unit 1006 is coupled between the first power supply VSS and reference node A, and switch element 1008 is coupled to driver element 1004 via reference node A, wherein switch element 1008 is a P-type mos transistor (PMOS), and the grid of this PMOS is coupled to the output of rp unit 1012, the source electrode of this PMOS is coupled to reference node A, and the drain electrode of this PMOS is coupled to capacitor cell 1010.Capacitor cell 1010 is coupled between switch element 1008 and second source VDD, and wherein capacitor cell 1010 can be a MOS capacitor with thin gate oxide.Wherein, under a normal operating condition, the input of reference node A(that is rp unit 1016) be a low voltage level, therefore, the output of rp unit 1012 can produce a high-voltage level, so switch element 1008(that is this PMOS) and strangulation unit 1002(that is this PMOS) all can be closed respectively.In other words, under this normal operating condition, driver element 1004 meeting control switch unit 1008 is in the state of not conducting, do not have electric current to make capacitor cell 1010 to pass through, so the present invention can reduce or eliminate the grid leakage current of capacitor cell 1010, and problem avoiding grid leakage current to cause.In addition, under a static discharge condition, the input of reference node A(that is rp unit 1016) just start to have the high-voltage level relative to the first power supply VSS.Therefore, the output of rp unit 1012 can produce a low voltage level, respectively starting switch unit 1008(that is this PMOS whereby) and strangulation unit 1002(that is this PMOS), provide from the low impedance path between second source VDD to the first power supply VSS, to get rid of ESD electric current.In other words; under this static discharge condition; driver element 1004 control switch unit 1008 is in the state (namely switch element 1008 can trigger the state into conducting because of static discharge) of conducting, has normal electrostatic discharge protection to make ESD protection circuit 1000.In addition, note that the above embodiments only illustrate as of the present invention at this, instead of restrictive condition of the present invention, for example, the quantity of rp unit can change according to the demand of different circuit design.

Please refer to Figure 11; it is the schematic block diagram of the simplification of ESD protection circuit 1100 according to of the present invention 1 the 9th embodiment; wherein ESD protection circuit 1100 is one based on the ESD (Electrostatic Discharge) clamp circuit (CR-based power-rail ESD clamp circuit) of capacitance-resistance conductor rail, and ESD protection circuit 1100 comprises: strangulation unit 1102, driver element 1104, resistance unit 1106, switch element 1108 and a capacitor cell 1110.Strangulation unit 1102 is coupled between one first power supply VSS and a second source VDD, wherein strangulation unit 1102 is a P-type mos transistor (PMOS), and driver element 1104 is coupled between strangulation unit 1102 and a reference node A, and wherein driver element 1104 comprises 3 rp units 1112,1114,1116.Resistance unit 1106 is coupled between the first power supply VSS and reference node A, and switch element 1108 is coupled to driver element 1104 via reference node A, wherein switch element 1108 is a N-type metal oxide semiconductor transistor (NMOS), and the grid of this NMOS is coupled to the output of rp unit 1114, the drain electrode of this NMOS is coupled to reference node A, and the source electrode of this NMOS is coupled to capacitor cell 1110.Capacitor cell 1110 is coupled between switch element 1108 and second source VDD, and wherein capacitor cell 1110 can be a MOS capacitor with thin gate oxide.Wherein, under a normal operating condition, the input of reference node A(that is rp unit 1116) be a low voltage level, therefore, the output that the output of rp unit 1114 can produce a low voltage level and rp unit 1112 can produce a high-voltage level, so switch element 1108(that is this NMOS) and strangulation unit 1102(that is this PMOS) all can be closed respectively.In other words, under this normal operating condition, driver element 1104 meeting control switch unit 1108 is in the state of not conducting, do not have electric current to make capacitor cell 1110 to pass through, so the present invention can reduce or eliminate the grid leakage current of capacitor cell 1110, and problem avoiding grid leakage current to cause.In addition, under a static discharge condition, the input of reference node A(that is rp unit 1116) just start to have the high-voltage level relative to the first power supply VSS.Therefore, the output that the output of rp unit 1114 can produce a high-voltage level and rp unit 1112 can produce a low voltage level, respectively starting switch unit 1108(that is this NMOS whereby) and strangulation unit 1102(that is this PMOS), there is provided from the low impedance path between second source VDD to the first power supply VSS, to get rid of ESD electric current.In other words; under this static discharge condition; driver element 1104 control switch unit 1108 is in the state (namely switch element 1108 can trigger the state into conducting because of static discharge) of conducting, has normal electrostatic discharge protection to make ESD protection circuit 1100.In addition, note that the above embodiments only illustrate as of the present invention at this, instead of restrictive condition of the present invention, for example, the quantity of rp unit can change according to the demand of different circuit design.

Please refer to Figure 12; it is the schematic block diagram of the simplification of ESD protection circuit 1200 according to of the present invention 1 the tenth embodiment; wherein ESD protection circuit 1200 is one based on the ESD (Electrostatic Discharge) clamp circuit (CR-based power-rail ESD clamp circuit) of capacitance-resistance conductor rail, and ESD protection circuit 1200 comprises: strangulation unit 1202, driver element 1204, resistance unit 1206, switch element 1208 and a capacitor cell 1210.Strangulation unit 1202 is coupled between one first power supply VSS and a second source VDD, wherein strangulation unit 1202 is a P-type mos transistor (PMOS), and driver element 1204 is coupled between strangulation unit 1202 and a reference node A, and wherein driver element 1204 comprises 3 rp units 1212,1214,1216.Resistance unit 1206 is coupled between the first power supply VSS and reference node A, and switch element 1208 is coupled to driver element 1204 via reference node A, and wherein switch element 1208 is a transmission gate (transmission gate).Capacitor cell 1210 is coupled between switch element 1208 and second source VDD, and wherein capacitor cell 1210 can be a MOS capacitor with thin gate oxide.Wherein, under a normal operating condition, the input of reference node A(that is rp unit 1216) be a low voltage level, therefore, the output that the output of rp unit 1214 can produce a low voltage level and rp unit 1212 can produce a high-voltage level, so switch element 1208(that is this transmission gate) and strangulation unit 1202(that is this PMOS) all can be closed respectively.In other words, under this normal operating condition, driver element 1204 meeting control switch unit 1208 is in the state of not conducting, do not have electric current to make capacitor cell 1210 to pass through, so the present invention can reduce or eliminate the grid leakage current of capacitor cell 1210, and problem avoiding grid leakage current to cause.In addition, under a static discharge condition, the input of reference node A(that is rp unit 1216) just start to have the high-voltage level relative to the first power supply VSS.Therefore, the output that the output of rp unit 1214 can produce a high-voltage level and rp unit 1212 can produce a low voltage level, respectively starting switch unit 1208(that is this transmission gate whereby) and strangulation unit 1202(that is this PMOS), there is provided from the low impedance path between second source VDD to the first power supply VSS, to get rid of ESD electric current.In other words; under this static discharge condition; driver element 1204 control switch unit 1208 is in the state (namely switch element 1208 can trigger the state into conducting because of static discharge) of conducting, has normal electrostatic discharge protection to make ESD protection circuit 1200.In addition, note that the above embodiments only illustrate as of the present invention at this, instead of restrictive condition of the present invention, for example, the quantity of rp unit can change according to the demand of different circuit design.

In sum; compared with prior art; ESD protection circuit disclosed by the present invention can control the state that this switch element is in not conducting in normal operation condition; do not have electric current to make this capacitor cell to pass through; so the present invention can reduce or eliminate the grid leakage current of capacitor cell, and grid leakage current is avoided to cause the problem of ESD protection circuit.

The foregoing is only preferred embodiment of the present invention, every equalization done according to claim of the present invention changes and modifies, and all should belong to covering scope of the present invention.

[symbol description]

100,200: ESD protection circuit

102,202: strangulation unit

104,204: driver element

106,206: resistance unit

110,210: capacitor cell

300,400,500,600,700,800,900,1000,1100,1200: ESD protection circuit

302,402,502,602,702,802,902,1002,1102,1202: strangulation unit

304,404,504,604,704,804,904,1004,1104,1204: driver element

306,406,506,606,706,806,906,1006,1106,1206: resistance unit

308,408,508,608,708,808,908,1008,1108,1208: switch element

310,410,510,610,710,810,910,1010,1110,1210: capacitor cell

412,414,912,914: buffer cell

512,514,516,612,614,616,712,714,716,1012,1014,1016,1112,1114,1116,1212,1214,1216: rp unit

A: reference node.

Claims (10)

1. an ESD protection circuit, comprising:
One strangulation unit, is coupled between one first power supply and a second source;
One driver element, is coupled between described strangulation unit and a reference node;
One resistance unit, is coupled between described first power supply and described reference node;
One switch element, is coupled to described driver element via described reference node; And
One capacitor cell, is coupled between described switch element and described second source;
Wherein under a normal operating condition, described driver element controls the state that described switch element is in not conducting, and under a static discharge condition, described driver element controls described switch element and is in conducting state.
2. ESD protection circuit according to claim 1, also comprises:
At least one buffer cell, is coupled between described switch element and described driver element.
3. ESD protection circuit according to claim 1, wherein said driver element comprises:
Multiple rp unit, is coupled between described switch element and described strangulation unit.
4. ESD protection circuit according to claim 1, wherein said switch element is a N-type metal oxide semiconductor transistor (NMOS), P-type mos transistor (PMOS) or a transmission gate.
5. ESD protection circuit according to claim 1, wherein said capacitor cell is a MOS capacitor with thin gate oxide.
6. ESD protection circuit according to claim 1, the voltage of wherein said first power supply is greater than the voltage of described second source, and described ESD protection circuit is one based on the ESD (Electrostatic Discharge) clamp circuit of the conductor rail of resistance capacitance.
7. ESD protection circuit according to claim 6, wherein said strangulation unit is a N-type metal oxide semiconductor transistor (NMOS).
8. ESD protection circuit according to claim 1, the voltage of wherein said second source is greater than the voltage of described first power supply, and described ESD protection circuit is one based on the ESD (Electrostatic Discharge) clamp circuit of capacitance-resistance conductor rail.
9. ESD protection circuit according to claim 8, wherein said strangulation unit is a P-type mos transistor (PMOS).
10. an ESD protection circuit, comprising:
One strangulation unit, is coupled between one first power supply and a second source;
One driver element, is coupled between described strangulation unit and a reference node;
One resistance unit, is coupled between described first power supply and described reference node;
One switch element, is coupled to described driver element; And
One capacitor cell, is coupled between described switch element and described second source;
Wherein said switch element is coupled between described resistance unit and described capacitor cell, and under a normal operating condition, described driver element controls the state that described switch element is in not conducting, and under a static discharge condition, described driver element controls described switch element and is in conducting state.
CN201310565459.1A 2013-11-13 2013-11-13 Electrostatic discharge protection circuit CN104638622A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105045008A (en) * 2015-08-20 2015-11-11 深圳市华星光电技术有限公司 ESD protection circuit of liquid crystal display panel

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101421896A (en) * 2006-04-21 2009-04-29 沙诺夫公司 ESD clamp control by detection of power state
TW201104827A (en) * 2009-07-31 2011-02-01 Univ Nat Sun Yat Sen Electrostatic discharge protecting circuit with ultra-low standby leakage current for twice supply voltage tolerance
US20110043953A1 (en) * 2009-08-18 2011-02-24 Ming-Dou Ker Esd protection circuit with merged triggering mechanism
CN102222892A (en) * 2011-06-14 2011-10-19 北京大学 Low-leakage type power supply clamping ESD (electronic static discharge) protection circuit
CN102882198A (en) * 2011-07-15 2013-01-16 台湾积体电路制造股份有限公司 Rc triggered ESD protection device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101421896A (en) * 2006-04-21 2009-04-29 沙诺夫公司 ESD clamp control by detection of power state
TW201104827A (en) * 2009-07-31 2011-02-01 Univ Nat Sun Yat Sen Electrostatic discharge protecting circuit with ultra-low standby leakage current for twice supply voltage tolerance
US20110043953A1 (en) * 2009-08-18 2011-02-24 Ming-Dou Ker Esd protection circuit with merged triggering mechanism
CN102222892A (en) * 2011-06-14 2011-10-19 北京大学 Low-leakage type power supply clamping ESD (electronic static discharge) protection circuit
CN102882198A (en) * 2011-07-15 2013-01-16 台湾积体电路制造股份有限公司 Rc triggered ESD protection device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105045008A (en) * 2015-08-20 2015-11-11 深圳市华星光电技术有限公司 ESD protection circuit of liquid crystal display panel

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Application publication date: 20150520