CN1658388A - Electrostatic discharge protection circuit - Google Patents

Electrostatic discharge protection circuit Download PDF

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Publication number
CN1658388A
CN1658388A CN 200410057254 CN200410057254A CN1658388A CN 1658388 A CN1658388 A CN 1658388A CN 200410057254 CN200410057254 CN 200410057254 CN 200410057254 A CN200410057254 A CN 200410057254A CN 1658388 A CN1658388 A CN 1658388A
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China
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channel mos
effect transistor
protection circuit
nmos
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CN 200410057254
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Chinese (zh)
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CN100390987C (en
Inventor
齐藤则章
桥本贤治
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富士通株式会社
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Priority to JP2004041775A priority Critical patent/JP2005235947A/en
Priority to JP041775/2004 priority
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Publication of CN1658388A publication Critical patent/CN1658388A/en
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Publication of CN100390987C publication Critical patent/CN100390987C/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Abstract

A space-saving electrostatic discharge protection circuit that protects an internal circuit effectively against an ESD. When a positive ESD voltage is applied to a power supply terminal VDD, a PMOS is in the on state for time determined by a time constant given by a first resistor and a capacitor and the voltage of a gate of an NMOS rises due to voltage generated across a second resistor. As a result, the potential of a substrate is raised, a parasitic bipolar transistor on the NMOS turns on at a low drain voltage, an electric current generated by the ESD flows to a power supply terminal VSS via a power supply line, and the internal circuit is protected.

Description

ESD protection circuit

Technical field

The present invention relates to ESD protection circuit, more particularly, relate to a kind of ESD protection circuit of protecting internal circuit to avoid electrostatic discharge effect.

Background technology

The small semiconductor device, for example large scale integrated circuit (LSI) may be because of discharging from the external static electrification lotus, thereby cause decreased performance or fault.

Therefore, LSI has comprised ESD protection circuit (esd protection circuit), and this circuit can be protected internal circuit, makes it avoid acting on the influence of the Electrostatic Discharge voltage of power end or signal input-output end.

Fig. 8 is the circuit diagram of traditional E SD protective circuit.

Esd protection circuit 800 comprises power supply clamper part 810 and grid voltage control section 820; wherein; described power supply clamper part 810 comprises a n NMOS N-channel MOS N (MOS) field-effect transistor (NMOS) 811; be used to prevent that ESD voltage from acting on internal circuit 900, and described grid voltage control section 820 is used for controlling the grid voltage of the NMOS811 that is included in described power supply clamper part 810.

Power supply clamper part 810 comprises NMOS 811, its be connected electrically in the power line 901 that links to each other with power end VDD and with power line 902 that power end VSS links to each other between.The input-output end of NMOS 811 (drain electrode or source electrode) links to each other with power line 901 via resistance 812, and another input-output end of NMOS811 links to each other with power line 902.In Fig. 8, with dashed lines schematically shows parasitic bipolar transistor 811a, dead resistance 811b and the parasitic diode 811c on the NMOS 811.

For example, positive dc voltage is acted on power end VDD, and power end VSS links to each other with ground (GND).

Grid voltage control section 820 has a complementary MOS (CMOS) inverter structure, and comprises p channel MOS field-effect transistor (PMOS) 821 and NMOS 822.The input-output end of PMOS 821 links to each other with power line 901, and another input-output end of PMOS 821 then links to each other with the input-output end of NMOS 811 and the gate terminal that is included in the NMOS 811 in the power supply clamper part 810.Input-output end of NMOS 822 and described another input-output end of PMOS 821 and the gate terminal that is included in the NMOS 811 in the power supply clamper part 810 link to each other, and another input-output end of NMOS 822 links to each other with power line 902.The gate terminal of PMOS821 and NMOS 822 all links to each other with power line 901.

Next the operation of traditional E SD protective circuit 800 is described.

Suppose that with power end VSS be benchmark (GND), positive dc voltage is acted on power end VDD.So in grid voltage control section 820, PMOS 821 disconnects and NMOS 822 conductings.As a result, the gate terminal of the NMOS 811 in the power supply clamper part 810 just is electrically connected to power line 902, and NMOS 811 disconnects.Thus, the positive dc voltage that acts on power end VDD will be provided for internal circuit 900, and internal circuit 900 can be carried out predetermined operation.

When a positive ESD voltage is benchmark when being applied to power end VDD with power end VSS (GND), in the depletion layer in the n of NMOS 811 type drain junction district, avalanche breakdown will take place.As a result, the electromotive force of substrate will rise.When the base stage of parasitic bipolar transistor 811a and the electrical potential difference between the emitter reach about 0.7V, parasitic bipolar transistor 811a conducting, the electric current that ESD produced flows to power end VSS via power line 902, internal circuit 900 thereby obtained protection.When negative ESD voltage is benchmark when being applied to power end VSS with power end VDD (GND), internal circuit 900 will be protected in the same way.

When positive ESD voltage is benchmark when being applied to power end VSS with power end VDD (GND), be subjected to forward bias at the parasitic diode 811c of 0.7V left and right sides conducting.When parasitic diode 811c conducting, the current direction power end VDD that ESD produced, thereby internal circuit 900 has obtained protection.When negative ESD voltage is benchmark when being applied to power end VDD with power end VSS (GND), internal circuit 900 will be protected in the same way.

In addition, in Fig. 8, the parasitic capacitance (not shown) between the drain and gate of NMOS 811 is used to promote the grid voltage of NMOS 811.This electromotive force of substrate that raise, and reduced the voltage of parasitic bipolar transistor 811a conducting.That is to say, the easier conducting of parasitic bipolar transistor 811a.

In addition; disclose a kind of esd protection circuit, in this circuit, a capacity cell (capacitance with about several pico farads) is connected between the grid and drain electrode of NMOS; the voltage that is used to control its grid is (for example referring to the flat 6-163824 of the formerly disclosed patent application No. of Japan, Fig. 1).

Summary of the invention

According to the present invention, a kind of ESD protection circuit that is used to protect internal circuit to avoid electrostatic discharge effect comprises: power supply clamper part, it comprises n channel MOS field-effect transistor, this transistor be connected electrically in first power line that links to each other with first power end and with second source line that the second source end links to each other between; With the grid voltage control section, be used to control the grid voltage of described n channel MOS field-effect transistor, wherein said grid voltage control section comprises: p channel MOS field-effect transistor, this transistorized input-output end links to each other with described first power line, and another input-output end links to each other with the gate terminal of described n channel MOS field-effect transistor; First resistor, an end of this resistor links to each other with described another input-output end of described p channel MOS field-effect transistor and the gate terminal of described n channel MOS field-effect transistor, and the other end then links to each other with described second source line; Second resistor, an end of this resistor links to each other with described first power line, and the other end links to each other with the gate terminal of described p channel MOS field-effect transistor; And capacitor, an end of this capacitor links to each other with the gate terminal of the described other end of described second resistor and described p channel MOS field-effect transistor, and the other end links to each other with described second source line.

Description of drawings

In conjunction with the accompanying drawing that illustrates each preferred embodiment of the present invention, from following description, will make clear of the present invention more than and other characteristics and advantage.

Fig. 1 shows the circuit diagram of the principle of esd protection circuit according to an embodiment of the invention.

Fig. 2 is the physical circuit figure of esd protection circuit according to an embodiment of the invention.

Fig. 3 shows the transient response of traditional esd protection circuit when having applied ESD voltage.

Fig. 4 shows the transient response of esd protection circuit when having applied ESD voltage according to an embodiment of the invention.

Fig. 5 is the circuit diagram that is used for protecting the esd protection circuit of this internal circuit when ESD voltage is applied to the input signal end of internal circuit.

Fig. 6 shows the structure of the grid voltage control section that is included in the esd protection circuit shown in Figure 5, and described grid voltage control section is used to control the grid voltage of NMOS.

Fig. 7 is in accordance with another embodiment of the present invention, is used for protecting the circuit diagram of the esd protection circuit of this internal circuit when ESD voltage is applied to the input signal end of internal circuit.

Fig. 8 is the circuit diagram of traditional E SD protective circuit.

Embodiment

In traditional esd protection circuit, the conducting voltage of the parasitic bipolar transistor on the NMOS in the power supply clamper part reduces because of parasitic capacitance, and the value of parasitic capacitance is less than or equal to 1 flying method.Thus, the conducting voltage of parasitic bipolar transistor can't reduce a lot.Therefore, the electric current that ESD produced may flow into internal circuit, causes element impaired.

In traditional esd protection circuit, by between the grid of NMOS and drain electrode, connecting a big capacity cell (capacitance that for example has several pico farads), thereby raise grid voltage, use this esd protection circuit, entire area increases because of this capacity cell.In addition, under many circumstances, esd protection circuit is formed in the I/O zone of LSI, and in this zone, a plurality of transistor arrangement are the array apperance.Therefore, must add a process that forms capacity cell.In addition, in order to obtain the electric capacity of about several pico farads, the NMOS that a plurality of parasitic capacitance values can be less than or equal to 1 flying method is together in parallel.Yet, in this case, must use a lot of NMOS, so entire area has increased.

The present invention is exactly in order to overcome the above problems.The purpose of this invention is to provide a kind of space-saving esd protection circuit, it can protect internal circuit to avoid the influence of ESD effectively.

Below with reference to accompanying drawing embodiments of the invention are described.

Fig. 1 shows the circuit diagram of the principle of esd protection circuit according to an embodiment of the invention.

Esd protection circuit 100 can protect internal circuit to avoid the ESD influence; it comprises power supply clamper part 110 and grid voltage control section 120; described power supply clamper part 110 comprises a NMOS111; its be connected the power line 201 that links to each other with power end VDD and with power line 202 that power end VSS links to each other between, described grid voltage control section 120 is used to control the grid voltage of NMOS 111.

In power supply clamper part 110, the input-output end of NMOS 111 (drain electrode or source electrode) links to each other with power line 201 via resistor 112, and another input-output end of NMOS 111 links to each other with power line 202.In Fig. 1, with dashed lines schematically shows parasitic bipolar transistor 111a, dead resistance 111b and the parasitic diode 111c on the NMOS 111.The collector and emitter of parasitic bipolar transistor 111a corresponds respectively to drain electrode and the source electrode of NMOS 111.In this example, the drain electrode of NMOS 111 links to each other with power line 201.

Dredge the powerful electric current that ESD produces if a plurality of NMOS 111 are set, the characteristic of these NMOS 111 can be different so.In this case, have only parasitic bipolar transistor 111a conducting, the electric current that ESD produced will flow to it.For fear of the generation of this situation, be provided with resistor 112 (details will be described later).

Grid voltage control section 120 comprises PMOS 121, resistor 122 and 123 and capacitor 124.The input-output end of PMOS 121 links to each other with power line 201, and another input-output end of PMOS 121 links to each other with the gate terminal of NMOS 111.One end of resistor 122 links to each other with described another input-output end of PMOS121 and the gate terminal of NMOS 111, and the other end of resistor 122 then links to each other with power line 202.One end of resistor 123 links to each other with power line 201, and the other end links to each other with the gate terminal of PMOS 121.One end of capacitor 124 links to each other with the gate terminal of the described other end of resistor 123 and PMOS 121, and the other end of capacitor 124 then links to each other with power line 202.

PMOS 121 is being in conducting state by resistor 123 and capacitor 124 given time constants in the determined time.The grid voltage of NMOS 111 in the power supply clamper part 110 raises owing to passing the voltage that resistor 122 produced.

The operation of esd protection circuit 100 will be described below.

What suppose to act on power end VDD is positive dc voltage, and is benchmark (GND) with power end VSS.So the PMOS 121 in the grid voltage control section 120 disconnects.In this case, the gate terminal of the NMOS 111 in the power supply clamper part 110 is electrically connected to power line 202, and NMOS 111 disconnects.Therefore, the positive dc voltage that acts on power end VDD will be supplied to internal circuit 200, and internal circuit 200 is carried out predetermined operation.

When positive ESD voltage is benchmark (GND) when being applied to power end VDD and going up with power end VSS, when the drain voltage of NMOS 111 is elevated to certain value (Va), in the depletion layer in the n of NMOS 111 type drain junction district, avalanche breakdown will take place.As a result, electric current flows through substrate, and the electromotive force of substrate will rise.When the base stage of parasitic bipolar transistor 111a and the electrical potential difference between the emitter reach about 0.7V, parasitic bipolar transistor 111a conducting.Thus, the electric current that ESD produced flows to power end VSS via power line 202, and internal circuit 200 has obtained protection.

In grid voltage control section 120, PMOS 121 is being in conducting state by resistor 123 and capacitor 124 given time constants in the determined time.The grid voltage of NMOS 111 raises owing to passing the voltage that resistor 122 produced.As a result, on the surface of silicon substrate under the grid, formed a raceway groove.Electronics in this raceway groove enters the depletion layer in the drain junction district, and has formed electron-hole pair.The electron stream that is produced is to drain electrode, and substrate is flow through in the hole that is produced.This will cause avalanche breakdown.Therefore, parasitic bipolar transistor 111a conducting at an easy rate.That is to say that the parasitic bipolar transistor 111a on the NMOS111 will conducting on low drain voltage.

When negative ESD voltage is benchmark (GND) when being applied to power end VSS and going up with power end VDD, internal circuit 200 is protected in the same way.

On the other hand, when positive ESD voltage is benchmark (GND) when being applied to power end VSS and going up with power end VDD, be subjected to forward bias at the parasitic diode 111c of 0.7V left and right sides conducting.When parasitic diode 111c conducting, the current direction power end VDD that ESD produced is so internal circuit 200 has been subjected to protection.When negative ESD voltage is benchmark (GND) when being applied to power end VDD and going up with power end VSS, internal circuit 200 is protected in the same way.

As mentioned above; use is according to the esd protection circuit 100 of embodiment of the present invention; parasitic bipolar transistor 111a in the power supply clamper part 110 on the NMOS 111 will hang down conducting on the drain voltage; the internal circuit 200 so electric current that ESD produced just can not flowed through, but flow through power supply clamper part 110.Therefore, internal circuit 200 can be protected.

In addition, use the esd protection circuit 100 according to embodiment of the present invention, capacitor 124 will be used to control the time (grid voltage of NMOS 111 keeps the high time) that PMOS 121 is in conducting state, so do not need big capacitance.About a few flying method is just enough.Therefore, the area of esd protection circuit 100 can not increase.

To describe esd protection circuit according to an embodiment of the invention in detail below.

Fig. 2 is the physical circuit figure of esd protection circuit according to an embodiment of the invention.

Esd protection circuit 300 comprises power supply clamper part 310 and grid voltage control section 320; wherein power supply clamper part 310 comprises NMOS 311; NMOS 311 be connected electrically in the power line 401 that links to each other with power end VDD and with power line 402 that power end VSS links to each other between, grid voltage control section 320 is used for controlling the grid voltage of power supply clamper part 310 NMOS 311.

In power supply clamper part 310, the input-output end of NMOS 311 (drain electrode or source electrode) links to each other with power line 401 via resistor 312, and another input-output end of NMOS 311 links to each other with power line 402.In Fig. 2, with dashed lines schematically shows parasitic bipolar transistor 311a, dead resistance 311b and the parasitic diode 311c on the NMOS 311.The collector and emitter of parasitic bipolar transistor 311a corresponds respectively to drain electrode and the source electrode of NMOS 311.

For by the powerful electric current that ESD produced, a plurality of NMOS 311 in parallel.Even these a plurality of NMOS 311 variant on characteristic (the voltage difference of avalanche breakdown takes place), the parasitic bipolar transistor 311a on these a plurality of NMOS311 also can be by resistor 312 conductings simultaneously.

Below the effect of resistor 312 will be described particularly.If described a plurality of NMOS 311 is connected in parallel, parasitic bipolar transistor 311a will be different because of the voltage that the avalanche breakdown conducting takes place when positive ESD voltage is applied to power end VDD so.In addition, because the voltage drop that produces on the conductor resistance acts on the voltage near the parasitic bipolar transistor 311a of power end VDD and acts on away from meeting between the voltage on the parasitic bipolar transistor 311a of power end VDD different.Thus, not necessarily which parasitic bipolar transistor 311a with conducting.(still, avalanche breakdown voltage is lower, and will be easy to conducting near the parasitic bipolar transistor 311a on the NMOS 311 of power end VDD.) when a parasitic bipolar transistor 311a conducting, the electric current that ESD produced will flow to power end VSS, the electromotive force of power line 401 can not rise.Therefore, other parasitic bipolar transistor 311a can conducting, the parasitic bipolar transistor 311a of that conducting and electric current will be flowed through.As a result, that NMOS 311 of conducting will damage.The effect of resistor 312 is as follows.When parasitic bipolar transistor 311a conducting, during current direction power end VSS that ESD produced, resistor 312 will make the electromotive force of power line 401 remain more than or equal to certain value.By this, other parasitic bipolar transistor 311a is easy to conducting.As a result, all conductings of parasitic bipolar transistor 311a, the electric current that ESD produced is not the NMOS 311 that flows through, but all NMOS311 that flows through.

Grid voltage control section 320 comprises PMOS 321, active component 322 and 323 and NMOS 324.The input-output end of PMOS 321 links to each other with power line 401, and another input-output end of PMOS321 links to each other with the gate terminal of NMOS 311.Active component 322 and comprises NMOS 322-1,322-2,322-3 and the 322-4 of series connection between described another I/O end and power line 402 of PMOS 321.Active component 323 and comprises PMOS 323-1,323-2,323-3 and the 323-4 of series connection between the gate terminal and active component 322 of power line 401, PMOS 321.NMOS 324 is connected between active component 323 and the power line 402.PMOS 323-1,323-2,323-3 and 323-4 link to each other with power line 402 with the gate terminal of NMOS 324.

The conducting resistance of NMOS 322-1,322-2,322-3 and the 322-4 that connects in the active component 322 in the grid voltage control section 320 is suitable with the effect of the resistor shown in Fig. 1 122.Equally, the effect of the conducting resistance of PMOS 323-1,323-2,323-3 and the 323-4 of series connection and the resistor shown in Fig. 1 123 is suitable in the active component 323.Parasitic capacitance among the NMOS 324 is suitable with the effect of the capacitor shown in Fig. 1 124.

A plurality of PMOS 321 (not shown) parallel connections are with the grid voltage of control NMOS 311.In addition, a plurality of (for example 10) NMOS 324 parallel connections are to control the time that PMOS 321 is in conducting state by the parasitic capacitance in them.In Fig. 2, four NMOS 322-1,322-2,322-3 and 322-4 connect in active component 322.Yet, can increase or reduce the quantity of NMOS in the active component 322, with the summation by their conduction resistance values the grid voltage of NMOS 311 in the power supply clamper part 310 is adjusted into a suitable value (for example, 2.5V).Equally, also can suitably change the quantity of PMOS in the active component 323, with the control time constant.

The operation of esd protection circuit 300 will be described below.

Suppose that positive dc voltage acts on power end VDD, and with power end VSS as benchmark (GND).PMOS 323-1 in the active component 323 is to the 323-4 conducting so, and the PMOS 321 in the grid voltage control section 320 will disconnect.At this moment, NMOS 322-1 is to the 322-4 conducting.By this, the gate terminal of the NMOS 311 in the power supply clamper part 310 is electrically connected with power line 402 via active component 322, and NMOS 311 disconnects.As a result, the positive dc voltage that acts on power end VDD will be provided for internal circuit 400, and internal circuit 400 is carried out predetermined operation.

When with power end VSS being benchmark (GND) when positive ESD voltage is applied to power end VDD, when the drain voltage of NMOS 311 rises to certain value (Va), in the depletion layer in NMOS 311 in the n type drain junction district avalanche breakdown will take place.As a result, electric current flows through substrate, and the electromotive force of substrate rises.When the base stage of parasitic bipolar transistor 311a and the electrical potential difference between the emitter reach about 0.7V, parasitic bipolar transistor 311a conducting.By this, the electric current that ESD produced flows to power end VSS via power line 402, and internal circuit 400 has obtained protection.

In grid voltage control section 320, PMOS 321 is being in conducting state by the given time constant of the parasitic capacitance among active component 323 and the NMOS 324 in the determined time.The grid voltage of NMOS 311 is owing to the voltage that is produced on the active component 322 raises.As a result, on the surface of silicon under the grid, just formed a raceway groove.Electronics in this raceway groove enters the depletion layer in the drain junction district, and generates electron-hole pair.The electron stream that is produced is to drain electrode, and substrate is then flow through in the hole that is produced.This will cause avalanche breakdown.Therefore, parasitic bipolar transistor 311a is easy to conducting.That is to say that the parasitic bipolar transistor 311a on the NMOS 311 will conducting on low drain voltage.

When negative ESD voltage is benchmark (GND) when being applied to power end VSS and going up with power end VDD, internal circuit 400 will be protected in the same way.

On the other hand, when positive ESD voltage is benchmark (GND) when being applied to power end VSS and going up with power end VDD, will be subjected to forward bias at the parasitic diode 311c of about 0.7V conducting.When parasitic diode 311c conducting, the current direction power end VDD that ESD produced is so internal circuit 400 has obtained protection.When negative ESD voltage is benchmark (GND) when being applied to power end VDD with power end VSS, internal circuit 400 will be protected in the same way.

To illustrate when 3 the simulation result of resulting transient response when the ESD voltage of 000V acts on the power end VDD of esd protection circuit shown in Figure 2 300 below.Also will illustrate the simulation result of the transient response of traditional E SD protective circuit 800 shown in Figure 8.These simulation results are all realized with a kind of commercial available circuit emulator (HSPICE).

Fig. 3 shows the transient response of traditional E SD protective circuit when having applied ESD voltage.

In Fig. 3, trunnion axis instruction time (s), and vertical axis instructed voltage (V).There is shown drain voltage and the grid voltage of the NMOS 811 in the power supply clamper part 810.

Parasitic bipolar transistor 811a conducting on voltage Vt on the NMOS 811.As shown in Figure 3, the grid voltage that causes by the parasitic capacitance (not shown) of the NMOS 811 in the traditional E SD protective circuit 800 0.68V that has an appointment at most that rises.Thus, voltage Vt is 7V, is higher.

Voltage Vt must be lower than the voltage that makes internal circuit 400 impaired, that is to say, be lower than the voltage (electric current that ESD produced necessarily can not pass through internal circuit 400) of transistor (not shown) in the internal circuit 400.In addition, in order to prevent parasitic bipolar transistor 311a conducting when NMOS 311 operate as normal, voltage Vt must be higher than normal power voltage (rated supply voltage).In esd protection circuit 300, voltage Vt is set by the grid voltage of controlling NMOS 311 according to embodiment of the present invention.

Grid voltage to NMOS 311 is controlled, and makes the quantity of the electron-hole pair that electronics in raceway groove is produced when entering depletion layer in the drain junction district to increase.The hole that is produced is detected as the electric current that flows through substrate.Therefore, when the electric current that flows through substrate is the strongest, produced the electron-hole pair of maximum quantity.If the grid voltage of NMOS 311 satisfies this condition, will obtain correct voltage Vt so.

If the grid voltage of NMOS 311 is too low, then the electron-hole pair quantity of Chan Shenging seldom, the electric current that flows through substrate is very weak.As a result, the electromotive force of substrate can not rise, and parasitic bipolar transistor 311a conducting easily.

If the grid voltage of NMOS 311 is too high, then the resistance in the raceway groove will cause voltage drop, and the electron-hole pair quantity that is produced seldom.As a result, the electric current of the substrate of flowing through is very weak, and parasitic bipolar transistor 311a can conducting.

Fig. 4 shows the transient response of esd protection circuit when having applied ESD voltage according to embodiment of the present invention.

In Fig. 4, trunnion axis instruction time (s), and vertical axis instructed voltage (V).There is shown drain voltage and the grid voltage of the NMOS 311 in the power supply clamper part 310.

Transient response shown in Fig. 4 obtains by following esd protection circuit 300 is carried out emulation; in this esd protection circuit 300; 36 NMOS 311 in parallel in power supply clamper part 310; 34 PMOS 321 in parallel in grid voltage control section 320, and in grid voltage control section 320 10 NMOS 324 in parallel.These be included in the MOS field-effect transistor in the esd protection circuit 300 each all have the grid long (L) of 0.34 μ m and the grid wide (W) of 1.56 μ m.

As shown in Figure 4, be raised to 2.5V at grid voltage according to the NMOS 311 in the esd protection circuit 300 of embodiment of the present invention.As a result, voltage Vt can be reduced to 4.5V.

As mentioned above; utilization is according to the esd protection circuit 300 of embodiment of the present invention; then the parasitic bipolar transistor 311a on the NMOS 311 in the power supply clamper part 310 will hang down conducting on the drain voltage; the internal circuit 400 so electric current that ESD produced is not flowed through, but the power supply clamper part 310 of flowing through.Therefore, internal circuit 400 can be protected.

In addition, utilize the esd protection circuit 300 according to embodiment of the present invention, the capacitor that then is used to control PMOS 321 conducting state times (that is, the grid potential of NMOS 311 remains the high time) just no longer needs big capacitance.About a few flying method is just enough.Therefore, can use the parasitic capacitance among the NMOS 324, and the area of esd protection circuit 300 can not increase.

In addition, utilize the esd protection circuit 300 according to embodiment of the present invention, then resistor and capacitor can be by using NMOS 322-1,322-2,322-3 and 322-4, and PMOS 323-1,323-2,323-3 and 323-4 and NMOS 324 form.This has saved the process that forms unnecessary element.For example, can making wherein efficiently, transistor arrangement is the IO macrocell of array.

To be described in the esd protection circuit that is used to protect internal circuit when ESD voltage is applied to the input signal end of internal circuit rather than power end VDD or VSS below.

Fig. 5 is the circuit diagram that is used to protect the esd protection circuit of internal circuit when ESD voltage is applied to the input signal end of internal circuit.

Wherein with Fig. 1 in identical assembly come mark with identical label, and save description of them.

Esd protection circuit 500 is used for when ESD voltage is applied to the input signal end VIN of internal circuit 200 protection internal circuit 200, esd protection circuit 500 comprise be connected electrically in the power line 201 that links to each other with power end VDD and with holding wire 203 that input signal end VIN links to each other between PMOS 501, be connected electrically in holding wire 203 and with power line 202 that power end VSS links to each other between NMOS 502, the grid voltage control section 520 that the grid voltage control section 510 and being used to that is used to control the grid voltage of PMOS 501 is controlled the grid voltage of NMOS 502.

NMOS 502 links to each other with holding wire 203 by resistor 503.For by the powerful electric current that ESD produced, there is a plurality of NMOS 502 parallel with one another.As mentioned above, even these a plurality of NMOS502 there are differences (the voltage difference that avalanche breakdown takes place) on characteristic, a plurality of parasitic bipolar transistor 502a also can be by resistor 503 conductings simultaneously.

In Fig. 5, with dashed lines schematically shows some parasitic antennas, comprise capacitor 200a, its capacitance is corresponding to electric capacity between the power supply of internal circuit 200, also comprise parasitic bipolar transistor 501a, dead resistance 501b and parasitic diode 501c on the PMOS 501, and parasitic bipolar transistor 502a, dead resistance 502b on the NMOS 502 and parasitic diode 502c.In this example, the drain electrode of NMOS 501 links to each other with power line 201.

The grid voltage control section 510 that is used to control the grid voltage of PMOS 501 has the CMOS inverter structure.For example, in the grid voltage control section 820 in traditional E SD protective circuit 800 shown in Figure 8, the gate terminal of PMOS 821 and NMOS 822 is connected to GND, just can be with grid voltage control section 820 as grid voltage control section 510.

Fig. 6 shows the structure of the grid voltage control section that is included in grid voltage in the esd protection circuit shown in Figure 5, that be used to control NMOS.

In Fig. 6, the PMOS501 that is included in the esd protection circuit shown in Figure 5 500, grid voltage control section 510 etc. are not shown.

The circuit structure of the grid voltage control section 120 shown in Fig. 1 can be used for grid voltage control section 520, with the grid voltage of control NMOS 502.That is to say that grid voltage control section 520 comprises PMOS 521, resistor 522 and 523 and capacitor 524.The input-output end of PMOS 521 links to each other with power line 201, and another input-output end of PMOS 521 links to each other with the gate terminal of NMOS502.One end of resistor 522 links to each other with described another input-output end of PMOS 521 and the gate terminal of NMOS 502, and the other end of resistor 522 links to each other with power line 202.One end of resistor 523 links to each other with power line 201, and the other end of resistor 523 links to each other with the gate terminal of PMOS 521.One end of capacitor 524 links to each other with the gate terminal of the described other end of resistor 523 and PMOS 521, and the other end of capacitor 524 links to each other with power line 202.

Describe below when ESD voltage is applied to input signal end VIN, by the operation of esd protection circuit 500 execution.

When positive ESD voltage is benchmark (GND) when being applied to input signal end VIN with power end VDD, the PMOS 501 shown in Fig. 5 is subjected to forward bias.By this, parasitic diode 501c conducting, current direction power end VDD is so internal circuit 200 has obtained protection.

When negative ESD voltage is that benchmark (GND) is when being applied to input signal end VIN with power end VDD; (1) the parasitic bipolar transistor 501a conducting on the PMOS 501; the current direction input signal end VIN that ESD produced; (2) be arranged in parasitic bipolar transistor 111a on the NMOS 111 of mains side and as shown in Figure 1 esd protection circuit 100 and the parasitic diode 502c conducting on the NMOS 502; the current direction input signal end VIN that ESD produced; and (3) by have and the power supply of internal circuit 200 between the capacitor 200a of the corresponding capacitance of electric capacity and the parasitic diode 502c on the NMOS 502 ESD has taken place, the current direction input signal end VIN that ESD produced.As a result, internal circuit 200 has obtained protection.

Compare with NMOS 111, the parasitic bipolar transistor 501a on the PMOS 501 only transmits more weak electric current.Therefore; if parasitic diode 502c on the parasitic bipolar transistor 501a on the PMOS 501, the NMOS 502 and the parasitic bipolar transistor 111a conducting on voltage Vtlp, Vfn and Vtln respectively that is arranged in the esd protection circuit 100 of mains side, design should guarantee following relation establishment so:

Vtln+Vfn<Vtlp

That is to say, above path described in (2) should be used as " primary current path ".

On the other hand; when positive ESD voltage is that benchmark (GND) is when being applied to input signal end VIN with power end VSS; (1) the parasitic bipolar transistor 502a on the NMOS 502 is with conducting; the current direction power end VSS that ESD produced; (2) the parasitic diode 501c on the PMOS 501; and be arranged in all conductings of parasitic bipolar transistor 111a on the NMOS 111 of mains side and as shown in Figure 1 esd protection circuit 100; the current direction power end VSS that ESD produced; and (3) by the parasitic diode 501c on the PMOS 501 and have and the power supply of internal circuit 200 between the capacitor 200a of the corresponding capacitance of electric capacity ESD has taken place, the current direction that ESD produced power end VSS.

When negative ESD voltage is benchmark (GND) when being applied to input signal end VIN with power end VSS, the parasitic diode 502c on the NMOS 502 is subjected to forward bias.As a result, parasitic diode 502c conducting, the current direction that ESD produced input signal end VIN.

Below with reference to Fig. 5 and Fig. 6 specifically describe when positive ESD voltage be benchmark (GND) when being applied to input signal end VIN with power end VSS, esd protection circuit 500 is in situation (1) performed operation down.

When positive ESD voltage is benchmark (GND) when being applied to input signal end VIN with power end VSS, in the depletion layer in the n of NMOS 502 type drain junction district avalanche breakdown will take place.As a result, electric current will flow through substrate, and the electromotive force of substrate rises.When the base stage of parasitic bipolar transistor 502a and the electrical potential difference between the emitter reach about 0.7V, parasitic bipolar transistor 502a conducting.By this, the electric current that ESD produced flows to power end VSS by power line 202, and internal circuit 200 has obtained protection.

At this moment, the parasitic diode 501c on the PMOS shown in Fig. 5 501 is in conducting state.Thus, the electric current that ESD produced flows along the power line 201 that links to each other with power end VDD, and the electromotive force of power line 201 raises.As a result, in grid voltage control section 520, PMOS 521 is in conducting state in the time constant that is provided by resistor 523 that links to each other with power line 201 and capacitor 524 in the determined time.The grid potential of NMOS 502 raises because of the voltage that is produced on the resistor 522.Therefore, on the surface of silicon substrate under the grid, formed a raceway groove.Electronics in this raceway groove enters the depletion layer in the drain junction district, and produces electron-hole pair.The electron stream that is produced is to drain electrode, the hole that the is produced substrate of flowing through.This will cause avalanche breakdown.Thus, parasitic bipolar transistor 502a is easy to conducting.That is to say that the parasitic bipolar transistor 502a on the NMOS 502 will conducting on low drain voltage.

As a result, except top (2) described path, can also establish the path described in (1) soon.This is arranged in reduction the load of NMOS 111 of the esd protection circuit 100 of mains side.

The same with the esd protection circuit 300 shown in Fig. 2, can a plurality of PMOS 521 in parallel, with the grid voltage of control NMOS 502.

In addition, the same with esd protection circuit 300, can form resistor 522 with the NMOS of a plurality of series connection.Equally, can form resistor 523 with a plurality of PMOS of series connection.Also can form capacitor 524 with a plurality of NMOS of parallel connection.Can suitably change the quantity of these elements, (for example, 2.5V) (on this suitable value, heavy current will flow through substrate) perhaps controls the time that PMOS 521 is in conducting state thereby the grid voltage of NMOS 502 is set to a suitable value.

This has saved the process that forms unnecessary element.For example, can making wherein efficiently, transistor arrangement is the IO macrocell of array.

In addition, following circuit can be used as esd protection circuit, is used for protecting when ESD voltage is applied to the input signal end of internal circuit this internal circuit.

Fig. 7 is according to another embodiment of the invention, is used for protecting when ESD voltage is applied to the input signal end of internal circuit the circuit diagram of the esd protection circuit of this internal circuit.

The grid voltage control section 530 that comprises the grid voltage that is used to control NMOS 502 in the esd protection circuit shown in Figure 7.This grid voltage control section 530 is different from the grid voltage control section 520 shown in Fig. 5.Other assembly in the esd protection circuit shown in Figure 7 is identical with the assembly shown in Fig. 5.In Fig. 7, come these assemblies of mark with identical label, perhaps not shown.

The grid voltage control section 530 that is used to control the grid voltage of NMOS 502 comprises PMOS531, resistor 532 and 533 and capacitor 534.The input-output end of PMOS 531 links to each other with holding wire 203, and another input-output end of PMOS 531 links to each other with the gate terminal of NMOS 502.One end of resistor 532 links to each other with described another input-output end of PMOS 531 and the gate terminal of NMOS 502, and the other end of resistor 532 links to each other with power line 202.One end of resistor 533 links to each other with holding wire 203, and the other end of resistor 533 links to each other with the gate terminal of PMOS 531.One end of capacitor 534 links to each other with the described other end of resistor 533 and the gate terminal of PMOS531, and the other end of capacitor 534 links to each other with power line 202.

The operation of the esd protection circuit shown in Fig. 7 is identical with the operation of the esd protection circuit 100 shown in Fig. 1.Yet, must be considered as signal end VIN to power end VDD.At this moment, when normal running, " H " (high level) or " L " (low level) have been imported from input signal end VIN output or to it.When being input as " H ", the gate terminal of PMOS 531 is in " H ", and NMOS 502 does not work.When being input as " L ", PMOS 531 conductings.Yet the gate terminal of NMOS 502 is in " L ", and NMOS 502 does not work.When positive ESD voltage is benchmark (GND) when being applied to input signal end VIN with power end VSS, the grid voltage of NMOS 502 remains height by resistor 533 and capacitor 534 in certain time period.As a result, parasitic bipolar transistor 502a conducting, the current direction that ESD produced power end VSS, so internal circuit 200 has obtained protection.

For the esd protection circuit shown in Fig. 2 300, can a plurality of PMOS531 in parallel, with the grid voltage of control NMOS 502.

In addition, the same with esd protection circuit 300, can form resistor 532 with the NMOS of a plurality of series connection.Equally, can form resistor 533 with a plurality of PMOS of series connection.Also can form capacitor 534 with a plurality of NMOS of parallel connection.Can suitably change the quantity of these elements, (for example, 2.5V) (on this suitable value, heavy current will flow through substrate) perhaps controls the time that PMOS 531 is in conducting state thereby the grid voltage of NMOS 502 is set to a suitable value.

The present invention is applicable to that the internal circuit of protection among the LSI avoid the esd protection circuit of ESD influence.

According to the present invention, when positive ESD voltage acts on first power end, in the time constant that provides by a certain resistor and a certain capacitor in the determined time, PMOS is in conducting state, one end of described resistor links to each other with first power line, the other end links to each other with the gate terminal of described PMOS, and an end of described capacitor links to each other with the described other end of described resistor and the gate terminal of described PMOS, the other end links to each other with the second source line, and the grid voltage of NMOS raises because of the voltage that is produced on the following resistor, one end of this resistor links to each other with another input-output end of described PMOS and the gate terminal of described NMOS, and the other end links to each other with described second source line.As a result, the electromotive force of substrate raises, and the conducting on low drain voltage of the parasitic bipolar transistor on the described NMOS is so internal circuit has obtained protection.

In addition, described capacitor is used to be provided with the time that described PMOS is in conducting state, and very little electric capacity is just enough.This has realized the saving in space.

Foregoing is regarded as only schematically having explained principle of the present invention.Further, because for a person skilled in the art, can make a lot of modifications and change at an easy rate, so do not wish to limit the present invention in the strict structure and application of shown and description, therefore, all suitable modification things and equivalent all can be regarded as having fallen into the present invention in the scope of claims and equivalent thereof.

Claims (17)

1. an ESD protection circuit is used to protect internal circuit to avoid the influence of static discharge, and described circuit comprises:
Power supply clamper part comprises n channel MOS field-effect transistor, this transistor be connected electrically in first power line that links to each other with first power end and with second source line that the second source end links to each other between; With
The grid voltage control section is used to control the grid voltage of described n channel MOS field-effect transistor, and wherein said grid voltage control section comprises:
P channel MOS field-effect transistor, its an input-output end links to each other with described first power line, and another input-output end links to each other with the gate terminal of described n channel MOS field-effect transistor;
First resistor, its end links to each other with described another input-output end of described p channel MOS field-effect transistor and the gate terminal of described n channel MOS field-effect transistor, and the other end links to each other with described second source line;
Second resistor, its end links to each other with described first power line, and the other end links to each other with the gate terminal of described p channel MOS field-effect transistor; With
Capacitor, its end links to each other with the described other end of described second resistor and the gate terminal of described p channel MOS field-effect transistor, and the other end links to each other with described second source line.
2. ESD protection circuit as claimed in claim 1; wherein; described grid voltage control section is controlled the grid voltage of described n channel MOS field-effect transistor, makes the voltage of the parasitic bipolar transistor conducting on the described n channel MOS field-effect transistor be lower than the voltage that makes described internal circuit impaired.
3. ESD protection circuit as claimed in claim 1, wherein, described first resistor is a plurality of n channel MOS field-effect transistors of series connection.
4. ESD protection circuit as claimed in claim 1, wherein, described second resistor is a plurality of p channel MOS field-effect transistors of series connection.
5. ESD protection circuit as claimed in claim 1, wherein, described capacitor is a plurality of n channel MOS field-effect transistors in parallel.
6. ESD protection circuit; be used to protect internal circuit to avoid acting on the influence of the static discharge voltage of input signal end; described internal circuit be connected electrically in first power line that links to each other with first power end and with second source line that the second source end links to each other between, described circuit comprises:
N channel MOS field-effect transistor, it is connected electrically between the holding wire and described second source line that links to each other with described input signal end; With
The grid voltage control section is used to control the grid voltage of described n channel MOS field-effect transistor, and wherein said grid voltage control section comprises:
P channel MOS field-effect transistor, its an input-output end links to each other with described first power line, and another input-output end links to each other with the gate terminal of described n channel MOS field-effect transistor;
First resistor, its end links to each other with described another input-output end of described p channel MOS field-effect transistor and the gate terminal of described n channel MOS field-effect transistor, and the other end links to each other with described second source line;
Second resistor, its end links to each other with described first power line, and the other end links to each other with the gate terminal of described p channel MOS field-effect transistor; With
Capacitor, its end links to each other with the described other end of described second resistor and the gate terminal of described p channel MOS field-effect transistor, and the other end links to each other with described second source line.
7. ESD protection circuit as claimed in claim 6, wherein, described first resistor is a plurality of n channel MOS field-effect transistors of series connection.
8. ESD protection circuit as claimed in claim 6, wherein, described second resistor is a plurality of p channel MOS field-effect transistors of series connection.
9. ESD protection circuit as claimed in claim 6, wherein, described capacitor is a plurality of n channel MOS field-effect transistors in parallel.
10. ESD protection circuit as claimed in claim 6 also comprises:
The 2nd p channel MOS field-effect transistor, it is connected electrically between described first power line and the described holding wire; With
The second grid voltage control section is used to control the grid voltage of described the 2nd p channel MOS field-effect transistor.
11. ESD protection circuit as claimed in claim 10, wherein, the described second grid voltage control section is a CMOS inverter, the input end grounding of this inverter.
12. ESD protection circuit; be used to protect internal circuit to avoid acting on the influence of the static discharge voltage of input signal end; described internal circuit be connected electrically in first power line that links to each other with first power end and with second source line that the second source end links to each other between, described circuit comprises:
N channel MOS field-effect transistor, it is connected electrically between the holding wire and described second source line that links to each other with described input signal end; With
The grid voltage control section is used to control the grid voltage of described n channel MOS field-effect transistor, and wherein said grid voltage control section comprises:
P channel MOS field-effect transistor, its an input-output end links to each other with described holding wire, and another input-output end links to each other with the gate terminal of described n channel MOS field-effect transistor;
First resistor, its end links to each other with described another input-output end of described p channel MOS field-effect transistor and the gate terminal of described n channel MOS field-effect transistor, and the other end links to each other with described second source line;
Second resistor, its end links to each other with described holding wire, and the other end links to each other with the gate terminal of described p channel MOS field-effect transistor; With
Capacitor, its end links to each other with the described other end of described second resistor and the gate terminal of described p channel MOS field-effect transistor, and the other end links to each other with described second source line.
13. ESD protection circuit as claimed in claim 12, wherein, described first resistor is a plurality of n channel MOS field-effect transistors of series connection.
14. ESD protection circuit as claimed in claim 12, wherein, described second resistor is a plurality of p channel MOS field-effect transistors of series connection.
15. ESD protection circuit as claimed in claim 12, wherein, described capacitor is a plurality of n channel MOS field-effect transistors in parallel.
16. ESD protection circuit as claimed in claim 12 also comprises:
The 2nd p channel MOS field-effect transistor, it is connected electrically between described first power line and the described holding wire; With
The second grid voltage control section is used to control the grid voltage of described the 2nd p channel MOS field-effect transistor.
17. ESD protection circuit as claimed in claim 16, wherein, the described second grid voltage control section is a CMOS inverter, the input end grounding of this inverter.
CNB2004100572543A 2004-02-18 2004-08-26 Electrostatic discharge protection circuit CN100390987C (en)

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CN107565537A (en) * 2017-09-29 2018-01-09 广州慧智微电子有限公司 A kind of esd protection circuit and method
CN107565537B (en) * 2017-09-29 2019-09-20 广州慧智微电子有限公司 A kind of esd protection circuit and method
CN108512207A (en) * 2018-04-18 2018-09-07 矽力杰半导体技术(杭州)有限公司 Electrostatic discharge protective circuit

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US20050180076A1 (en) 2005-08-18

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