CN109752612B - Simulation circuit and method of chip ESD protection circuit - Google Patents
Simulation circuit and method of chip ESD protection circuit Download PDFInfo
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Abstract
The invention provides a simulation circuit and a simulation method of a chip ESD protection circuit, which can find a device with poor ESD resistance in a chip in advance through simulation, optimize the circuit and improve the ESD resistance of the chip. The simulation circuit comprises an ESD excitation source, an ESD protection module and at least one functional module, wherein the ESD excitation source is connected between a power supply voltage VDD and a common grounding voltage VSS; the ESD excitation source is used for loading ESD voltage according to a set ESD current characteristic curve; the ESD protection module is internally provided with a power supply clamp NMOS tube NESD, the drain electrode of the power supply clamp NMOS tube NESD is provided with a current monitor Ifail connected with a power supply voltage VDD, and the source electrode of the power supply clamp NMOS tube NESD is connected with a common ground voltage VSS; the functional module is provided with a CMOS tube N1, and a voltage monitor Efail is respectively arranged between the grid and the drain of the CMOS tube N1 and between the grid and the source.
Description
Technical Field
The invention relates to a simulation test of a chip, in particular to a simulation circuit and a method of a chip ESD protection circuit.
Background
In the prior art, each chip includes an ESD protection module and a corresponding functional module, as shown in fig. 1. The ESD protection module generally includes a large-sized power clamp NMOS transistor NESD, the gate g1 of which is connected to the power supply VDD through a capacitor C1 and to ground VSS through a resistor R1.
The functional module realizes various functions of the chip, wherein the CMOS tube N1 is very sensitive to ESD, and the gate oxide of N1 is easily damaged by ESD events, so that important verification is required. In fig. 1, Rvdd is the power supply network resistance of the VDD power supply from the pad to the ESD protection module, and Rvss is the ground resistance of VSS from the pad to the ESD protection module.
When an ESD strike occurs when the chip is in PS mode (VDD + ESD pulse, VSS 0), there will be a current flow from VDD to VSS as shown in fig. 2. When an ESD event occurs in PS mode, positive current Iesd flows from the VDD pad, through Rvdd, through NESD, through Rvss, and finally to the VSS pad. If ESD strength is large, then Iesd is large, and the current through the NESD is large, which may cause the NESD to burn out, such as the NESD node 1 in FIG. 2. Meanwhile, if the ESD strength is large, the gate-drain voltage (Vgd) or the gate-source voltage (Vgs) of the N1 transistor may be too large, so that the gate-oxide insulating layer (node 2 or node 3) in the middle of the gate-drain or gate-source is broken down.
How to predict whether the node 1, the node 2 and the node 3 in fig. 2 can be damaged by the ESD shock in advance in a complex ESD event is very meaningful for optimizing an ESD protection scheme and a power supply network.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a simulation circuit and a simulation method of a chip ESD protection circuit, which can find a device with poor ESD resistance in a chip in advance through simulation, optimize the circuit and improve the ESD resistance of the chip.
The invention is realized by the following technical scheme:
a simulation circuit of a chip ESD protection circuit comprises an ESD excitation source, an ESD protection module and at least one functional module, wherein the ESD excitation source is connected between a power supply voltage VDD and a common grounding voltage VSS;
the ESD excitation source is used for loading ESD voltage according to a set ESD current characteristic curve;
the ESD protection module is internally provided with a power supply clamp NMOS tube NESD, the drain electrode of the power supply clamp NMOS tube NESD is provided with a current monitor Ifail connected with a power supply voltage VDD, and the source electrode of the power supply clamp NMOS tube NESD is connected with a common ground voltage VSS;
the functional module is provided with a CMOS tube N1, and a voltage monitor Efail is respectively arranged between the grid and the drain of the CMOS tube N1 and between the grid and the source.
Preferably, a power supply network resistor Rvdd is arranged between the power supply voltage VDD and the ESD protection module from the pad, and a ground resistor Rvss is arranged between the common ground voltage VSS and the ESD protection module from the pad.
Preferably, the ESD protection module further includes a capacitor C1 and a resistor R1, wherein the gate of the power clamp NMOS NESD is connected to the power voltage VDD through a capacitor C1, and the gate is connected to the common ground voltage VSS through a resistor R1.
A simulation method of a chip ESD protection circuit comprises the following steps,
step 2, obtaining an ESD current characteristic curve for determining the ESD level from a factory or a customer;
step 3, fitting an ESD current characteristic curve through mathematical modeling;
step 4, inserting a current monitor Ifail and a voltage monitor Efail into the simulation circuit according to the simulation circuit in the scheme;
step 5, obtaining the current limit value and the voltage limit value which can be borne by the device from a process plant, and inputting the current limit value and the voltage limit value into a corresponding current monitor Ifail and a corresponding voltage monitor Efail;
step 6, opening a current monitor Ifail switch, and monitoring the current in the ESD simulation;
step 7, starting an ESD excitation source, and starting simulation according to the fitted ESD current characteristic curve;
step 8, if the Ifail current of the current monitor exceeds the set limit value, reporting an actual effect error, then increasing the size of a power supply clamp NMOS tube NESD in the ESD protection module, and repeating the step 7 to simulate again;
step 9, if the current of the current monitor Ifail does not exceed the set limit value, a voltage monitor Efail switch is opened, and the voltage in the ESD simulation is monitored;
step 10, if the voltage of the voltage monitor Efail exceeds the set limit value, reporting an actual effect error, reducing the resistance Rvdd and the grounding resistance Rvss of a power supply network or increasing the size of a power supply clamp NMOS tube NESD in an ESD protection module, and re-simulating;
and 11, if the voltage of the voltage monitor Efail does not exceed the set limit value, the ESD protection module is effective, and the simulation is finished.
Preferably, in step 1, the HBM model with an ESD level of 2000V that the chip needs to reach is determined.
Preferably, the specific step of fitting the ESD current characteristic curve by mathematical modeling in step 3 is as follows,
step 3.1, describing the ESD current characteristic through the following mathematical formula to obtain a fitted current characteristic curve of the ESD excitation source;
when the Time is less than or equal to Td;
when Time > Td;
wherein, the Time is a Time coordinate in the ESD discharge process,
vhbm is a model voltage corresponding to the ESD level which is required to be achieved by the chip; τ 1 is a time constant of ESD current rising, τ 2 is a time constant of ESD current falling, and Td is a starting time point of ESD current falling trend;
and 3.2, adjusting the time parameters tau 1, tau 2 and Td to enable the current characteristic curve of the fitted ESD excitation source to be close to the ESD current characteristic curve provided by a factory, so as to obtain the fitted ESD current characteristic curve for the ESD excitation source.
Compared with the prior art, the invention has the following beneficial technical effects:
according to the invention, the current monitor is added on the ESD protection device in the ESD protection module, so that the maximum bearing current of the ESD protection device can be limited and protected during simulation, the influence on the ESD protection device is avoided, and the verification and detection of current parameters are realized; the voltage monitor between the grid drain electrodes and the voltage monitor between the grid source electrodes on the CMOS tube in the functional module can limit and protect the maximum bearing voltage of the grid oxide of the CMOS tube during simulation, thereby avoiding influencing the CMOS tube and simultaneously realizing the verification and detection of voltage parameters.
Drawings
Fig. 1 is a schematic diagram of a chip internal module structure in the prior art.
Fig. 2 shows the ESD current path in PS mode of the chip in the prior art.
FIG. 3 is a block diagram of the simulation circuit according to the embodiment of the present invention.
Fig. 4 is an ESD current characteristic curve of the human discharge model in the example of the present invention.
Fig. 5 is a comparison of the fitted and real current characteristic curves described in the examples of the invention.
FIG. 6 is a flow chart of the simulation method in an embodiment of the present invention.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
As shown in fig. 3, the simulation circuit according to the present invention adds 1 ESD excitation source between a power supply voltage VDD and a common ground voltage VSS, and sets 1 current monitor (Ifail) between a drain of a power clamp NMOS NESD and a gate and a drain of a CMOS transistor N1, and sets 1 voltage monitor (Efail) between the gate and a source, respectively. The gate of the power clamp NMOS NESD is connected to the power supply voltage VDD through a capacitor C1, the gate is connected to the common ground voltage VSS through a resistor R1, Rvdd is a power supply network resistor for the power supply voltage VDD from the pad to the ESD protection module, and Rvss is a ground resistor for the common ground voltage VSS from the pad to the ESD protection module.
Specifically, the ESD stimulus is a current characteristic curve describing a specific ESD event, which is provided by a chip application customer or an ESD test factory, and is related to an ambient temperature, a humidity and a contact manner. Fig. 4 is an ESD current characteristic curve when HBM (human body discharge model) provided by a certain factory is equal to 2000V.
A mathematical model is established based on factory supplied ESD current characteristics, as shown in fig. 4. The current characteristics are described by the following mathematical formula:
when the Time is less than or equal to Td;
when Time > Td;
where Vhbm is 2000V, the human discharge model voltage is set to 2000V
Time parameters: τ 1-5.2 ns τ 2-150 ns Td-5.3 ns (4)
When the time is less than Td, the current is represented as formula (1), and when the time is greater than Td, the current is represented as formula (2). Where Ip is derived from equation (3). The Time parameter is shown as formula (4), Time is a Time coordinate in the ESD discharge process, τ 1 is an ESD current rise Time constant, τ 2 is an ESD current fall Time constant, and Td is an ESD current fall trend start Time point. The time parameters τ 1, τ 2, and Td are adjusted to make the ESD stimulus curve close to the factory-supplied ESD current characteristic curve, as shown in fig. 5.
Ireal is a factory-supplied current characteristic curve. Isim is a current characteristic curve fitted by mathematical formulas (1) and (2). As can be seen from fig. 5, in the ESD simulation, the simulator calls equations (1) and (2) to generate an ESD stimulus close to the real situation.
The current monitor (Ifail) is used for monitoring whether the current flowing through the ESD protection device reaches a limit value, if the current reaches the limit value, an error is reported, the simulation is stopped, and the simulation is carried out after the design of the ESD protection module is optimized.
The current monitor needs to provide the maximum current that the device size and unit size can withstand.
The voltage monitor (Efail) is used for monitoring whether the voltage flowing through the ESD protection device reaches a limit value, if the voltage reaches the limit value, an error is reported, simulation is stopped, and simulation is carried out after ESD design is optimized. After simulation error, the ESD designer can increase the size of the NESD, i.e. increase the channel width from 300um to 350um, and the NESD can withstand 2000V.
The voltage monitor needs to provide positive and negative voltages that the device gate oxide can withstand. After simulation error, the ESD designer can increase the size of NESD, i.e., increase the channel width from 300um to 400um, or decrease the resistance of Rvdd and Rvss until the gate oxide voltage of N1 is below the limit.
Based on the simulation diagram of fig. 3, a complete ESD protection circuit simulation flow is shown in fig. 6, and when ESD simulation is performed:
1. the ESD level that the chip needs to reach is determined. Such as 2000V, which is required to reach the HBM model.
2. The HBM 2000V current characteristic is obtained from the factory or customer.
3. Through mathematical modeling, the HBM 2000V current characteristic curve is fitted.
4. A current monitor Ifail and a voltage monitor Efail are inserted into the circuit.
5. The current limit and the voltage limit that can be tolerated by the device are obtained from the process plant and input into the respective current monitor Ifail and voltage monitor Efail.
6. Opening an Ifail switch of the current monitor to monitor the current in the ESD simulation
7. The simulation is started.
8. If the Ifail current of the current monitor exceeds the set limit value, a failure is reported. And then re-simulating after increasing the size of the ESD device.
9. And if the current of the current monitor Ifail does not exceed the set limit value, opening a voltage monitor Efail switch to monitor the voltage in the ESD simulation.
10. If the voltage of the voltage monitor Efail exceeds the set limit value, an effect error is reported. And then, reducing the resistance Rvdd of the power supply network and the resistance Rvss of the ground or increasing the size of a power supply clamp NMOS tube NESD in the ESD protection module, and re-simulating.
11. If the voltage monitor Efail voltage does not exceed the set limit value, the simulation ends.
Claims (5)
1. The simulation device of the chip ESD protection circuit is characterized by comprising an ESD excitation source, an ESD protection module and at least one functional module, wherein the ESD excitation source is connected between a power supply voltage VDD and a common grounding voltage VSS;
the ESD excitation source is used for loading ESD voltage according to a set ESD current characteristic curve;
the ESD protection module is internally provided with a power supply clamp NMOS tube NESD, the drain electrode of the power supply clamp NMOS tube NESD is provided with a current monitor Ifail connected with a power supply voltage VDD, and the source electrode of the power supply clamp NMOS tube NESD is connected with a common ground voltage VSS;
a CMOS tube N1 is arranged in the functional module, and a voltage monitor Efail is respectively arranged between the grid and the drain of the CMOS tube N1 and between the grid and the source;
a power supply network resistor Rvdd is arranged between a power supply voltage VDD from a bonding pad and the ESD protection module, and a grounding resistor Rvss is arranged between a common grounding voltage VSS from the bonding pad and the ESD protection module;
the current monitor Ifail is used for monitoring whether the current flowing through the ESD protection device reaches a limit value, if the current reaches the limit value, an error is reported, and the ESD protection module is optimized by increasing the size of a power supply clamp NMOS tube NESD in the ESD protection module;
the voltage monitor Efail is used for monitoring whether the voltage flowing through the ESD protection device reaches a limit value or not, if the voltage reaches the limit value, an error is reported, and the ESD protection module is optimized by reducing the resistance Rvdd of a power supply network and the resistance Rvss of a ground or increasing the size of a power supply clamp NMOS tube NESD in the ESD protection module.
2. The emulation device of the ESD protection circuit of claim 1, wherein the ESD protection module further comprises a capacitor C1 and a resistor R1; the gate of the power clamp NMOS NESD is connected to the power supply voltage VDD through a capacitor C1, and the gate is connected to the common ground voltage VSS through a resistor R1.
3. A simulation method of a chip ESD protection circuit, based on the simulation device of claim 1 or 2, comprising the steps of,
step 1, determining the ESD level required to be reached by a chip;
step 2, obtaining an ESD current characteristic curve for determining the ESD level from a factory or a customer;
step 3, fitting an ESD current characteristic curve through mathematical modeling;
step 4, obtaining the current limit value and the voltage limit value which can be borne by the device from a process plant, and inputting the current limit value and the voltage limit value into a corresponding current monitor Ifail and a corresponding voltage monitor Efail;
step 5, opening a current monitor Ifail switch, and monitoring the current in the ESD simulation;
step 6, starting an ESD excitation source, and starting simulation according to the fitted ESD current characteristic curve;
7, if the Ifail current of the current monitor exceeds the set limit value, reporting an actual effect error, then increasing the size of a power supply clamp NMOS tube NESD in the ESD protection module, and repeating the step 7 to simulate again;
step 8, if the current of the current monitor Ifail does not exceed the set limit value, a voltage monitor Efail switch is opened, and the voltage in the ESD simulation is monitored;
step 9, if the voltage of the voltage monitor Efail exceeds the set limit value, reporting an actual effect error, reducing the resistance Rvdd and the grounding resistance Rvss of the power supply network or increasing the size of a power supply clamp NMOS tube NESD in the ESD protection module, and re-simulating;
and step 10, if the voltage of the voltage monitor Efail does not exceed the set limit value, the ESD protection module is effective, and the simulation is finished.
4. The method for simulating the ESD protection circuit of the chip according to claim 3, wherein in step 1, the HBM model with the ESD level of 2000V to be achieved by the chip is determined.
5. The simulation method of the ESD protection circuit of the chip according to claim 3, wherein the step of fitting the ESD current characteristic curve in step 3 by mathematical modeling comprises the following steps,
step 3.1, describing the ESD current characteristic through the following mathematical formula to obtain a fitted current characteristic curve of the ESD excitation source;
when the Time is less than or equal to Td;
when Time > Td;
wherein, the Time is a Time coordinate in the ESD discharge process,
vhbm is a model voltage corresponding to the ESD level which is required to be achieved by the chip; τ 1 is a time constant of ESD current rising, τ 2 is a time constant of ESD current falling, and Td is a starting time point of ESD current falling trend;
and 3.2, adjusting the time parameters tau 1, tau 2 and Td to enable the current characteristic curve of the fitted ESD excitation source to be close to the ESD current characteristic curve provided by a factory, so as to obtain the fitted ESD current characteristic curve for the ESD excitation source.
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| CN111046621B (en) * | 2019-12-23 | 2021-08-10 | 北京大学 | ESD (electro-static discharge) behavior level model circuit of hysteresis device |
| CN113690153B (en) * | 2021-08-10 | 2023-10-31 | 深圳市华星光电半导体显示技术有限公司 | Method for preventing ESD from damaging TFT and preparation method of TFT |
| CN113723041B (en) * | 2021-09-01 | 2024-03-29 | 联芸科技(杭州)股份有限公司 | Insertion method and device of power supply clamping circuit and storage medium |
| CN113761818B (en) * | 2021-11-09 | 2022-02-11 | 微龛(广州)半导体有限公司 | ESD simulation method and simulation circuit |
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