CN111737937B - Semiconductor device modeling method - Google Patents
Semiconductor device modeling method Download PDFInfo
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Abstract
A semiconductor device modeling method is disclosed, comprising establishing a native transistor model and a parasitic transistor model, the native transistor model substrate being connected to the parasitic transistor model base and grounded through a substrate resistor; the drain electrode of the native transistor model and the collector electrode of the parasitic transistor are connected to the drain end of the semiconductor device through a drain end resistor; the source of the native transistor model and the emitter of the parasitic transistor are both connected to the source terminal of the semiconductor device. The native transistor model and the parasitic transistor model of the semiconductor device modeling method comprise collision ionization current formulas, the two collision ionization current formulas are arranged to ensure the lifting of the substrate voltage, the starting of the parasitic transistor model, the simulation of the snapback phenomenon and the parameter acquisition of an ESD device, and the model is simple, good in convergence and high in simulation speed.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a modeling method of a semiconductor device.
Background
With the continuous progress of the process, the gate oxide thickness of the device is continuously thinned, the internal circuit of the chip is more and more easily damaged by Static electricity, and the capability requirement on an electrostatic discharge (ESD) device including the circuit is also higher and higher. The gate-grounded NMOS (N-Metal-Oxide-Semiconductor) tube (GGNMOS) is the most widely used ESD device, and in order to ensure the reliability of ESD, the protection capability of the protection circuit of the GGNMOS needs to be accurately predicted, so as to optimize the circuit design, reduce the design period, and improve the reliability of the chip. SPICE (Simulation program with integrated circuit emphasis, a simulation circuit simulator) is the most common circuit-level simulation program, various software manufacturers provide Vspice, hspice, pspice different versions of SPICE software, simulation cores of which are different in size, and SPICE simulation algorithms developed by Berkeley university, california, usa are adopted, so that a semiconductor device modeling method can be used for simulation test through the program.
As shown in FIG. 1, curve L1 is the drain voltage V of a conventional MOS (metal-oxide semiconductor, metal oxide semiconductor) device D And drain current I D Is the drain voltage V of the ESD device D And drain current I D Wherein, the A1 area is a linear area, the A2 area is a saturated area, the A3 area is a snapback area, the A4 area is an avalanche breakdown area, in the A4 area, a conventional MOS device breaks down to generate a large number of hole electron pairs, hole current passes through substrate flow to the ground, and forms voltage drop on parasitic substrate resistance, thereby raising substrate potential, starting parasitic 'source-substrate-drain' NPN BJT, forming a current release path, generating voltage snapback phenomenon, reducing the voltage of a drain terminal to the voltage of the snapback area A3, improving charge release speed, timely releasing static electricity and protecting a chip. The inflection voltage of the A4 area corresponds to the starting voltage of the ESD, and the inflection voltage of the A3 area corresponds to the maintaining voltage of the ESD device.
The ability to predict GGNMOS requires the creation of accurate simulation models, especially accurate simulations of Snapback (Snapback) phenomena of ESD devices.
As shown in fig. 2, the gate G, source S and substrate 110 of the GGNMOS of the ESD device 100 are grounded, and the drain D receives the ESD current I ESD Drain region 122 receives ESD current I ESD Post-impact ionization current I gen Parasitic transistor B1, impact ionization current is discharged through the substrate, substrate current I sub Through the substrate resistance R sub Lifting the substrate resistance R sub Voltage, turn on parasitic transistor B1, ESD current I ESD Divided into parasitic channel currents I b And a native channel current I c The channels through the parasitic transistor B1 and the native transistor are released to the source region 121 to the source terminal S, respectively, and then to ground. In the GGNMOS device, the parasitic transistor B1 is a BJT (Bipolar Junction Transistor ), and the native transistor T1 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-Oxide-semiconductor field effect transistor).
As shown in fig. 3, the conventional GGNMOS modeling method divides the entire device into a native transistor T1, a parasitic transistor B1, and a impact ionization current source I GEN And a substrate resistance R sub The terminals include source S, drain D, gate G of the native transistor T1 and base B of the parasitic transistor B1, where the key focus of modeling is on impact ionization current source I GEN Is the impact ionization current I of (2) gen In the modeling of the conventional GGNMOS, the native transistor T1 (native transistor model) adopts a simple MOS model, the parasitic transistor B1 (parasitic transistor model) adopts a simple EM model or GP model, and the impact ionization current I gen Usually, verilog-A language is adopted for representation, the formula is complex, and the simulation speed is low.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a semiconductor device modeling method, thereby improving the simulation speed.
According to an aspect of the present invention, there is provided a semiconductor device modeling method including:
establishing a native transistor model, wherein a drain electrode of the native transistor model is connected to a drain end of the semiconductor device through a drain end resistor, a source electrode of the native transistor model is connected to a source end of the semiconductor device through a source end resistor, a gate electrode of the native transistor model is a gate electrode of the semiconductor device, and a substrate of the native transistor model is connected to the source end of the semiconductor device through a substrate resistor;
establishing a parasitic transistor model, wherein the base electrode of the parasitic transistor model is connected with the substrate of the native transistor, the collector electrode is connected to the drain end of the semiconductor device through the drain end resistor, the emitter electrode is connected to the source end of the semiconductor device through the source end resistor,
the parasitic transistor model is connected with the substrate resistor through the first substrate resistor, and the parasitic transistor model is connected with the substrate resistor through the substrate resistor.
Optionally, the native transistor model is a BSIM4 model including the first impact ionization current formula.
Optionally, the parasitic transistor model is a BJT model of VBIC including the second impact ionization current formula.
Optionally, the characterization formula of the substrate resistance is:
R sub ＝R0+R1*exp(-V ds )+R2*V ds *exp(-V ds )
wherein R0 is the initial value of the substrate resistor, R1 and R2 are correction terms related to voltage, R sub For substrate resistance, V ds Is the drain-source voltage.
Optionally, the parasitic transistor model is a HICUM BJT model.
Optionally, the parasitic transistor model is a MEXTRAM BJT model.
Optionally, the first impact ionization current formula of the native transistor model is characterized by Verilog-a.
Optionally, the second impact ionization current formula of the parasitic transistor model is characterized by Verilog-a.
The modeling method of the semiconductor device comprises the steps of establishing a native transistor model and a parasitic transistor model, wherein a native transistor model substrate is connected to a parasitic transistor model base electrode and grounded through a substrate resistor; the drain electrode of the native transistor model and the collector electrode of the parasitic transistor are connected to the drain end of the semiconductor device through a drain end resistor; the source of the native transistor model and the emitter of the parasitic transistor are both connected to the source terminal of the semiconductor device. The primary transistor model and the parasitic transistor model both comprise collision ionization current formulas, two collision ionization current formulas are set, the first collision ionization current and the second collision ionization current flow through the substrate resistor to raise the substrate voltage drop, the starting of the parasitic transistor model can be ensured, the simulation of the snapback phenomenon can be ensured, the convergence is improved, the parameter acquisition of the ESD device is ensured, and the model is simple, the convergence is good and the simulation speed is high.
The first collision ionization current formula of the native transistor model can be represented by Verilog-A, so that the simulation speed and convergence can be improved in the prior art, and the applicability of the semiconductor device modeling method is improved.
The second collision ionization current formula of the parasitic transistor model can be represented by Verilog-A, and the simulation speed and the convergence can be improved compared with the prior art, so that the applicability of the semiconductor device modeling method disclosed by the invention is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a volt-ampere characteristic of an ESD device according to the prior art;
figure 2 shows a cross-sectional view of a GGNMOS device according to the prior art;
FIG. 3 shows a schematic diagram of a model circuit structure of a GGNMOS model according to the prior art;
fig. 4 shows a schematic circuit structure of a GGNMOS model of a semiconductor device modeling method according to an embodiment of the present invention;
fig. 5 shows a volt-ampere characteristic of an ESD device obtained by a semiconductor device modeling method according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples.
Fig. 4 shows a schematic circuit structure of a GGNMOS model of a semiconductor device modeling method according to an embodiment of the present invention.
As shown in fig. 4, the GGNMOS model of the embodiment of the present invention divides the whole device into a native transistor T2 (native transistor model), a parasitic transistor B2 (parasitic transistor model), and a substrate resistance R sub Source end resistor R s And a drain resistor R d 。
The substrate of the native transistor T2 is connected to the base of the parasitic transistor B2 to output a first substrate current I sub The base of parasitic transistor B2 is connected to base current I b Substrate resistance R sub The current flowing upward is the total substrate current I sub_total The substrate resistor connects the substrate of the native transistor T2 and the base of the parasitic transistor B2 to the source terminal S, which is grounded, the drain terminal resistor R d The drain current on the transistor is I d The drain resistor is connected with the drain of the drain D and the native transistor T2 and the collector of the parasitic transistor B2, and the collector current of the parasitic transistor B2 is I c The current between the drain and the source of the native transistor T2 is I ds The source terminal resistor connects the source of the native transistor T2 and the emitter of the parasitic transistor B2 to the source terminal S. Drain terminal resistor R d Drain current I on d The ESD current at the drain input may be characterized.
The native transistor T2 is a BSIM4 model, and the equation of the self-contained impact ionization current Iii (the first impact ionization current equation) is:
wherein ALPHA0, ALPHA1 and BETA0 are model parameters, L eff For effective channel length, I ds To avoid collision ionization of drain D current, V ds Is the drain-source voltage, V dseff Is the effective drain-source voltage.
Equation (1) may characterize the first substrate current I in FIG. 4 sub I.e. I sub = Iii. Meanwhile, the invention adopts the VBIC model to represent the parasitic transistor B2, thereby avoiding the phenomenon that the parasitic transistor B2 can not be started by the combination of the collision ionization current of the simple EM or GP model and the BSIM4 model, and further the effect of snapback can not be achieved, and the collision ionization current I in the VBIC model program avc The formula (second impact ionization current formula) is:
I avc ＝I c *AVC1*(PC-V bci )*exp(-AVC2*(PC-V bci )*exp(MC-1)) (2)
in the formula (2), AVC1 and AVC2 are collision ionization parameters, PC and MC are capacitance parameters of a base electrode and a collector electrode of a transistor, I avc For the second substrate current, V bci In this embodiment, PC and MC are capacitance parameters of the base and collector of the parasitic transistor B2, which is the voltage between the base and collector inside the parasitic transistor B2.
The voltage dependence in the collision ionization current formulas of the formula (1) and the formula (2) is similar, parameters in the two models can better control the collision ionization current, and the first substrate current I sub And a second substrate current I avc Superposition to obtain total substrate current I sub_total And the substrate voltage drop is improved, the parasitic transistor B2 is started, and better simulation is obtained.
The embodiment adopts a VBIC model to represent the parasitic transistor B2, and can also adopt other models with collision ionization current formulas, such as a HICUM BJT model and a MEXTRAM BJT model.
For the substrate resistance R sub The present embodiment adopts the formula
R sub ＝R0+R1*exp(-V ds )+R2*V ds *exp(-V ds ) (3)
Characterising, in formula (3), R0 is the substrate resistance R sub R1 and R2 are correction terms related to voltage, V ds Is the drain-source voltage.
Fig. 5 shows a volt-ampere characteristic of an ESD device obtained by a semiconductor device modeling method according to an embodiment of the present invention.
As shown in the figure, the ESD device obtained by the GGNMOS model of the embodiment of the invention has the snapback phenomenon, namely the phenomenon that the voltage is increased and reduced and then increased in the process of gradually increasing the current, the secondary breakdown voltage is about 8V, the convergence is good, and only three formulas are adopted, so that the required parameters are less, and the simulation speed is high.
According to the modeling method of the semiconductor device, the BSIM4 model and the VBIC model are adopted to respectively represent the native transistor and the parasitic transistor, and the two models comprise collision ionization current formulas, so that the collision ionization current in the model can be more accurately represented, the parasitic BJT transistor is ensured to be started, the model simulation difficulty is simplified, and the model simulation speed and the model convergence are improved.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (8)
1. A method of modeling a semiconductor device, comprising:
establishing a native transistor model, wherein a drain electrode of the native transistor model is connected to a drain end of the semiconductor device through a drain end resistor, a source electrode of the native transistor model is connected to a source end of the semiconductor device through a source end resistor, a gate electrode of the native transistor model is a gate electrode of the semiconductor device, and a substrate of the native transistor model is connected to the source end of the semiconductor device through a substrate resistor;
establishing a parasitic transistor model, wherein the base electrode of the parasitic transistor model is connected with the substrate of the native transistor, the collector electrode is connected to the drain end of the semiconductor device through the drain end resistor, the emitter electrode is connected to the source end of the semiconductor device through the source end resistor,
the parasitic transistor model is connected with the substrate resistor through the first substrate resistor, and the parasitic transistor model is connected with the substrate resistor through the substrate resistor.
2. A method of modeling a semiconductor device according to claim 1, wherein,
the native transistor model is a BSIM4 model including the first impact ionization current formula.
3. A method of modeling a semiconductor device according to claim 1, wherein,
the parasitic transistor model is a BJT model of VBIC including the second impact ionization current formula.
4. The method of modeling a semiconductor device of claim 1, wherein the characterization formula for the substrate resistance is:
R sub ＝R0+R1*exp(-V ds )+R2*V ds *exp(-V ds )
wherein R0 is the initial value of the substrate resistor, R1 and R2 are correction terms related to voltage, R sub For substrate resistance, V ds Is the drain-source voltage.
5. A method of modeling a semiconductor device according to claim 1, wherein,
the parasitic transistor model is a HICUM BJT model.
6. The semiconductor device module of claim 1, wherein,
the parasitic transistor model is a MEXTRAM BJT model.
7. A method of modeling a semiconductor device according to claim 1, wherein,
the first impact ionization current formula of the native transistor model is characterized by Verilog-A.
8. A method of modeling a semiconductor device according to claim 1, wherein,
the second impact ionization current formula of the parasitic transistor model is characterized by Verilog-A.
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Citations (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006048525A (en) * | 2004-08-06 | 2006-02-16 | Toshiba Corp | Simulation method |
| JP2006100718A (en) * | 2004-09-30 | 2006-04-13 | Matsushita Electric Ind Co Ltd | Operation analyzing method for semiconductor integrated circuit device, analyzing apparatus used therefor, and optimization designing method using the apparatus |
| CN101169800A (en) * | 2007-10-29 | 2008-04-30 | 上海集成电路研发中心有限公司 | MOS transistor radio frequency circuit simulated macro model and its parameter extraction method |
| CN101221589A (en) * | 2007-09-29 | 2008-07-16 | 埃派克森微电子(上海)有限公司 | Circuit simulation model method |
| CN101706831A (en) * | 2009-06-12 | 2010-05-12 | 上海宏力半导体制造有限公司 | Circuit tolerance measure method in field of semiconductor design simulation |
| CN101726274A (en) * | 2009-12-01 | 2010-06-09 | 中国科学院上海微系统与信息技术研究所 | Method for determining width offset |
| CN102034865A (en) * | 2009-09-30 | 2011-04-27 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN102109570A (en) * | 2009-12-28 | 2011-06-29 | 中国科学院微电子研究所 | Method for measuring gate-source capacitance of field effect transistor under multiple biases |
| CN102637215A (en) * | 2011-02-10 | 2012-08-15 | 上海宏力半导体制造有限公司 | Modeling method of semiconductor device |
| CN102646147A (en) * | 2012-04-24 | 2012-08-22 | 中国科学院微电子研究所 | Modeling method of MOS device |
| CN102799721A (en) * | 2012-07-04 | 2012-11-28 | 上海宏力半导体制造有限公司 | Semiconductor device temperature coefficient modeling method and circuit design method |
| CN102956620A (en) * | 2012-12-03 | 2013-03-06 | 上海集成电路研发中心有限公司 | Testing structure and characterization method for junction capacitance of MOS (metal oxide semiconductor) transistor |
| CN103810311A (en) * | 2012-11-13 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Method for simulating bipolar transistor and bipolar transistor simulating circuit |
| CN104635135A (en) * | 2015-01-30 | 2015-05-20 | 中国科学院微电子研究所 | De-embedding method of compound semiconductor device |
| EP2899653A1 (en) * | 2014-01-28 | 2015-07-29 | IMEC vzw | Method, system and computer program product for characterizing the variability of an integrated circuit design |
| CN104881508A (en) * | 2014-11-27 | 2015-09-02 | 苏州能讯高能半导体有限公司 | Table look-up method-based modeling method and system of semiconductor device |
| CN105095537A (en) * | 2014-05-08 | 2015-11-25 | 无锡华润上华半导体有限公司 | Simulation model of high voltage device and modeling method for simulation model of high voltage device |
| CN105844059A (en) * | 2016-04-19 | 2016-08-10 | 成都海威华芯科技有限公司 | Modeling method of microwave high-power transistor |
| CN106124829A (en) * | 2016-06-29 | 2016-11-16 | 成都海威华芯科技有限公司 | Field-effect transistor dead resistance and the extracting method of raceway groove parameter |
| CN106709201A (en) * | 2017-01-06 | 2017-05-24 | 深圳市国微电子有限公司 | Circuit-level modeling method and model circuit which are used for GGNMOS |
| CN106951586A (en) * | 2017-02-15 | 2017-07-14 | 上海集成电路研发中心有限公司 | A kind of modeling method for the radio frequency MOS device for considering temperature effect |
| CN107622172A (en) * | 2017-10-13 | 2018-01-23 | 重庆大学 | The united compression joint type IGBT temperature field finite element modeling method of chip device level |
| CN107844644A (en) * | 2017-10-26 | 2018-03-27 | 上海集成电路研发中心有限公司 | A kind of method for establishing wafer pattern OPC model |
| WO2018054096A1 (en) * | 2016-09-20 | 2018-03-29 | 上海集成电路研发中心有限公司 | Method and system for testing optimization for semiconductor component and method and system for molding optimization |
| CN108509729A (en) * | 2018-04-04 | 2018-09-07 | 中国工程物理研究院电子工程研究所 | The emulation mode and system of characteristic after a kind of circuit irradiation to BJT devices |
| CN109063289A (en) * | 2018-07-19 | 2018-12-21 | 北京顿思集成电路设计有限责任公司 | The appraisal procedure of semiconductor devices |
| CN109101699A (en) * | 2018-07-19 | 2018-12-28 | 北京顿思集成电路设计有限责任公司 | The appraisal procedure of semiconductor devices |
| CN109143015A (en) * | 2018-07-19 | 2019-01-04 | 北京顿思集成电路设计有限责任公司 | Semiconductor devices dead resistance acquisition methods |
| CN111368490A (en) * | 2020-02-24 | 2020-07-03 | 杰华特微电子（杭州）有限公司 | Circuit model of transverse double-diffusion transistor and modeling method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5029096B2 (en) * | 2007-03-30 | 2012-09-19 | 富士通株式会社 | Power supply noise model generation method and power supply noise model generation apparatus |
-
2020
- 2020-07-16 CN CN202010686667.7A patent/CN111737937B/en active Active
Patent Citations (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006048525A (en) * | 2004-08-06 | 2006-02-16 | Toshiba Corp | Simulation method |
| JP2006100718A (en) * | 2004-09-30 | 2006-04-13 | Matsushita Electric Ind Co Ltd | Operation analyzing method for semiconductor integrated circuit device, analyzing apparatus used therefor, and optimization designing method using the apparatus |
| CN101221589A (en) * | 2007-09-29 | 2008-07-16 | 埃派克森微电子(上海)有限公司 | Circuit simulation model method |
| CN101169800A (en) * | 2007-10-29 | 2008-04-30 | 上海集成电路研发中心有限公司 | MOS transistor radio frequency circuit simulated macro model and its parameter extraction method |
| CN101706831A (en) * | 2009-06-12 | 2010-05-12 | 上海宏力半导体制造有限公司 | Circuit tolerance measure method in field of semiconductor design simulation |
| CN102034865A (en) * | 2009-09-30 | 2011-04-27 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN101726274A (en) * | 2009-12-01 | 2010-06-09 | 中国科学院上海微系统与信息技术研究所 | Method for determining width offset |
| CN102109570A (en) * | 2009-12-28 | 2011-06-29 | 中国科学院微电子研究所 | Method for measuring gate-source capacitance of field effect transistor under multiple biases |
| CN102637215A (en) * | 2011-02-10 | 2012-08-15 | 上海宏力半导体制造有限公司 | Modeling method of semiconductor device |
| CN102646147A (en) * | 2012-04-24 | 2012-08-22 | 中国科学院微电子研究所 | Modeling method of MOS device |
| CN102799721A (en) * | 2012-07-04 | 2012-11-28 | 上海宏力半导体制造有限公司 | Semiconductor device temperature coefficient modeling method and circuit design method |
| CN103810311A (en) * | 2012-11-13 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Method for simulating bipolar transistor and bipolar transistor simulating circuit |
| CN102956620A (en) * | 2012-12-03 | 2013-03-06 | 上海集成电路研发中心有限公司 | Testing structure and characterization method for junction capacitance of MOS (metal oxide semiconductor) transistor |
| EP2899653A1 (en) * | 2014-01-28 | 2015-07-29 | IMEC vzw | Method, system and computer program product for characterizing the variability of an integrated circuit design |
| CN105095537A (en) * | 2014-05-08 | 2015-11-25 | 无锡华润上华半导体有限公司 | Simulation model of high voltage device and modeling method for simulation model of high voltage device |
| CN104881508A (en) * | 2014-11-27 | 2015-09-02 | 苏州能讯高能半导体有限公司 | Table look-up method-based modeling method and system of semiconductor device |
| CN104635135A (en) * | 2015-01-30 | 2015-05-20 | 中国科学院微电子研究所 | De-embedding method of compound semiconductor device |
| CN105844059A (en) * | 2016-04-19 | 2016-08-10 | 成都海威华芯科技有限公司 | Modeling method of microwave high-power transistor |
| CN106124829A (en) * | 2016-06-29 | 2016-11-16 | 成都海威华芯科技有限公司 | Field-effect transistor dead resistance and the extracting method of raceway groove parameter |
| WO2018054096A1 (en) * | 2016-09-20 | 2018-03-29 | 上海集成电路研发中心有限公司 | Method and system for testing optimization for semiconductor component and method and system for molding optimization |
| CN106709201A (en) * | 2017-01-06 | 2017-05-24 | 深圳市国微电子有限公司 | Circuit-level modeling method and model circuit which are used for GGNMOS |
| CN106951586A (en) * | 2017-02-15 | 2017-07-14 | 上海集成电路研发中心有限公司 | A kind of modeling method for the radio frequency MOS device for considering temperature effect |
| CN107622172A (en) * | 2017-10-13 | 2018-01-23 | 重庆大学 | The united compression joint type IGBT temperature field finite element modeling method of chip device level |
| CN107844644A (en) * | 2017-10-26 | 2018-03-27 | 上海集成电路研发中心有限公司 | A kind of method for establishing wafer pattern OPC model |
| CN108509729A (en) * | 2018-04-04 | 2018-09-07 | 中国工程物理研究院电子工程研究所 | The emulation mode and system of characteristic after a kind of circuit irradiation to BJT devices |
| CN109063289A (en) * | 2018-07-19 | 2018-12-21 | 北京顿思集成电路设计有限责任公司 | The appraisal procedure of semiconductor devices |
| CN109101699A (en) * | 2018-07-19 | 2018-12-28 | 北京顿思集成电路设计有限责任公司 | The appraisal procedure of semiconductor devices |
| CN109143015A (en) * | 2018-07-19 | 2019-01-04 | 北京顿思集成电路设计有限责任公司 | Semiconductor devices dead resistance acquisition methods |
| CN111368490A (en) * | 2020-02-24 | 2020-07-03 | 杰华特微电子（杭州）有限公司 | Circuit model of transverse double-diffusion transistor and modeling method thereof |
Non-Patent Citations (3)
| Title |
|---|
| A theoretical model for calculating the effects of carrier heating with nonequilibrium hot phonons on semiconductor devices and the current-voltage relations;Chin-Yi Tsai;《Microelectronics Reliability》;第91卷(第2期);第335-343页 * |
| Modeling semiconductor devices by using Neuro Space Mapping;Mahdi Gordi Armaki, Seyed Ebrahim Hosseini;《Applied Mathematical Modelling》;第34卷(第11期);第3430-3438页 * |
| 深亚微米部分耗尽型SOI MOSFET的建模及特征提取方法;唐威;吴龙胜;刘存生;刘佑宝;;吉林大学学报(工学版)(第03期);全文 * |
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