CN111737937A - Modeling method of semiconductor device - Google Patents
Modeling method of semiconductor device Download PDFInfo
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- CN111737937A CN111737937A CN202010686667.7A CN202010686667A CN111737937A CN 111737937 A CN111737937 A CN 111737937A CN 202010686667 A CN202010686667 A CN 202010686667A CN 111737937 A CN111737937 A CN 111737937A
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Abstract
A modeling method of a semiconductor device is disclosed, which comprises establishing a native transistor model and a parasitic transistor model, wherein a substrate of the native transistor model is connected to a base electrode of the parasitic transistor model and is grounded through a substrate resistor; the drain electrode of the native transistor model and the collector electrode of the parasitic transistor are connected to the drain terminal of the semiconductor device through a drain terminal resistor; the source of the native transistor model and the emitter of the parasitic transistor are both connected to the source terminal of the semiconductor device. The native transistor model and the parasitic transistor model of the semiconductor device modeling method provided by the invention both comprise impact ionization current formulas, and the two impact ionization current formulas can ensure the rise of the substrate voltage, ensure the starting of the parasitic transistor model, ensure the simulation of the snapback phenomenon and ensure the acquisition of parameters of the ESD device, and the model is simple, good in convergence and high in simulation speed.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device modeling method.
Background
With the continuous advance of the process and the continuous reduction of the gate oxide thickness of the device, the internal circuit of the chip is more and more easily damaged by Static electricity, and the requirement on the capability of an ESD (Electro-Static discharge) device including a circuit is higher and higher. The gate-grounded NMOS (gate-grounded NMOS) is the most widely used ESD device, and in order to ensure ESD reliability, the protection capability of the protection circuit of the GGNMOS needs to be accurately predicted, so as to optimize the circuit design, reduce the design period, and improve the reliability of the chip. SPICE (Simulation program with integrated circuit simulator) is the most common circuit-level Simulation program, various software manufacturers provide different versions of SPICE software such as Vspice, Hspice, Pspice and the like, the Simulation cores of the SPICE software are different and the SPICE Simulation algorithm developed by Berkeley university of California of America is adopted, and the semiconductor device modeling method can be used for Simulation testing through the program.
As shown in fig. 1, a curve L1 represents a drain terminal voltage V of a conventional MOS (metal-oxide semiconductor) deviceDAnd a drain terminal current IDCurve L2 shows the drain voltage V of the ESD deviceDAnd a drain terminal current IDThe characteristic curve of (1), wherein the region a1 is a linear region, the region a2 is a saturation region, the region A3 is a snapback region, and the region a4 is an avalanche breakdown region, in the region a4, a conventional MOS device breaks down to generate a large number of hole electron pairs, the hole current flows to the ground through a substrate current, a voltage drop is formed on a parasitic substrate resistor, the substrate potential is raised, a parasitic source-substrate-drain NPN BJT is turned on to form a current release path, a voltage snapback phenomenon occurs, the drain voltage is reduced to the voltage of the snapback region A3, the charge release speed is increased, and electrostatic release is performed in time to protect the chip. The knee voltage of the A4 area corresponds to the ESD starting voltage, and the knee voltage of the A3 area corresponds to the maintaining voltage of the ESD device.
The ability to predict GGNMOS requires the establishment of accurate simulation models, particularly accurate simulation of the Snapback phenomenon of ESD devices.
As shown in fig. 2, the gate G, the source S and the substrate 110 of the GGNMOS of the ESD device 100 are grounded, and the drain D receives the ESD current IESDAnd drain region 122 receives ESD current IESDPost-generation impact ionization current IgenParasitic transistor B1, impact ionization current discharged through the substrate, substrate current IsubThrough-substrate resistance RsubRaising the substrate resistance RsubVoltage, turn on parasitic transistor B1, ESD current IESDDivided into parasitic channel currents IbAnd native channel current IcAnd is released to the source region 121 to the source terminal S and then to the ground through the channels of the parasitic transistor B1 and the native transistor, respectively. Wherein, in the GGNMOS device,the parasitic Transistor B1 is a BJT (Bipolar Junction Transistor), and the native Transistor T1 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
As shown in FIG. 3, the conventional GGNMOS modeling method divides the whole device into a native transistor T1, a parasitic transistor B1, and an impact ionization current source IGENAnd a substrate resistance RsubThe pigtails comprise the source S, drain D, gate G of the native transistor T1 and the base B of the parasitic transistor B1, wherein a key concern of the modeling is the impact ionization current source IGENImpact ionization current I ofgenIn the conventional GGNMOS modeling, the native transistor T1 (native transistor model) uses a simple MOS model, the parasitic transistor B1 (parasitic transistor model) uses a simple EM model or GP model, and the impact ionization current IgenThe method is generally characterized by adopting a Verilog-A language, and has the disadvantages of complex formula and slow simulation speed.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a semiconductor device modeling method, thereby improving the simulation speed.
According to an aspect of the present invention, there is provided a semiconductor device modeling method including:
establishing a native transistor model, wherein a drain electrode of the native transistor model is connected to a drain terminal of the semiconductor device through a drain terminal resistor, a source electrode of the native transistor model is connected to a source terminal of the semiconductor device through a source terminal resistor, a grid electrode of the semiconductor device is the grid electrode of the semiconductor device, and a substrate is connected to the source terminal of the semiconductor device through a substrate resistor;
establishing a parasitic transistor model, wherein the base electrode of the parasitic transistor model is connected with the substrate of the native transistor, the collector electrode is connected to the drain terminal of the semiconductor device through the drain terminal resistor, the emitter electrode is connected to the source terminal of the semiconductor device through the source terminal resistor,
the native transistor model and the parasitic transistor model respectively adopt a first impact ionization current formula and a second impact ionization current formula to respectively obtain a first substrate current and a second substrate current, and the first substrate current and the second substrate current are grounded through the substrate resistor to simulate and open the parasitic transistor model.
Optionally, the native transistor model is a BSIM4 model including the first impact ionization current formula.
Optionally, the parasitic transistor model is a BJT model of VBIC comprising the second impact ionization current formula.
Optionally, the characterization formula of the substrate resistance is:
Rsub＝R0+R1*exp(-Vds)+R2*Vds*exp(-Vds)
wherein R0 is the initial resistance value of the substrate resistance, R1 and R2 are correction terms related to the voltage, and RsubIs a substrate resistance, VdsIs the drain-source voltage.
Optionally, the parasitic transistor model is a HICUM BJT model.
Optionally, the parasitic transistor model is a MEXTRAM BJT model.
Optionally, the first impact ionization current formula of the native transistor model is characterized by Verilog-a.
Optionally, the second impact ionization current formula of the parasitic transistor model is characterized by Verilog-a.
The modeling method of the semiconductor device comprises the steps of establishing a primary transistor model and a parasitic transistor model, wherein a substrate of the primary transistor model is connected to a base electrode of the parasitic transistor model and is grounded through a substrate resistor; the drain electrode of the native transistor model and the collector electrode of the parasitic transistor are connected to the drain terminal of the semiconductor device through a drain terminal resistor; the source of the native transistor model and the emitter of the parasitic transistor are both connected to the source terminal of the semiconductor device. The primary transistor model and the parasitic transistor model respectively comprise an impact ionization current formula, two impact ionization current formulas are set, the first impact ionization current and the second impact ionization current flow through the substrate resistor, the substrate voltage drop is lifted, the opening of the parasitic transistor model can be guaranteed, the simulation of the snapback phenomenon is guaranteed, the convergence is improved, the parameter acquisition of the ESD device is guaranteed, and the model is simple, good in convergence and high in simulation speed.
The first impact ionization current formula of the native transistor model can be represented by Verilog-A, the simulation speed and convergence can be improved by the prior art, and the applicability of the semiconductor device modeling method is improved.
The second impact ionization current formula of the parasitic transistor model can be represented by Verilog-A, and compared with the prior art, the simulation speed and convergence can be improved, and the applicability of the semiconductor device modeling method is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a current-voltage characteristic of an ESD device according to the prior art;
fig. 2 shows a cross-sectional view of a GGNMOS device according to the prior art;
fig. 3 shows a schematic diagram of a model circuit structure of a GGNMOS model according to the prior art;
fig. 4 is a schematic circuit configuration diagram showing a GGNMOS model of a semiconductor device modeling method according to an embodiment of the present invention;
fig. 5 shows a current-voltage characteristic curve of an ESD device obtained by a semiconductor device modeling method according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 4 is a schematic circuit diagram showing a GGNMOS model of a semiconductor device modeling method according to an embodiment of the present invention.
As shown in fig. 4, the GGNMOS model of the embodiment of the present invention divides the entire device into a native transistor T2 (native transistor model), a parasitic transistor B2 (parasitic transistor model), and a substrate resistance RsubSource end resistance RsAnd a drain terminal resistor Rd。
The substrate of the native transistor T2 is connected to the base of the parasitic transistor B2 to output a first substrate current IsubThe base of the parasitic transistor B2 is connected to the base current IbSubstrate resistance RsubThe current flowing upwards is the total substrate current Isub_totalThe substrate resistor connects the substrate of the native transistor T2 and the base of the parasitic transistor B2 to the source terminal S, the source terminal S is grounded, and the drain terminal resistor RdCurrent at drain terminal is IdA drain resistor connected between the drain terminal D and the drain of the native transistor T2 and the collector of the parasitic transistor B2, wherein the collector current of the parasitic transistor B2 is IcThe current between the drain and the source of the native transistor T2 is IdsThe source terminal resistance connects the source of the native transistor T2 and the emitter of the parasitic transistor B2 to the source terminal S. Drain resistor RdOn the drain terminal current IdThe ESD current at the drain input can be characterized.
The native transistor T2 is a BSIM4 model, and the impact ionization current Iii formula (the first impact ionization current formula) of the model is:
wherein ALPHA0, ALPHA1 and BETA0 are model parameters, and L iseffFor effective channel length, IdsTo disregard the leakage D current of impact ionization, VdsIs the drain-source voltage, VdseffIs the effective drain-source voltage.
Equation (1) may characterize the first substrate current I in FIG. 4subI.e. IsubIii. Meanwhile, the parasitic transistor B2 is represented by the VBIC model, so that the phenomenon that the parasitic transistor B2 cannot be started and the snapback effect cannot be achieved due to the combination of the impact ionization current of the simple EM or GP model and the BSIM4 model is avoided, and the impact ionization current in the VBIC model programStream IavcThe formula (second impact ionization current formula) is:
Iavc＝Ic*AVC1*(PC-Vbci)*exp(-AVC2*(PC-Vbci)*exp(MC-1)) (2)
in equation (2), AVC1 and AVC2 are impact ionization parameters, PC and MC are capacitance parameters of transistor base and collector, IavcIs a second substrate current, VbciWhich is the voltage between the base and the collector inside the parasitic transistor B2, in the present embodiment, PC, MC are the capacitance parameters of the base and the collector of the parasitic transistor B2.
The voltage dependence in the impact ionization current formulas of the formula (1) and the formula (2) is similar, the parameters in the two models can better control the impact ionization current, and the first substrate current IsubAnd a second substrate current IavcThe total substrate current I is obtained by superpositionsub_totalAnd the substrate voltage drop is improved, and the parasitic transistor B2 is turned on, so that better simulation is obtained.
The present embodiment uses the VBIC model to characterize parasitic transistor B2, and can also use other models with impact ionization current formulas, such as HICUM BJT model and MEXTRAM BJT model.
For substrate resistance RsubIn this embodiment, the formula is adopted
Rsub＝R0+R1*exp(-Vds)+R2*Vds*exp(-Vds) (3)
Characterized in that in the formula (3), R0 is the substrate resistance RsubR1 and R2 are voltage-dependent correction terms, VdsIs the drain-source voltage.
Fig. 5 shows a current-voltage characteristic curve of an ESD device obtained by a semiconductor device modeling method according to an embodiment of the present invention.
As shown in the figure, the ESD device obtained by the GGNMOS model in the embodiment of the present invention has a snapback phenomenon, that is, a phenomenon that a voltage increases, decreases, and increases again in a process of a current gradually increasing, a secondary breakdown voltage is about 8V, a convergence is good, and only three formulas are adopted, so that a required parameter is small, and a simulation speed is high.
According to the semiconductor device modeling method, the BSIM4 model and the VBIC model are adopted to represent the native transistor and the parasitic transistor respectively, the two models respectively comprise the impact ionization current formula, so that the impact ionization current in the models can be more accurately represented, the starting of the parasitic BJT transistor is guaranteed, the model simulation difficulty is simplified, and the model simulation speed and the convergence are improved.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (8)
1. A method of modeling a semiconductor device, comprising:
establishing a native transistor model, wherein a drain electrode of the native transistor model is connected to a drain terminal of the semiconductor device through a drain terminal resistor, a source electrode of the native transistor model is connected to a source terminal of the semiconductor device through a source terminal resistor, a grid electrode of the semiconductor device is the grid electrode of the semiconductor device, and a substrate is connected to the source terminal of the semiconductor device through a substrate resistor;
establishing a parasitic transistor model, wherein the base electrode of the parasitic transistor model is connected with the substrate of the native transistor, the collector electrode is connected to the drain terminal of the semiconductor device through the drain terminal resistor, the emitter electrode is connected to the source terminal of the semiconductor device through the source terminal resistor,
the native transistor model and the parasitic transistor model respectively adopt a first impact ionization current formula and a second impact ionization current formula to respectively obtain a first substrate current and a second substrate current, and the first substrate current and the second substrate current are grounded through the substrate resistor to simulate and open the parasitic transistor model.
2. The semiconductor device modeling method of claim 1,
the native transistor model is a BSIM4 model that includes the first impact ionization current formula.
3. The semiconductor device modeling method of claim 1,
the parasitic transistor model is a BJT model of VBIC comprising the second impact ionization current formula.
4. The method of claim 1, wherein the characterization formula for the substrate resistance is:
Rsub＝R0+R1*exp(-Vds)+R2*Vds*exp(-Vds)
wherein R0 is the initial resistance value of the substrate resistance, R1 and R2 are correction terms related to the voltage, and RsubIs a substrate resistance, VdsIs the drain-source voltage.
5. The semiconductor device modeling method of claim 1,
the parasitic transistor model is a HICUM BJT model.
6. The semiconductor device module of claim 1,
the parasitic transistor model is a MEXTRAM BJT model.
7. The semiconductor device modeling method of claim 1,
a first impact ionization current formula of the native transistor model is characterized by adopting Verilog-A.
8. The semiconductor device modeling method of claim 1,
and a second impact ionization current formula of the parasitic transistor model is characterized by adopting Verilog-A.
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| CN115544940A (en) * | 2022-12-01 | 2022-12-30 | 全芯智造技术有限公司 | Dislocation simulation method and device, readable storage medium and terminal |
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