CN102956620A - Testing structure and characterization method for junction capacitance of MOS (metal oxide semiconductor) transistor - Google Patents
Testing structure and characterization method for junction capacitance of MOS (metal oxide semiconductor) transistor Download PDFInfo
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- CN102956620A CN102956620A CN2012105100755A CN201210510075A CN102956620A CN 102956620 A CN102956620 A CN 102956620A CN 2012105100755 A CN2012105100755 A CN 2012105100755A CN 201210510075 A CN201210510075 A CN 201210510075A CN 102956620 A CN102956620 A CN 102956620A
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Abstract
The invention relates to the technical field of a semiconductor, and discloses a testing structure and a characterization method for junction capacitance of an MOS (metal oxide semiconductor) transistor. Based on the traditional method for extraction of the junction capacitance of the MOS transistor, a testing structure for different design parameters is added. By measuring the junction capacitance of a first testing unit of a PN junction and a second testing unit of the MOS transistor with completely identical doping conditions, such parameters as the horizontal diffusion length, and the capacitance of every unit and the like of the doping in an active region of the MOS transistor are extracted accurately, and the junction capacitance of the MOS transistor or other MOS structures to be tested is accurately characterized. By adopting the testing structure and the characterization method, no specific dependence on characteristic dimensions of the MOS transistor is needed, high-precision characterization and modeling of the junction capacitance of the MOS transistor can still be ensured along with reduction of the characteristic dimensions of a semiconductor device and forward movement of a technological process node, and effective characterization of performances of the MOS transistor can be realized.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly the source in the MOS transistor/drain junction capacity measurement and characterization technique.
Background technology
Growth at full speed along with small size, low price, portable mobile communication and consumption electronic product demand, simple digital circuit product can't be satisfied the demand, mixed signal SOC (system on a chip) with analog circuit occupies more and more consequence in IC industry, the CMOS analog circuit progressively develops into the mixed-signal system of high speed, high complexity, low-work voltage from the circuit of low speed, low complex degree, small-signal, high working voltage.Meanwhile, dwindling of device size had higher requirement to the reduction of the various ghost effects of MOS transistor and the raising of signal to noise ratio.
In MOS transistor, source, leakage doped region are called active area, form PN junction between active area and the substrate, so exist parasitic PN junction electric capacity in the MOS transistor, and this parasitic capacitance has very important impact to the performance of MOS transistor.The active area junction capacitance of MOS transistor can be decomposed into three parts usually: the active area bottom capacitor, along the STI(shallow trench isolation from) the side electric capacity on border, and along the side electric capacity of channel boundary.These electric capacity are all closely related with area, shape and the doping section of PN junction.When the active area voltage of MOS transistor changes, electric capacity is with charge or discharge, and when MOS transistor is operated in the higher state of frequency, active area knot parasitic capacitance discharge and recharge the operating efficiency that will have a strong impact on circuit, thereby affect the high frequency characteristics of MOS transistor.In addition, the noise of substrate also will be tied parasitic capacitance along active area and pass to MOS transistor, and transmit to each branch road of MOS circuit in the loop that noise also will form by substrate and each parasitic capacitance, further has a strong impact on whole circuit performance.Therefore, the active area junction capacitance of MOS transistor is to weigh and optimize an important indicator of MOS transistor performance, and simultaneously, the accuracy of MOS transistor junction capacitance model also becomes a key factor that affects the MOS circuit design.
In the prior art, as shown in Figure 1, the MOS transistor of based semiconductor substrate 100 includes source region 110 and grid 120, and grid 120 sidewalls are coated with side wall 140, is surrounded with the STI shallow trench isolation from 130 around the MOS transistor.The junction capacitance of MOS transistor mainly comprises: active area 110 with the bottom junction capacitance at 210 places, Semiconductor substrate 100 interfaces, active area 110 and the side junction capacitance of STI shallow trench isolation from 220 places, 130 interfaces, and the side junction capacitance at active area 110 and MOS transistor channel interface 230 places.And to MOS transistor active area junction capacitance C
Bs Common bottom interface 210 area A by active area 110-Semiconductor substrate 100 of sign
rAnd the bottom area junction capacitance C of unit
Js, active area 110 and the border girth P of STI shallow trench isolation from 220 places, 130 interfaces
jAnd unit perimeter junction capacitance C
Jsw, MOS transistor active area 110 and channel interface 230 places border overall length W
TotalAnd the channel width junction capacitance C of unit
JswgRealize etc. parameter.Yet, in existing sign or modeling process, usually do not consider that horizontal proliferation length Δ L after active area injects is on the impact of PN junction girth and area between MOS transistor active area 110 and the substrate 100, or the approximate transverse diffusion distance of thinking that active area 110 injects equates with MOS transistor grid curb wall 140 width, considers accurately not that all the horizontal proliferation length Δ L of active area Implantation is for the impact of junction capacitance in MOS transistor junction capacitance sign of the prior art or the modeling method that is:.
Yet, along with constantly dwindling of feature sizes of semiconductor devices and constantly pushing ahead of manufacturing process node, device performance improves constantly sensitiveness of parameters, and the horizontal proliferation length that MOS transistor source, leakage are injected has very important material impact to accurate sign or the modeling of MOS transistor junction capacitance.
Summary of the invention
Technology to be solved by this invention is, a kind of MOS transistor junction capacitance test structure and characterizing method are provided, can take into full account the practical factors such as horizontal proliferation that MOS transistor preparation process intermediate ion injects, realization is to the accurate sign of MOS transistor junction capacitance, and can be applicable to provide more accurately MOS transistor junction capacitance model.
For solving the problems of the technologies described above, the invention provides a kind of MOS transistor junction capacitance test structure, this structure comprises the first test cell and the second test cell, and the first test cell comprises two or more PN junctions, and the second test cell comprises two or more MOS transistor.
As optional technical scheme, PN junction in the first test cell be have shallow trench isolation from longitudinal P N knot, all the doping condition with described MOS transistor active area is identical for the doping type in described PN junction ion implantation doping district, doping content, the Implantation degree of depth etc., described PN junction is with in described MOS transistor places identical Semiconductor substrate or doped well region, and two or more MOS transistor have identical lateral wall width described in the second test structure.
As optional technical scheme, the first test cell comprises two longitudinal P N knots, and described two PN junctions have different area and perimeters; The second test cell comprises two MOS transistor, and described two MOS transistor have different channel widths.
As optional technical scheme, the first test cell comprises n longitudinal P N knot, wherein, and n
1Individual PN junction the first equivalent PN junction, the n of forming in parallel
2Individual PN junction the second equivalent PN junction, n, the n of forming in parallel
1, n
2Be integer and n
1+ n
2=n＞2, the described first equivalent PN junction has different equivalent areas and equivalent perimeter from the described second equivalent PN junction.
As optional technical scheme, the second test cell comprises m MOS transistor, wherein, and m
1Individual MOS transistor cascade forms the first interdigitated MOS structure, m
2Individual MOS transistor cascade forms the second interdigitated MOS structure, m, m
1, m
2Be integer and m
1+ m
2=m＞2.In this technical scheme, optional, the first interdigitated MOS structure is identical with MOS transistor quantity in the second interdigitated MOS structure, and channel width is different; Optionally, the first interdigitated MOS structure is different with MOS transistor quantity in the second interdigitated MOS structure, and channel width is identical.
The present invention also provides a kind of MOS transistor junction capacitance characterizing method, may further comprise the steps:
The first test cell is provided, comprise two or more have shallow trench isolation from longitudinal P N knot;
Measure the junction capacitance of each PN junction in described the first test cell;
Area A according to each PN junction bottom interface in described the first test cell
RdAnd PN junction doped region and shallow trench isolation from border girth P
JdExtract unit are junction capacitance C
JsWith unit perimeter junction capacitance C
Jsw
The second test cell is provided, comprise two or more MOS transistor, all the doping condition with described PN junction ion implantation doping district is identical for the doping type of described MOS transistor active area, doping content, the Implantation degree of depth etc., and places in the Semiconductor substrate or doped well region identical with described PN junction;
Measure the junction capacitance of each MOS transistor in described the second test cell;
Lateral wall width SP, channel width W and active area border and horizontal proliferation length Δ L, active area and the channel width junction capacitance C of channel interface place unit apart from the doping of SA extraction active area that close on grid according to each MOS transistor in described the second test cell
Jswg
Characterize the MOS transistor junction capacitance.
As optional technical scheme, the junction capacitance C of each PN junction in the first test cell
dComprise bottom junction capacitance and shallow trench spacer sides electric capacity, and C
d=C
Js* A
Rd+ C
Jsw* P
Jd, wherein, A
RdBe described PN junction bottom interface area, C
JsBe described PN junction bottom interface unit are junction capacitance, P
JdBe the border girth of described PN junction doped region and shallow trench isolating interface, C
JswFor described PN junction doped region and shallow trench isolation from boundary unit perimeter junction capacitance.
Further, described the first test cell comprises n longitudinal P N knot, wherein, and n
1Individual PN junction the first equivalent PN junction, the n of forming in parallel
2Individual PN junction the second equivalent PN junction, n, the n of forming in parallel
1, n
2Be integer and n
1+ n
2=n＞2, the described first equivalent PN junction has different equivalent areas and equivalent perimeter from the described second equivalent PN junction; At this moment, only measure the first equivalent PN junction junction capacitance and the second equivalent PN junction junction capacitance in described the first test cell.
As optional technical scheme, the junction capacitance C of each MOS transistor in the second test cell
BsComprise bottom junction capacitance, shallow trench spacer sides electric capacity and raceway groove side electric capacity, and C
Bs=C
Js* A
r+ C
Jsw* P
j+ C
Jswg* W
Total, wherein, A
rBe described MOS transistor active area bottom interface area, C
JsBe described MOS transistor active area bottom interface unit are junction capacitance, P
jBe the border girth of described MOS transistor active area and shallow trench isolating interface, C
JswFor described MOS transistor active area and shallow trench isolation from unit perimeter junction capacitance at the interface, W
TotalBe the border overall length at described MOS transistor active area and channel interface place, C
JswgBe described MOS transistor active area and channel interface place unit channel width junction capacitance.
Further, described MOS transistor active area bottom interface area A
r=2 * W * (SA-SP+ Δ L), the border girth P of described MOS transistor active area and shallow trench isolating interface
j=4 * (SA-SP+ Δ L)+2W, the border overall length W at described MOS transistor active area and channel interface place
Total=2W, wherein, W is described MOS transistor channel width, and SA is described MOS transistor active area border and the distance of closing on grid, and SP is the lateral wall width of described MOS transistor, and Δ L is the horizontal proliferation length that described MOS transistor active area mixes.
Further, the second test cell comprises m MOS transistor, wherein, and m
1Individual MOS transistor cascade forms the first interdigitated MOS structure, m
2Individual MOS transistor cascade forms the second interdigitated MOS structure, m, m
1, m
2Be integer and m
1+ m
2=m＞2, and described the first interdigitated MOS structure has different MOS transistor quantity or different channel widths from described the second interdigitated MOS structure; At this moment, only measure the first interdigitated MOS structure junction capacitance and the second interdigitated MOS structure junction capacitance in described the second test cell.
Further, the MOS transistor junction capacitance of described sign is applicable to active area doping type, doping content, the Implantation degree of depth etc., and all the doping condition with described PN junction ion implantation doping district is identical, and places the Semiconductor substrate identical with described PN junction or the MOS structure in the doped well region.The measurement of junction capacitance adopts capacitor voltage characteristic measuring instrument or digital capacitance tester to realize in the first test cell, the second test cell.
The invention has the advantages that, the MOS transistor junction capacitance test structure that provides and characterizing method are based on one group of identical longitudinal P N knot of doping condition and MOS transistor, on the basis of conventional MOS transistor junction electric capacity extracting method, increased the test structure of different designs parameter, that is: the MOS transistor of the PN junction of different area and girth and different channel widths or comprise the interdigitated MOS structure of different crystal pipe quantity, extract by test and relevant parameter to the PN junction junction capacitance, consider in the technical process because the parametric variable that horizontal proliferation effect etc. are introduced, characterize more exactly the junction capacitance of MOS transistor.In addition, compared with prior art, test structure provided by the invention and characterizing method do not have specific dependence to the characteristic size of MOS transistor, along with dwindling of feature sizes of semiconductor devices and pushing ahead of manufacturing process node, still can guarantee the characterized with good accuracy to the MOS transistor junction capacitance, this characterizing method is significant to Accurate Model and the parameter extraction of the modeling and simulating of MOS device, particularly MOS transistor junction capacitance, and more accurately device model can be provided for the optimal design of MOS circuit.
Description of drawings
Fig. 1 is MOS transistor junction capacitance test schematic diagram in the prior art;
Fig. 2 is the present invention the first test cell longitudinal P N knot cross-sectional view;
Fig. 3 is the present invention the first test cell longitudinal P N knot domain structure schematic diagram;
Fig. 4 is the present invention's the second test cell MOS transistor cross-sectional view;
Fig. 5 is the present invention's the second test cell interdigitated MOS structural profile structural representation;
Fig. 6 is the present invention's the second test cell interdigitated MOS structure domain structure schematic diagram;
Fig. 7 is MOS transistor junction capacitance characterizing method flow chart of steps of the present invention;
Fig. 8 is the C of match in the MOS transistor junction capacitance characterizing method of the present invention
Bs'-W curve synoptic diagram.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing embodiments of the present invention are described in further detail.Those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be used by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
The present invention's the first embodiment provides a MOS transistor junction capacitance test structure.
The MOS transistor junction capacitance test structure that this embodiment provides comprises the first test cell and the second test cell.
The first test cell comprise two or more have shallow trench isolation from longitudinal P N knot, Fig. 2 is this PN junction cross-sectional view.As shown in Figure 2, this PN junction places on the Semiconductor substrate 100, has a doped region 101, and is surrounded with shallow trench isolation from 130 around the doped region 101.In this embodiment, Semiconductor substrate 100 is that the first semiconductor type mixes, and the doped region 101 of PN junction is that the second semiconductor type mixes.As shown in Figure 2, the doped region 101 of PN junction has the bottom junction capacitance with bottom interface 201 places of Semiconductor substrate 100, and this bottom interface area is A
Rd, its unit are junction capacitance is C
Js Doped region 101 and the shallow trench isolation of PN junction have the side junction capacitance from 202 places, 130 interfaces, and the border girth at this interface 202 is P
Jd, its unit perimeter junction capacitance is C
Jsw, the junction capacitance C of longitudinal P N shown in Figure 2 knot then
d=C
Js* A
Rd+ C
Jsw* P
JdAs another embodiment, also replaceable on the Semiconductor substrate 100 is the well region that the first semiconductor type mixes, and described PN junction doped region 101 is formed in this well region, and doped region 101 contacts with well region and forms longitudinal P N knot.
As optional execution mode, the first test cell comprises two longitudinal P N knots, and Fig. 3 is the first test cell PN junction domain structure schematic diagram.As shown in Figure 3, the first test cell comprises based semiconductor substrate 100, is surrounded with the first PN junction D of shallow trench isolation from 130
1With the second PN junction D
2, doped region 101 contacts with Semiconductor substrate 100 and forms longitudinal P N knot.In the present embodiment, the first PN junction D
1With the second PN junction D
2Has different area and perimeters, that is: the first PN junction D
1With the second PN junction D
2Have different junction capacitance, measure respectively the first PN junction D
1Junction capacitance C
D1With the second PN junction D
2Junction capacitance C
D2, can extract PN junction bottom unit are junction capacitance C in this structure
JsWith shallow trench isolation from border units girth junction capacitance C
Jsw
As preferred forms, the first test cell comprises n longitudinal P N knot, wherein, and n
1Individual PN junction the first equivalent PN junction, the n of forming in parallel
2Individual PN junction the second equivalent PN junction, n, the n of forming in parallel
1, n
2Be integer and n
1+ n
2=n＞2, and the first equivalent PN junction has different equivalent areas and equivalent perimeter from the second equivalent PN junction.In this execution mode, unit are junction capacitance C in bottom in the measurement of the first equivalent PN junction and the second equivalent PN junction junction capacitance and the PN junction structure
JsWith shallow trench isolation from border units girth junction capacitance C
JswExtraction identical with foregoing description, do not repeat them here.It is to be noted, compare with the measurement of single PN junction junction capacitance, adopt a plurality of PN junctions equivalent area, equivalent perimeter that forms equivalent PN junction in parallel to have comparatively flexibly alternative and larger parameter area, therefore, the junction capacitance certainty of measurement of equivalence PN junction structure is higher, the bottom unit are junction capacitance C that extracts under this execution mode
JsWith shallow trench isolation from border units girth junction capacitance C
JswMore accurate.
The second test cell comprises two or more MOS transistor.Fig. 4 is MOS transistor cross-sectional view in the second test cell.As shown in Figure 4, described MOS transistor places on the Semiconductor substrate 100 of the first semiconductor type doping, is source/leakage symmetrical structure, and is surrounded with shallow trench isolation on every side from 130.MOS transistor includes source region 110 and grid 120, grid 120 sidewalls are coated with side wall 140, wherein, side wall 140 width of MOS transistor are SP, active area 110 is the Second Type semiconductor doping, the distance of active area 110 borders and adjacent gate 120 is SA, and the horizontal proliferation length of active area 110 ion implantation dopings is Δ L.In this embodiment, each MOS transistor of the second test cell has identical lateral wall width SP.As another embodiment, Semiconductor substrate 100 is also replaceable to be the well region that the first semiconductor type mixes, and this MOS transistor places described well region, and it is long that each MOS transistor has identical grid in the second test cell.
In this embodiment, the doping type of MOS transistor active area 110, doping content, the Implantation degree of depth etc. are all identical with the doping condition in PN junction ion implantation doping district 101 in the first test cell, and MOS transistor places on the identical Semiconductor substrate 100 with PN junction, that is: MOS transistor active area 110 equates with PN junction bottom interface unit are junction capacitance in the first test cell with the bottom interface 210 unit are junction capacitance of Semiconductor substrate 100; MOS transistor active area 110 and shallow trench isolation PN junction doped region 101 in 130 interface boundaries, 220 place's unit perimeter junction capacitance and the first test cell equates from 130 boundary unit perimeter junction capacitance with shallow trench isolation.Except above-mentioned two at the interface the junction capacitance, the main junction capacitance of MOS transistor also includes the junction capacitance at source region 110 and MOS transistor channel interface 230 places, and the border overall length at described MOS transistor active area and channel interface place is W
Total, this unit channel width junction capacitance is C
JswgAs shown in Figure 4, in the second test cell, the junction capacitance of each MOS transistor:
C
bs=C
js×A
r+C
jsw×P
j+C
jswg×W
total，
As optional execution mode, the second test cell comprises the first MOS transistor M
1, the second MOS transistor M
2, and described first, second MOS transistor has different channel width W
1, W
2, that is: the first MOS transistor M
1With the second MOS transistor M
2Has different junction capacitance.
For single MOS transistor:
A
r＝2×W×(SA-SP＋ΔL)；P
j＝4×(SA-SP＋ΔL)＋2W；W
total＝2×W。Wherein, W is the MOS transistor channel width.
Measure the first MOS transistor M in the second test cell
1With the second MOS transistor M
2Junction capacitance, according to two MOS transistor junction capacitance expression formulas and channel width value match C
Bs-W curve can extract horizontal proliferation length Δ L and the MOS transistor active area 110 and the channel interface 230 channel width junction capacitance C of place unit of MOS transistor active area 110 ion implantation dopings in the second test cell
JswgThereby, further characterize out MOS transistor junction capacitance under the same process parameter.
As preferred forms, the second test cell comprises m MOS transistor, wherein, and m
1Individual MOS transistor cascade forms the first interdigitated MOS structure M
1', m
2Individual MOS transistor cascade forms the second interdigitated MOS structure M
2', m, m
1, m
2Be integer and m
1+ m
2=m＞2.Wherein, the first interdigitated MOS structure M
1' and the second interdigitated MOS structure M
2' MOS transistor quantity identical, channel width is different, or MOS transistor quantity is different, channel width is identical; That is: in the second test cell, the first interdigitated MOS structure M
1' and the second interdigitated MOS structure M
2' have different junction capacitance.
Fig. 5 is interdigitated MOS structural profile structural representation, and Fig. 6 is interdigitated MOS structure domain structure schematic diagram.
Such as Fig. 5, shown in Figure 6, described interdigitated MOS structure places on the Semiconductor substrate 100, and is surrounded with shallow trench isolation on every side from 130, in order to Semiconductor substrate 100 on other device isolation.This comprises in the interdigitated MOS structure of a plurality of MOS transistor cascades, adjacent two MOS transistor share an active area 110, the distance of active area 110 borders and adjacent gate 120 is SA, the distance of adjacent two grids 120 is PS in the interdigitated MOS structure, side wall 140 width are SP, and the horizontal proliferation length of active area 110 Implantations is Δ L.As most preferred embodiment, in the interdigitated MOS structure, it is long that the grid 120 of each MOS transistor has identical grid, and the side wall 140 of cover gate 120 sidewalls has identical lateral wall width, and each MOS transistor has identical channel width W in the interdigitated MOS structure.
As shown in Figure 5, junction capacitance in the interdigitated MOS structure mainly comprises: the bottom junction capacitance at each MOS transistor active area 110 and 210 places, Semiconductor substrate 100 interfaces, each MOS transistor active area 100 and the side junction capacitance of shallow trench isolation from 130 interface boundaries, 220 places, and the side junction capacitance at each MOS transistor active area 100 and MOS transistor channel interface 230 places.The junction capacitance of interdigitated MOS structure: C then
Bs'=C
Js* A
r'+C
Jsw* P
j'+C
Jswg* W
Total', wherein, A
r' be described interdigitated MOS structure active area 110 bottom interface 210 gross areas, C
JsBe described interdigitated MOS structure active area 110 bottom interface 210 unit are junction capacitance, P
j' be described interdigitated MOS structure active area 110 and the border overall circumference of shallow trench isolation from 130 interfaces 220, C
JswFor described interdigitated MOS structure active area 110 and shallow trench isolation from 130 interfaces, 220 place's unit perimeter junction capacitance, W
Total' be the border overall length at described interdigitated MOS structure active area 110 and channel interface 230 places, C
JswgBe described interdigitated MOS structure active area 110 and channel interface 230 place unit's channel width junction capacitance.
As shown in Figure 6, in conjunction with interdigitated MOS structural profile structural representation shown in Figure 5 as can be known, in the interdigitated MOS structure that comprises the individual MOS transistor cascade of m ', described interdigitated MOS structure active area 110 bottom interface 210 gross areas:
A
r’＝W×[(PS-2SP＋2ΔL)×(m’-1)＋2(SA-SP＋ΔL)]；
Described interdigitated MOS structure active area 110 and the border overall circumference of shallow trench isolation from 130 interfaces 220: P
j'=2 * (PS-2SP+2 Δ L) * (m '-1)+4 (SA-SP+ Δ L)+2W;
The border overall length at described interdigitated MOS structure active area 110 and channel interface 230 places:
W
total’＝2W×m’。
Further, in the interdigitated MOS structure, each MOS transistor is the source and leaks symmetrical structure, and each MOS transistor adopts identical process conditions preparation, each grid appearance etc.
Seen from the above description, in this embodiment, measure respectively the first interdigitated MOS structure junction capacitance C in the second test cell
Bs1' and the second interdigitated MOS structure junction capacitance C
Bs2', according to the design parameter of the second test cell, can extract horizontal expanding length Δ L and the active area 110 and the channel interface 230 channel width junction capacitance C of place unit of active area 110 ion implantation dopings in the second test cell
JswgThereby, the accurate sign of realization MOS transistor junction capacitance.
It is to be noted, in the MOS transistor test structure that this embodiment provides, the active area of MOS transistor has identical doping condition in PN junction doped region in the first test cell and the second test cell, thereby guarantees the accuracy of finishing the electric capacity characterization result.
The MOS transistor junction capacitance test structure that this embodiment provides is based on one group of identical longitudinal P N knot of doping condition and MOS transistor, on the basis of conventional MOS transistor junction Test Constructure of, increased the test structure of different designs parameter, that is: the MOS transistor of the PN junction of different area and girth and different channel widths or comprise the interdigitated MOS structure of different crystal pipe quantity, extract by test and relevant parameter to the PN junction junction capacitance, consider in the technical process because the parametric variable that horizontal proliferation effect etc. are introduced, characterize more exactly the junction capacitance of MOS transistor.The test structure that this embodiment provides does not have specific dependence to the characteristic size of MOS transistor, along with dwindling of feature sizes of semiconductor devices and pushing ahead of manufacturing process node, still can guarantee the high precision measurement to the MOS transistor junction capacitance, realize the accurate sign to the MOS transistor junction capacitance.
The present invention's the second embodiment provides a MOS transistor junction capacitance characterizing method.
The MOS transistor junction capacitance characterizing method flow chart of steps that Fig. 7 provides for this embodiment.
As shown in Figure 7, the MOS transistor junction capacitance characterizing method that provides of this embodiment may further comprise the steps:
Step S1: the first test cell is provided, comprise two or more have shallow trench isolation from longitudinal P N knot.
In this step, in the first test cell the PN junction structure as shown in Figure 2, each PN junction all places on the Semiconductor substrate 100, has a doped region 101, and is surrounded with shallow trench isolation from 130 around the doped region 101.In addition, Semiconductor substrate 100 is that the first semiconductor type mixes, and the doped region 101 of PN junction is that the second semiconductor type mixes.The doped region that it should be noted that each longitudinal P N knot in the first test cell has the doping conditions such as identical doping type, doping content and the Implantation degree of depth, and places in the identical Semiconductor substrate or doped well region.
As optional execution mode, the first test cell comprises two longitudinal P N knots.As shown in Figure 3, the first test cell comprises based semiconductor substrate 100, is surrounded with the first PN junction D of shallow trench isolation from 130
1With the second PN junction D
2, doped region 101 contacts with Semiconductor substrate 100 and forms longitudinal P N knot.In the present embodiment, the first PN junction D
1With the second PN junction D
2Has different area and perimeters.
As preferred forms, the first test cell comprises n longitudinal P N knot, wherein, and n
1Individual PN junction the first equivalent PN junction, the n of forming in parallel
2Individual PN junction the second equivalent PN junction, n, the n of forming in parallel
1, n
2Be integer and n
1+ n
2=n＞2, and the first equivalent PN junction has different equivalent areas and equivalent perimeter from the second equivalent PN junction.
Step S2: the junction capacitance of measuring each PN junction in described the first test cell.
In this step, when the first test cell comprises two longitudinal P N knots, measure respectively the first PN junction D
1Junction capacitance C
D1With the second PN junction D
2Junction capacitance C
D2When the first test cell comprises a plurality of longitudinal P N knot, measure respectively the first equivalent PN junction D
1' junction capacitance C
D1' and the second PN junction D
2' junction capacitance C
D2'.The measurement of above-mentioned first each junction capacitance of test cell adopts capacitor voltage characteristic measuring instrument, digital capacitance tester or other this areas capacitance characteristic measuring instrument commonly used to realize.
Step S3: extract each PN junction bottom interface unit are junction capacitance C in the first test cell
Js, side at the interface PN junction doped region and shallow trench isolation from border units girth junction capacitance C
Jsw
In this step, by in longitudinal P N junction structure shown in Figure 2 and the first embodiment to the description of the first test structure junction capacitance as can be known, the junction capacitance C of each PN junction in the first test cell
dMainly comprise bottom junction capacitance and shallow trench spacer sides electric capacity, and C
d=C
Js* A
Rd+ C
Jsw* P
Jd, wherein, A
RdBe described PN junction bottom interface 201 areas, C
JsBe described PN junction bottom interface 201 unit are junction capacitance, P
JdBe described PN junction doped region 101 and the border girth of shallow trench isolation from 130 interfaces 202, C
JswFor described PN junction doped region 101 and shallow trench isolation from 130 interfaces, 202 place's unit perimeter junction capacitance.
As optional execution mode, the first test cell comprises two longitudinal P N knots, according to the first PN junction D that measures among the step S2
1Junction capacitance C
D1With the second PN junction D
2Junction capacitance C
D2Simultaneous equations:
, A wherein
Rd1, A
Rd2Be respectively the first PN junction D
1With the second PN junction D
2Bottom interface 201 areas, P
Jd1, P
Jd2Be respectively the first PN junction D
1With the second PN junction D
2Knot doped region 101 and the border girth of shallow trench isolation from 130 interfaces 202, A
Rd1, A
Rd2, P
Jd1, P
Jd2Be the design parameter of the first test cell.Can extract the bottom interface 201 unit are junction capacitance that obtain PN junction doped region in described the first test cell 101 and Semiconductor substrate 100 according to above-mentioned simultaneous equations
, PN junction doped region 101 and the shallow trench isolation interface 202 place's unit perimeter junction capacitance from 130
As preferred forms, the first test cell comprises a plurality of longitudinal P N knots, measures n among the step S2
1Individual PN junction the first equivalent PN junction D that forms in parallel
1' junction capacitance C
D1' and the second equivalent PN junction D
2' junction capacitance C
D2'.In this execution mode, the first equivalent PN junction D
1' and the second equivalent PN junction D
2' equivalent area A
Rd1', A
Rd2' and equivalent perimeter P
Jd1', P
Jd2' all can directly extract according to the design parameter of each PN junction in the first test cell unit are junction capacitance C in bottom in the measurement of its junction capacitance and the PN junction structure
JsWith shallow trench isolation from border units girth junction capacitance C
JswExtraction identical with foregoing description, do not repeat them here.It is to be noted, compare with the measurement of single PN junction junction capacitance, adopt a plurality of PN junctions equivalent area, equivalent perimeter that forms equivalent PN junction in parallel to have comparatively flexibly alternative and larger parameter area, therefore, the junction capacitance certainty of measurement of equivalence PN junction structure is higher, the bottom unit are junction capacitance C that extracts under this execution mode
JsWith shallow trench isolation from border units girth junction capacitance C
JswMore accurate.
Step S4: the second test cell is provided, comprises two or more MOS transistor.
In this step, in the second test cell each MOS transistor cross-section structure as shown in Figure 4, described MOS transistor places on the Semiconductor substrate 100 that the first semiconductor type mixes, and is source/leakage symmetrical structure, and is surrounded with shallow trench isolation on every side from 130.MOS transistor includes source region 110 and grid 120, grid 120 sidewalls are coated with side wall 140, wherein, side wall 140 width of MOS transistor are SP, active area 110 is the Second Type semiconductor doping, the distance of active area 110 borders and adjacent gate 120 is SA, and the horizontal proliferation length of active area 110 ion implantation dopings is Δ L.In this embodiment, each MOS transistor of the second test cell has identical grid length and lateral wall width SP.
In this step, the doping type of MOS transistor active area 110, doping content, the Implantation degree of depth etc. are all identical with the doping condition in PN junction ion implantation doping district 101 in the first test cell, and MOS transistor places on the identical Semiconductor substrate 100 with PN junction, that is: MOS transistor active area 110 equates with PN junction bottom interface unit are junction capacitance in the first test cell with the bottom interface 210 unit are junction capacitance of Semiconductor substrate 100; MOS transistor active area 110 and shallow trench isolation PN junction doped region 101 in 130 interface boundaries, 220 place's unit perimeter junction capacitance and the first test cell equates from 130 boundary unit perimeter junction capacitance with shallow trench isolation.Except above-mentioned two at the interface the junction capacitance, the main junction capacitance of MOS transistor also includes the junction capacitance at source region 110 and MOS transistor channel interface 230 places, and the border overall length at described MOS transistor active area and channel interface place is W
Total, this unit channel width junction capacitance is C
Jswg
As optional execution mode, the second test cell comprises two MOS transistor: the first MOS transistor M
1, the second MOS transistor M
2, and described first, second MOS transistor has different channel width W
1, W
2, that is: the first MOS transistor M
1With the second MOS transistor M
2Has different junction capacitance.
As preferred forms, the second test cell comprises m MOS transistor, wherein, and m
1Individual MOS transistor cascade forms the first interdigitated MOS structure, m
2Individual MOS transistor cascade forms the second interdigitated MOS structure, m, m
1, m
2Be integer and m
1+ m
2=m＞2.Wherein, the MOS transistor quantity of the first interdigitated MOS structure and the second interdigitated MOS structure is identical, channel width is different, or MOS transistor quantity is different, channel width is identical; That is: in the second test cell, the first interdigitated MOS structure has different junction capacitance with the second interdigitated MOS structure.
Step S5: the junction capacitance of measuring each MOS transistor in described the second test cell.
In this step, when the second test cell comprises two MOS transistor, measure respectively the first MOS transistor M
1Junction capacitance C
Bs1With the second MOS transistor M
2Junction capacitance C
Bs2When the second test cell comprises a plurality of MOS transistor, measure respectively the first interdigitated MOS structure M
1' junction capacitance C
Bs1' and the second interdigitated MOS structure M
2' junction capacitance C
Bs2'.The measurement of above-mentioned second each junction capacitance of test cell adopts capacitor voltage characteristic measuring instrument, digital capacitance tester or other this areas capacitance characteristic measuring instrument commonly used to realize.
Step S6: extract each MOS transistor active area mixes in described the second test cell horizontal proliferation length Δ L, active area and the channel width junction capacitance C of channel interface place unit
Jswg
In this step, by in MOS transistor cross-sectional view shown in Figure 4 and the first embodiment to the description of the second test structure junction capacitance as can be known, the junction capacitance C of each MOS transistor in the second test cell
BsThe side electric capacity that mainly comprises bottom junction capacitance, shallow trench spacer sides electric capacity and active area and channel interface place, and C
Bs=C
Js* A
r+ C
Jsw* P
j+ C
Jswg* W
Total, wherein, A
rBe described MOS transistor active area 110 and Semiconductor substrate 100 bottom interface 210 areas, C
JsBe described MOS transistor active area 110 and Semiconductor substrate 100 bottom interface 210 unit are junction capacitance, P
jBe described MOS transistor active area 110 and the border girth of shallow trench isolation from 130 interfaces 220, C
JswFor described MOS transistor active area 110 and shallow trench isolation from 130 interfaces, 220 place's unit perimeter junction capacitance, W
TotalBe the border overall length of described MOS transistor active area 110 with channel interface 230 places, C
JswgBe described MOS transistor active area 110 and channel interface 230 place unit's channel width junction capacitance.
As optional execution mode, the second test cell comprises two MOS transistor, according to the first MOS transistor M that measures among the step S5
1Junction capacitance C
Bs1With the second MOS transistor M
2Junction capacitance C
Bs2Simultaneous equations:
, wherein: A
r=2W * (SA-SP+ Δ L), P
j=4 * (SA-SP+ Δ L)+2W, W
Total=2W, then:
C
Bs=Δ L (C
Js2W+4C
Jsw)+C
Jswg2W+C
Js2W (SA-SP)+C
Jsw[4 (SA-SP)+2W], wherein: SA is the distance of MOS transistor active area 110 frontier distance adjacent gate 130, SP is grid curb wall 140 width, W is the MOS transistor channel width, above-mentioned each parameter is MOS transistor design parameter or technological parameter, can directly extract or by live width scanning electron microscopy, high precision electro sub-microscope etc. each mos transistor measurement of the second test cell be obtained.Can extract the horizontal proliferation length Δ L that obtains MOS transistor doped region 110 ion implantation dopings in described the second test cell according to above-mentioned simultaneous equations and relevant parameter, MOS transistor active area 110 and the MOS transistor channel interface 230 channel width junction capacitance C of place unit
Jswg
As preferred forms, the second test cell comprises a plurality of MOS transistor, measures among the step S5 to comprise m
1The first interdigitated MOS structure M of individual MOS transistor cascade
1' junction capacitance C
Bs1' and comprise m
2The second interdigitated MOS structure M of individual MOS transistor cascade
2' junction capacitance C
Bs2'.The junction capacitance C of interdigitated MOS structure
Bs'=C
Js* A
r'+C
Jsw* P
j'+C
Jswg* W
Total', wherein, A
r' be described interdigitated MOS structure active area 110 bottom interface 210 gross areas, C
JsBe described interdigitated MOS structure active area 110 bottom interface 210 unit are junction capacitance, P
j' be described interdigitated MOS structure active area 110 and the border overall circumference of shallow trench isolation from 130 interfaces 220, C
JswFor described interdigitated MOS structure active area 110 and shallow trench isolation from 130 interfaces, 220 place's unit perimeter junction capacitance, W
Total' be the border overall length at described interdigitated MOS structure active area 110 and channel interface 230 places, C
JswgBe described interdigitated MOS structure active area 110 and channel interface 230 place unit's channel width junction capacitance.Further, as shown in Figure 6, in conjunction with interdigitated MOS structural profile structural representation shown in Figure 5 as can be known, in the interdigitated MOS structure that comprises the individual MOS transistor cascade of m ', interdigitated MOS structure active area 110 bottom interface 210 gross areas:
A
r’＝W×[(PS-2SP＋2ΔL)×(m’-1)＋2(SA-SP＋ΔL)]；
Described interdigitated MOS structure active area 110 and the border overall circumference of shallow trench isolation from 130 interfaces 220: P
j'=2 * (PS-2SP+2 Δ L) * (m '-1)+4 (SA-SP+ Δ L)+2W;
The border overall length W at described interdigitated MOS structure active area 110 and channel interface 230 places
Total'=2W * m '.
As optional embodiment, the first interdigitated MOS structure M
1' and the second interdigitated MOS structure M
2' have identical MOS transistor quantity and different channel widths, that is: a m
1=m
2, W
1≠ W
2, bringing each parameter expression of interdigitated MOS structure into interdigitated MOS structure junction capacitance expression formula, can be reduced to: C
Bs'=f
1(C
Jswg, Δ L) and W+f
2(Δ L), wherein, f
1(C
Jswg, Δ L) and by parameter Δ L and C
JswgDetermine f
2(Δ L) determined by parameter Δ L, according to the first interdigitated MOS structure M that measures
1' junction capacitance C
Bs1' and the second interdigitated MOS structure M
2' junction capacitance C
Bs2', match C
Bs'-W curve, as shown in Figure 8, intercept f
2(Δ L) can extract the horizontal proliferation length Δ L of active area 110 ion implantation dopings in the second test cell, again by slope f
1(C
Jswg, Δ L) and can extract the channel width junction capacitance C of unit at active area in the second test cell 110 and MOS transistor channel interface 230 places
Jswg
As another optional embodiment, the first interdigitated MOS structure M
1' and the second interdigitated MOS structure M
2' have different MOS transistor quantity and identical channel width, that is: a m
1≠ m
2, W
1=W
2, bringing each parameter expression of interdigitated MOS structure into interdigitated MOS structure junction capacitance expression formula, can be reduced to: C
Bs'=f
3(C
Jswg, Δ L) and m '+f
4(Δ L), wherein, f
3(C
Jswg, Δ L) and by parameter Δ L and C
JswgDetermine f
4(Δ L) determined by parameter Δ L, according to the first interdigitated MOS structure M that measures
1' junction capacitance C
Bs1' and the second interdigitated MOS structure M
2' junction capacitance C
Bs2', match C
Bs'-m ' curve, intercept f
4(Δ L) can extract the horizontal proliferation length Δ L of active area 110 ion implantation dopings in the second test cell, again by slope f
3(C
Jswg, Δ L) and can extract the channel width junction capacitance C of unit at active area in the second test cell 110 and MOS transistor channel interface 230 places
Jswg
It is to be noted, in this execution mode, compare with the measurement of single MOS transistor junction capacitance, the interdigitated MOS structural parameters that adopt a plurality of MOS transistor cascades to form are chosen has comparatively flexibly alternative and larger parameter area, therefore, the junction capacitance certainty of measurement of interdigitated MOS structure is higher, the channel width junction capacitance C of unit at the horizontal proliferation length Δ L of active area 110 ion implantation dopings in the second test cell that extracts under this execution mode and active area 110 and MOS transistor channel interface 230 places
JswgMore accurate.
Step S7: characterize the MOS transistor junction capacitance.
In this step, according to parameters such as the constituent parts junction capacitance of extracting among step S3, the S6 and horizontal proliferation length, can directly characterize MOS transistor junction capacitance: C
Bs=C
Js* A
r+ C
Jsw* P
j+ C
Jswg* W
Total, at this moment, A
r, P
j, W
TotalFor MOS transistor active area bottom interface area to be characterized, active area and shallow trench isolation from interface boundary girth and active area and channel interface place border overall length.This characterization result is applicable to active area doping type, doping content, the Implantation degree of depth etc., and all the doping condition with described PN junction ion implantation doping district is identical, and places the Semiconductor substrate identical with described PN junction or the MOS structure in the doped well region.
As optional embodiment, this step comprises: a MOS structure to be measured is provided, characterizes described MOS structure junction capacitance to be measured.At this moment, described MOS structure active area doping type to be measured, doping content, the Implantation degree of depth are all identical with described the second test cell, and described MOS structure to be measured places in the Semiconductor substrate or doped well region identical with first, second test cell.Under above-mentioned same process parameter, described MOS structure to be measured equates with the active area Implantation horizontal proliferation length Δ L of MOS transistor in the second test cell, and MOS structure to be measured has the bottom interface unit junction capacitance C identical with PN junction in the first test cell
Js, with shallow trench isolation from boundary unit perimeter junction capacitance C
Jsw, have simultaneously the unit channel width junction capacitance C identical with MOS transistor in the second test cell
Jswg, associated transverse diffusion length Δ L and constituent parts junction capacitance according to the first test cell, the second test cell extract in conjunction with the design parameter of MOS structure to be measured, can accurately record the MOS structure junction capacitance to be measured of telling.
In this step, MOS structure to be measured can be single MOS transistor, also can be for comprising the interdigitated MOS structure of a plurality of MOS transistor cascades.Identical with interdigitated MOS structure junction capacitance expression formula about MOS transistor in the second test structure in the expression formula of single MOS transistor and interdigitated MOS structure junction capacitance and this embodiment, do not repeat them here.
In this embodiment, providing or preparing order of the first test cell, the second test cell, MOS structure to be measured is not subjected to the above-mentioned steps sequence limit, and above-mentioned each semiconductor structure can adopt that identical process conditions interlock system is standby to be finished.Simultaneously, the extraction order of MOS transistor junction capacitance in the extraction of PN junction junction capacitance in the first test cell, the second test cell is not subjected to the above-mentioned steps sequence limit equally, can adjust arbitrarily junction capacitance extraction order according to test condition and layout design.
The MOS transistor junction capacitance characterizing method that this embodiment provides is based on one group of identical longitudinal P N knot of doping condition and MOS transistor, on the basis of conventional MOS transistor junction electric capacity extracting method, increased the test structure of different designs parameter, that is: the MOS transistor of the PN junction of different area and girth and different channel widths or comprise the interdigitated MOS structure of different crystal pipe quantity, by PN junction junction capacitance and relevant parameter are extracted, consider in the technical process because the parametric variable that horizontal proliferation effect etc. are introduced, characterize more exactly the junction capacitance of MOS transistor.The test structure that this embodiment provides and characterizing method do not have specific dependence to the characteristic size of MOS transistor, along with dwindling of feature sizes of semiconductor devices and pushing ahead of manufacturing process node, still can guarantee the high precision measurement to the MOS transistor junction capacitance, realize the accurate sign to the MOS transistor junction capacitance.
It needs to be noted, the MOS transistor junction capacitance characterizing method that this embodiment provides further is applicable to the semiconductor device building model and simulation, can be used for accurately setting up MOS device junction capacitance model, and extraction relevant parameter, and this characterizing method does not rely on special process node and device size, and is significant in the performance characterization of MOS device and circuit, optimal design.
Although pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (18)
1. a MOS transistor junction capacitance test structure comprises the first test cell and the second test cell, it is characterized in that:
Described the first test cell comprises two or more PN junctions;
Described the second test cell comprises two or more MOS transistor.
2. MOS transistor junction capacitance test structure according to claim 1 is characterized in that, the PN junction in described the first test cell be have shallow trench isolation from longitudinal P N knot.
3. MOS transistor junction capacitance test structure according to claim 2, it is characterized in that, the doping type in described PN junction ion implantation doping district, doping content, the Implantation degree of depth all doping type, doping content, the Implantation degree of depth with described MOS transistor active area are identical, and described PN junction is with in described MOS transistor places identical Semiconductor substrate or doped well region.
4. MOS transistor junction capacitance test structure according to claim 3 is characterized in that, two or more MOS transistor have identical lateral wall width described in the second test cell.
5. MOS transistor junction capacitance test structure according to claim 4 is characterized in that, described the first test cell comprises two longitudinal P N knots, and described two PN junctions have different area and perimeters.
6. MOS transistor junction capacitance test structure according to claim 4 is characterized in that, described the first test cell comprises n longitudinal P N knot, wherein, and n
1Individual PN junction the first equivalent PN junction, the n of forming in parallel
2Individual PN junction the second equivalent PN junction, n, the n of forming in parallel
1, n
2Be integer and n
1+ n
2=n＞2, the described first equivalent PN junction has different equivalent areas and equivalent perimeter from the described second equivalent PN junction.
7. MOS transistor junction capacitance test structure according to claim 4 is characterized in that, described the second test cell comprises two MOS transistor, and described two MOS transistor have different channel widths.
8. MOS transistor junction capacitance test structure according to claim 4 is characterized in that, described the second test cell comprises m MOS transistor, wherein, and m
1Individual MOS transistor cascade forms the first interdigitated MOS structure, m
2Individual MOS transistor cascade forms the second interdigitated MOS structure, m, m
1, m
2Be integer and m
1+ m
2=m＞2.
9. MOS transistor junction capacitance test structure according to claim 8 is characterized in that, described the first interdigitated MOS structure is identical with MOS transistor quantity in the second interdigitated MOS structure, and channel width is different.
10. MOS transistor junction capacitance test structure according to claim 8 is characterized in that, described the first interdigitated MOS structure is different with MOS transistor quantity in the second interdigitated MOS structure, and channel width is identical.
11. a MOS transistor junction capacitance characterizing method is characterized in that, may further comprise the steps:
The first test cell is provided, comprise two or more have shallow trench isolation from longitudinal P N knot;
Measure the junction capacitance of each PN junction in described the first test cell;
Extract each PN junction bottom interface unit are junction capacitance C in described the first test cell
Js, PN junction doped region and shallow trench isolation from border units girth junction capacitance C
Jsw
The second test cell is provided, comprise two or more MOS transistor, the doping type of described MOS transistor active area, doping content, the Implantation degree of depth all doping type, doping content, the Implantation degree of depth with described PN junction ion implantation doping district are identical, and place in the Semiconductor substrate or doped well region identical with described PN junction;
Measure the junction capacitance of each MOS transistor in described the second test cell;
Extract each MOS transistor active area mixes in described the second test cell horizontal proliferation length Δ L, active area and the channel width junction capacitance C of channel interface place unit
Jswg
Characterize the MOS transistor junction capacitance.
12. MOS transistor junction capacitance characterizing method according to claim 11 is characterized in that, the junction capacitance C of each PN junction in described the first test cell
dComprise bottom junction capacitance and shallow trench spacer sides electric capacity, and C
d=C
Js* A
Rd+ C
Jsw* P
Jd, wherein, A
RdBe described PN junction bottom interface area, C
JsBe described PN junction bottom interface unit are junction capacitance, P
JdBe the border girth of described PN junction doped region and shallow trench isolating interface, C
JswFor described PN junction doped region and shallow trench isolation from boundary unit perimeter junction capacitance.
13. MOS transistor junction capacitance characterizing method according to claim 12 is characterized in that, described the first test cell comprises n longitudinal P N knot, wherein, and n
1Individual PN junction the first equivalent PN junction, the n of forming in parallel
2Individual PN junction the second equivalent PN junction, n, the n of forming in parallel
1, n
2Be integer and n
1+ n
2=n＞2, the described first equivalent PN junction has different equivalent areas and equivalent perimeter from the described second equivalent PN junction; At this moment, only measure the first equivalent PN junction junction capacitance and the second equivalent PN junction junction capacitance in described the first test cell.
14. MOS transistor junction capacitance characterizing method according to claim 11 is characterized in that, the junction capacitance C of each MOS transistor in described the second test cell
BsComprise bottom junction capacitance, shallow trench spacer sides electric capacity and raceway groove side electric capacity, and C
Bs=C
Js* A
r+ C
Jsw* P
j+ C
Jswg* W
Total, wherein, A
rBe described MOS transistor active area bottom interface area, C
JsBe described MOS transistor active area bottom interface unit are junction capacitance, P
jBe the border girth of described MOS transistor active area and shallow trench isolating interface, C
JswFor described MOS transistor active area and shallow trench isolation from unit perimeter junction capacitance at the interface, W
TotalBe the border overall length at described MOS transistor active area and channel interface place, C
JswgBe described MOS transistor active area and channel interface place unit channel width junction capacitance.
15. MOS transistor junction capacitance characterizing method according to claim 14 is characterized in that, described MOS transistor active area bottom interface area A
r=2 * W * (SA-SP+ Δ L), the border girth P of described MOS transistor active area and shallow trench isolating interface
j=4 * (SA-SP+ Δ L)+2W, the border overall length W at described MOS transistor active area and channel interface place
Total=2W, wherein, W is described MOS transistor channel width, and SA is described MOS transistor active area border and the distance of closing on grid, and SP is the lateral wall width of described MOS transistor, and Δ L is the horizontal proliferation length that described MOS transistor active area mixes.
16. MOS transistor junction capacitance characterizing method according to claim 14 is characterized in that described the second test cell comprises m MOS transistor, wherein, and m
1Individual MOS transistor cascade forms the first interdigitated MOS structure, m
2Individual MOS transistor cascade forms the second interdigitated MOS structure, m, m
1, m
2Be integer and m
1+ m
2=m＞2, and described the first interdigitated MOS structure has different MOS transistor quantity or different channel widths from described the second interdigitated MOS structure; At this moment, only measure the first interdigitated MOS structure junction capacitance and the second interdigitated MOS structure junction capacitance in described the second test cell.
17. the described MOS transistor junction capacitance of any one characterizing method according to claim 10 ~ 16, it is characterized in that, the MOS transistor junction capacitance of described sign is applicable to active area doping type, doping content, the Implantation degree of depth, and all doping type, doping content, the Implantation degree of depth with described PN junction ion implantation doping district is identical, and places the Semiconductor substrate identical with described PN junction or the MOS structure in the doped well region.
18. MOS transistor junction capacitance characterizing method according to claim 17 is characterized in that, the extraction of junction capacitance adopts capacitor voltage characteristic measuring instrument or digital capacitance tester to measure realization in described the first test cell, the second test cell.
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| CN112685983A (en) * | 2020-12-29 | 2021-04-20 | 中国科学院上海微系统与信息技术研究所 | On-chip capacitor modeling method |
| CN113642277A (en) * | 2021-08-10 | 2021-11-12 | 中国科学院上海微系统与信息技术研究所 | Grid parasitic capacitance modeling method |
| CN113838835A (en) * | 2021-09-08 | 2021-12-24 | 长鑫存储技术有限公司 | Layout structure for testing junction capacitance and design method thereof |
| WO2023035453A1 (en) * | 2021-09-08 | 2023-03-16 | 长鑫存储技术有限公司 | Layout structure for testing junction capacitor, and design method therefor |
| CN113838835B (en) * | 2021-09-08 | 2024-05-03 | 长鑫存储技术有限公司 | Layout structure for testing junction capacitance and design method thereof |
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