CN112366145A - Test structure and test method for AC calibration - Google Patents
Test structure and test method for AC calibration Download PDFInfo
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- CN112366145A CN112366145A CN202011154146.3A CN202011154146A CN112366145A CN 112366145 A CN112366145 A CN 112366145A CN 202011154146 A CN202011154146 A CN 202011154146A CN 112366145 A CN112366145 A CN 112366145A
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- 238000012360 testing method Methods 0.000 title claims abstract description 131
- 238000010998 test method Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000003990 capacitor Substances 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims description 67
- 230000003071 parasitic effect Effects 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 11
- 101000595467 Homo sapiens T-complex protein 1 subunit gamma Proteins 0.000 claims description 5
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
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- 239000004065 semiconductor Substances 0.000 description 2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
Abstract
A test structure and a test method for AC calibration are provided, wherein a second test structure is provided and is positioned on a substrate and respectively used as an N-type heavily doped region of a source electrode and a drain electrode; a gate electrode between the source and drain electrodes; an STI region is formed in the substrate below the gate and between the source and drain. Testing the first test structure by adopting a Cgc test method to obtain a capacitor C1; providing a second test structure and a first test structure which does not comprise an STI region under a grid electrode, and testing the second test structure by adopting a Cgc test method to obtain capacitance C2; subtracting the capacitor C2 in the second step from the capacitor C1 to obtain a gate oxide capacitor C3; and calculating the equivalent electrical thickness of the gate oxide layer by using a capacitance formula. The invention utilizes the testing structure that the grid electrode is across on the STI to ensure that the channel under the grid oxide layer can not form an inversion or weak inversion, thereby eliminating the capacitance between the real grid oxide layer and the polysilicon grid electrode, and utilizes the Cgc capacitance testing method to accurately calculate the capacitance of the grid oxide layer so as to accurately calculate the electrical thickness of the grid oxide layer, thereby solving the problem of AC calibration.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a test structure for AC calibration.
Background
In the semiconductor chip process, the performance requirements are stable and improved due to the continuous shrinking of the component size. The calculation of the parasitic capacitance of the device is a difficult problem for both planar MOSFETs and finfets. However, the problem that the parasitic capacitance is larger and larger due to the continuous size reduction has already reached a considerable level, so that accurate calculation of the parasitic capacitance is critical, and generally, two conventional solutions are available: one is that an empirical coefficient is directly multiplied on the basis of the measured capacitance to achieve a relatively reasonable capacitance value, so the method cannot accurately reflect the condition of the parasitic capacitance and is not easy to find the problem; the second method is to design the calibration test key testkey to subtract so as to calculate the parasitic capacitance as much as possible, but some parasitic capacitances are difficult to subtract, such as the capacitance Cf between the gate and the source and the drain and the capacitance Cctg between the gate and the contact hole, so that the parasitic capacitances cannot be completely subtracted, and the calculation is biased. The problems of calculating the equivalent electrical thickness of the gate oxide layer by utilizing the capacitance of the gate oxide layer and using the equivalent electrical thickness for AC calibration generated by the method need to be solved urgently.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a test structure and a test method for AC calibration, which are used to solve the problem that the common test method in the prior art causes inaccurate test of equivalent electrical thickness of a gate oxide layer, and thus cannot be accurately used for AC calibration test.
To achieve the above and other related objects, the present invention provides a test structure and a test method for AC calibration, including at least:
a first test structure: the first test structure includes at least: a substrate; the N-type heavily doped regions are positioned on the substrate and respectively used as a source electrode and a drain electrode; the grid electrode is positioned between the upper surface of the substrate and the N-type heavily doped region; contact holes are respectively formed in the source drain electrode and the grid electrode; the contact holes are respectively provided with metal; the metal on the contact holes on the source and the drain electrodes is respectively connected with a bonding pad;
a second test structure; the second test structure includes at least: a substrate; the N-type heavily doped regions are positioned on the substrate and respectively used as a source electrode and a drain electrode; the grid electrode is positioned between the upper surface of the substrate and the N-type heavily doped region; an STI region is formed in the substrate below the grid electrode and between the source electrode and the drain electrode; contact holes are respectively formed in the source drain electrode and the grid electrode; the contact holes are respectively provided with metal; and the metal on the contact holes on the source and the drain electrodes is respectively connected with a bonding pad.
Preferably, the substrates of the first and second test structures are grounded; the contact holes connected with the grid electrodes in the first test structure and the second test structure are provided with metal on a first metal layer; the contact holes connected with the source and the drain in the first test structure and the second test structure are provided with metal on the contact holes in the first metal layer.
Preferably, in the first and second test structures, the metal on the contact hole connected to the gate is connected to a voltage signal, respectively.
The invention also provides a test method for AC calibration, which comprises the following steps:
step one, providing the first test structure, and testing the first test structure by adopting a Cgc test method to obtain a capacitor C1;
step two, providing the second test structure, and testing the second test structure by adopting a Cgc test method to obtain a capacitor C2;
step three, subtracting the capacitor C2 in the step two from the capacitor C1 in the step one to obtain a gate oxide capacitor C3;
and step four, calculating the equivalent electrical thickness of the gate oxide layer by using a capacitance formula.
Preferably, the capacitance C1 in step one comprises gate oxide capacitance and parasitic capacitance.
Preferably, the capacitor in the second step is a parasitic capacitor.
Preferably, the parasitic capacitance in the second step includes a capacitance Cf between the gate and the source/drain, a capacitance Cov between the gate and the STI region under the gate, a capacitance Cctg between the gate and the contact hole, and a capacitance Cm2p between the gate and the metal connected to the contact hole on the source/drain; and the capacitance Cm2m between the metal connected with the contact hole on the grid electrode and the metal connected with the contact hole on the source/drain electrode.
Preferably, the method for obtaining the capacitance C1 of the first test structure by using the Cgc test method in the step one comprises the following steps: (1) applying an alternating voltage small signal on the metal connected to the gate of the first test structure; (2) collecting current signals through a test pad on the metal connected to a source or drain of the first test structure; (3) integrating the collected current with time to calculate the charge amount; (4) calculating the capacitance C1 of the first test result according to the relation between the voltage and the charge quantity,
wherein, I1 is a current signal, and U1 is a voltage signal.
Preferably, the method for obtaining the capacitance C2 of the second test structure by using the Cgc test method in the step two comprises the following steps: (a) applying an alternating voltage small signal on the metal connected to the gate of the second test structure; (b) collecting current signals through a test pad on the metal connected with a contact hole of a source or a drain of the second test structure; (c) integrating the collected current with time to calculate the charge amount; (d) calculating the parasitic capacitance C2 of the calibration test key according to the relation between the voltage and the charge quantity,
wherein, I2 is a current signal, and U2 is a voltage signal.
Preferably, the voltage signal applied in step (1) or step (a) is a voltage signal having a frequency of 100 KHz.
Preferably, the equivalent electrical thickness of the gate oxide layer in the fourth step is the electrical thickness of the gate oxide layer.
As described above, the test structure and test method for AC calibration of the present invention have the following advantages: the invention utilizes the testing structure that the grid electrode is across on the STI to ensure that the channel under the grid oxide layer can not form an inversion or weak inversion, thereby successfully eliminating the capacitance between the real grid oxide layer and the polysilicon grid electrode, and utilizes the Cgc capacitance testing method to accurately calculate the capacitance of the grid oxide layer so as to accurately calculate the electrical thickness of the grid oxide layer, thereby solving the problem of AC calibration.
Drawings
FIG. 1 is a schematic diagram of a first test structure according to the present invention;
FIG. 2 is a schematic diagram of a second test structure according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides a test structure for AC calibration, the test structure for AC calibration comprising at least:
a first test structure: the first test structure includes at least: a substrate; the N-type heavily doped regions are positioned on the substrate and respectively used as a source electrode and a drain electrode; the grid electrode is positioned between the upper surface of the substrate and the N-type heavily doped region; contact holes are respectively formed in the source drain electrode and the grid electrode; the contact holes are respectively provided with metal; the metal on the contact holes on the source and the drain electrodes is respectively connected with a bonding pad; as shown in fig. 1, fig. 1 is a schematic diagram of a first test structure according to the present invention. The first test structure in this embodiment comprises: a substrate B; n-type heavily doped regions (N +) which are respectively used as source and drain electrodes and are positioned on the substrate B; the grid (polysilicon Poly) is positioned between the upper surface of the substrate B and the N-type heavily doped region (N +); contact holes CT are respectively arranged on the source drain electrode (N +) and the grid electrode (Poly); the contact holes are respectively provided with metal M1; and the metal M1 on the contact hole CT on the source and the drain are respectively connected with a PAD PAD.
The test structure for AC calibration in the present invention further comprises a second test structure; the second test structure in the present invention comprises at least: a substrate; the N-type heavily doped regions are positioned on the substrate and respectively used as a source electrode and a drain electrode; the grid electrode is positioned between the upper surface of the substrate and the N-type heavily doped region; an STI region is formed in the substrate below the grid electrode and between the source electrode and the drain electrode; contact holes are respectively formed in the source drain electrode and the grid electrode; the contact holes are respectively provided with metal; and the metal on the contact holes on the source and the drain electrodes is respectively connected with a bonding pad. As shown in fig. 2, fig. 2 is a schematic diagram of a second test structure in the present invention. The second test structure in this embodiment includes: a substrate B; n-type heavily doped regions (N +) which are respectively used as source and drain electrodes and are positioned on the substrate B; the grid (polysilicon Poly) is positioned between the upper surface of the substrate B and the N-type heavily doped region (N +); an STI region (STI) is formed in the substrate B below the gate electrode Poly and between the source electrode and the drain electrode (N +); contact holes CT are respectively arranged on the source drain electrode (N +) and the grid electrode Poly; the contact holes CT are respectively provided with metal M1; and the metal on the contact holes on the source and the drain electrodes is respectively connected with a PAD PAD.
Further to the present invention, the substrates B of the first test structure and the second test structure in this embodiment are both grounded; the contact holes CT connected with the grid electrodes in the first test structure and the second test structure are provided with metal on a first metal layer; the contact holes connected with the source and the drain in the first test structure and the second test structure are provided with metal on the contact holes in the first metal layer. That is, in the first test structure, the metal M1 connected to the gate through the contact hole CT and the metal M1 connected to the source and drain through the contact hole CT in the first test structure are both in the same metal layer, i.e., the first metal layer M1. In the invention, the contact holes in the first test structure and the second test structure are filled with metal.
Still further, in the first and second test structures in this embodiment, the metal on the contact hole connected to the gate is connected to a voltage signal, respectively.
The invention also provides a test method for AC calibration, the method comprising the steps of: step one, providing the first test structure, and testing the first test structure by adopting a Cgc test method to obtain a capacitor C1; further, the capacitor C1 in step one of this embodiment includes a gate oxide capacitor and a parasitic capacitor.
In the first test structure, a grid electrode is arranged between the source and the drain electrodes, a contact hole CT is arranged above the grid electrode and the source and the drain electrodes and used for connecting the source and the drain electrodes and the grid electrode to metal M1 positioned on the contact hole CT, metal M1 respectively connected with the source and the drain electrodes are respectively connected with a PAD PAD and used for collecting current signals, and metal M1 connected with the grid electrode is used for accessing a voltage alternating small signal.
Further, the method for obtaining the capacitance C1 of the first test structure by using the Cgc test method in the first step of this embodiment includes the following steps:
(1) applying an alternating voltage small signal on the metal connected to the gate Poly of the first test structure; further, the small ac voltage signal applied in step (1) of this embodiment is a voltage signal with a frequency of 100 KHz.
(2) Collecting current signals through a test pad on the metal connected to a source or drain of the first test structure; that is, a test PAD is disposed on a metal connected to a contact hole of a source or a drain of the first test structure, and a current signal I1 is collected;
(3) the collected current is integrated over time to calculate the charge amount, i.e. the charge amount
(4) Calculating the capacitance C1 of the first test result according to the relation between the voltage and the charge quantity,
wherein, I1 is a current signal, and U1 is a voltage signal.
The total capacitance of the first test structure in the first step comprises gate oxide capacitance and parasitic capacitance. The total capacitance C1 of the first test structure is composed of two parts, wherein one part is the gate oxide capacitance of the first test structure, and the gate oxide capacitance Cox is the capacitance between the gate and the channel of the first test structure. Another part of the total capacitance C1 constituting the first test structure is a parasitic capacitance, which in turn includes a capacitance Cf between the gate and the source/drain, a capacitance Cov between the gate and the STI region under the gate, a capacitance Cctg between the gate and the contact hole, and a capacitance Cm2p between the gate and the metal connected to the contact hole on the source/drain; and the capacitance Cm2m between the metal connected with the contact hole on the grid electrode and the metal connected with the contact hole on the source/drain electrode.
Further, the contact hole CT of the first test structure is filled with metal for connecting the source, the drain and the gate with the metal M1, respectively.
Step two, providing the second test structure, and testing the second test structure by adopting a Cgc test method to obtain a capacitor C2; further, the capacitor in step two of this embodiment is a parasitic capacitor. Still further, the parasitic capacitance in step two of this embodiment includes a capacitance Cf between the gate and the source/drain, a capacitance Cov between the gate and the STI region under the gate, a capacitance Cctg between the gate and the contact hole, and a capacitance Cm2p between the gate and the metal connected to the contact hole on the source/drain; and the capacitance Cm2m between the metal connected with the contact hole on the grid electrode and the metal connected with the contact hole on the source/drain electrode.
Further, the method for obtaining the capacitance C2 of the second test structure by using the Cgc test method in step two of this embodiment includes the following steps:
(a) applying an alternating voltage small signal on the metal connected to the gate of the second test structure; further, the ac small voltage signal applied in step (a) of this embodiment is a voltage signal U2 with a frequency of 100 KHz.
(b) Collecting current signals through a test pad on the metal connected with a contact hole of a source or a drain of the second test structure; namely, arranging a test PAD PAD on the metal connected with the contact hole of the source electrode or the drain electrode of the second test structure, and collecting a current signal I2;
(c) the collected current is integrated over time to calculate the charge amount, i.e. the charge amount
(d) Calculating the parasitic capacitance C2 of the calibration test key according to the relation between the voltage and the charge quantity,
wherein, I2 is a current signal, U2 is a voltage signal;
step three, subtracting the capacitor C2 from the capacitor C1 in the step one to obtain a gate oxide capacitor Cox, wherein Cox is C1-C2; according to the second test structure, the grid electrode is arranged on the STI region in a spanning mode, so that a channel under the grid oxide layer cannot form an inversion or weak inversion, and the grid oxide layer is removed in a capacitance mode;
and step four, calculating the equivalent electrical thickness of the gate oxide layer by using a capacitance formula. The capacitance calculation formula is as follows:
wherein ε represents the dielectric constant of the capacitor, s is the area of the gate oxide layer, and d is the equivalent electrical thickness of the gate oxide layer, expressed as the gate oxide layer in the present inventionThe electrical thickness, Tox, and, therefore,
in summary, the invention utilizes the testing structure that the grid electrode is across the STI to ensure that the channel under the grid oxide layer can not form the inversion or weak inversion, thereby successfully eliminating the real capacitance between the grid oxide layer and the polysilicon grid electrode, and utilizes the Cgc capacitance testing method to accurately calculate the capacitance of the grid oxide layer so as to accurately calculate the electrical thickness of the grid oxide layer, thereby solving the AC calibration problem. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. A test structure for AC calibration, comprising at least:
a first test structure: the first test structure includes at least: a substrate; the N-type heavily doped regions are positioned on the substrate and respectively used as a source electrode and a drain electrode; the grid electrode is positioned between the upper surface of the substrate and the N-type heavily doped region; contact holes are respectively formed in the source drain electrode and the grid electrode; the contact holes are respectively provided with metal; the metal on the contact holes on the source and the drain electrodes is respectively connected with a bonding pad;
a second test structure; the second test structure includes at least: a substrate; the N-type heavily doped regions are positioned on the substrate and respectively used as a source electrode and a drain electrode; the grid electrode is positioned between the upper surface of the substrate and the N-type heavily doped region; an STI region is formed in the substrate below the grid electrode and between the source electrode and the drain electrode; contact holes are respectively formed in the source drain electrode and the grid electrode; the contact holes are respectively provided with metal; and the metal on the contact holes on the source and the drain electrodes is respectively connected with a bonding pad.
2. The test structure for AC calibration according to claim 1, wherein: the substrates of the first and second test structures are grounded; the contact holes connected with the grid electrodes in the first test structure and the second test structure are provided with metal on a first metal layer; the contact holes connected with the source and the drain in the first test structure and the second test structure are provided with metal on the contact holes in the first metal layer.
3. The test structure for AC calibration according to claim 1, wherein: in the first test structure and the second test structure, metal on a contact hole connected with the grid is respectively connected with a voltage signal.
4. A test method for AC calibration according to any of claims 1 to 3, characterized in that it comprises the following steps:
step one, providing the first test structure, and testing the first test structure by adopting a Cgc test method to obtain a capacitor C1;
step two, providing the second test structure, and testing the second test structure by adopting a Cgc test method to obtain a capacitor C2;
step three, subtracting the capacitor C2 in the step two from the capacitor C1 in the step one to obtain a gate oxide capacitor C3;
and step four, calculating the equivalent electrical thickness of the gate oxide layer by using a capacitance formula.
5. The test method for AC calibration according to claim 4, wherein: the capacitor C1 in step one comprises a gate oxide capacitor and a parasitic capacitor.
6. The test method for AC calibration according to claim 4, wherein: and the capacitor in the second step is a parasitic capacitor.
7. The test method for AC calibration according to claim 6, wherein: the parasitic capacitance in the second step comprises capacitance Cf between the gate and a source/drain, capacitance Cov between the gate and an STI region below the gate, capacitance Cctg between the gate and a contact hole, and capacitance Cm2p between the gate and a metal connected with the contact hole on the source/drain; and the capacitance Cm2m between the metal connected with the contact hole on the grid electrode and the metal connected with the contact hole on the source/drain electrode.
8. The test method for AC calibration according to claim 4, wherein: the method for obtaining the capacitance C1 of the first test structure by using the Cgc test method in the first step comprises the following steps: (1) applying an alternating voltage small signal on the metal connected to the gate of the first test structure; (2) collecting current signals through a test pad on the metal connected to a source or drain of the first test structure; (3) integrating the collected current with time to calculate the charge amount; (4) calculating the capacitance C1 of the first test result according to the relation between the voltage and the charge quantity,
wherein, I1 is a current signal, and U1 is a voltage signal.
9. The test method for AC calibration according to claim 4, wherein: the method for obtaining the capacitance C2 of the second test structure by adopting the Cgc test method in the step two comprises the following steps: (a) applying an alternating voltage small signal on the metal connected to the gate of the second test structure; (b) collecting current signals through a test pad on the metal connected with a contact hole of a source or a drain of the second test structure; (c) integrating the collected current with time to calculate the charge amount; (d) calculating the calibration test key according to the relationship between voltage and chargeThe parasitic capacitance C2 is provided,
wherein, I2 is a current signal, and U2 is a voltage signal.
10. The test method for AC calibration according to claim 4, wherein: the voltage signal applied in the step (1) or the step (a) is a voltage signal with the frequency of 100 KHz.
11. The test method for AC calibration according to claim 4, wherein: and the equivalent electrical thickness of the gate oxide layer in the fourth step is the electrical thickness of the gate oxide layer.
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