CN109473367B - MOS capacitor test structure in SOI process and implementation method thereof - Google Patents
MOS capacitor test structure in SOI process and implementation method thereof Download PDFInfo
- Publication number
- CN109473367B CN109473367B CN201811217612.0A CN201811217612A CN109473367B CN 109473367 B CN109473367 B CN 109473367B CN 201811217612 A CN201811217612 A CN 201811217612A CN 109473367 B CN109473367 B CN 109473367B
- Authority
- CN
- China
- Prior art keywords
- mos
- pad
- connecting pad
- mos capacitor
- pseudo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Automation & Control Theory (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a MOS capacitor test structure in SOI technology and a realization method thereof, wherein the structure comprises the following steps: the MOS capacitors are used for simulating MOS capacitors designed by users; the dummy MOS capacitor is used for measuring the parasitic capacitance from the grid electrode bonding pad to other bonding pads so as to remove the parasitic capacitance of all the MOS capacitors by using the same dummy MOS capacitor structure.
Description
Technical Field
The invention relates to the technical field of MOS capacitance test, in particular to a MOS capacitance test structure in an SOI (Silicon-On-Insulator) process and an implementation method thereof.
Background
As shown in fig. 1, all conventional MOS capacitor test circuits have a MOS capacitor structure corresponding to a dummy MOS capacitor. As shown in fig. 2, during the test, the interconnection (interconnection) is disconnected from the connection between the metal line and the MOS to measure the Parasitic Capacitance (Parasitic Capacitance, Pad and extra Capacitance introduced by the line) of the MOS Capacitance, so as to separate the extra Capacitance introduced by the metal line from the intrinsic Capacitance of the MOS.
When a user lays a wire, MOS capacitors with different structures are designed, the most important difference of the MOS capacitors with different structures is that the shapes of the internal connecting wires are different and the distances between the internal connecting wires and the device are different, and fig. 3 shows three structures, each of which has 4 connecting pads: the grid G, the drain D, the source S and the body end B, the MOS tube area of the MOS capacitor is arranged at the middle, a first internal connecting wire is arranged from the grid G to the MOS tube, a second internal connecting wire is arranged from the drain D to the MOS tube, a third internal connecting wire is arranged from the source S to the MOS tube, a fourth internal connecting wire is arranged from the body end B to the MOS tube, the shape of the first internal connecting wire from the grid G to the MOS tube and the distance from the first internal connecting wire to the drain pad D of the MOS tube are the key points for generating the parasitic capacitance, the distances from the first internal connecting wire of the three structures from top to bottom to the drain pad D of the MOS tube of the MOS capacitor are 102.595, 32.525 and 7um in sequence, the shapes of the internal connecting wires of the three structures are different, and different parasitic capacitances can be generated.
Disclosure of Invention
In order to overcome the defects of the prior art, the present invention provides a structure for testing a MOS capacitor in an SOI process and a method for implementing the same, so as to reduce the occupied wafer area and maintain the accuracy of evaluating the MOS capacitor.
To achieve the above and other objects, the present invention provides a MOS capacitor test structure in SOI process, which comprises
The MOS capacitors are used for simulating MOS capacitors designed by users;
and the dummy MOS capacitor is used for measuring the parasitic capacitance from the grid bonding pad to other bonding pads so as to remove the parasitic capacitance of all the MOS capacitors by using the same dummy MOS capacitor structure.
Preferably, each MOS capacitor is composed of a MOS transistor area, a gate G connection pad, a drain D connection pad, a source S connection pad, a body B connection pad, a first internal connection line from the gate G connection pad to the MOS transistor area, a second internal connection line from the drain D connection pad to the MOS transistor area, a third internal connection line from the source connection pad S to the MOS transistor area, and a fourth internal connection line from the body connection pad B to the MOS transistor area.
Preferably, the pseudo MOS capacitor is composed of a MOS transistor area of the MOS capacitor, a gate G connection pad, a drain D connection pad, a source S connection pad, a body end B connection pad, a first pseudo internal connection line from the gate G connection pad to the MOS transistor area, a second pseudo internal connection line from the drain D connection pad to the MOS transistor area, a third pseudo internal connection line from the source connection pad S to the MOS transistor area, and a fourth pseudo internal connection line from the body end connection pad B to the MOS transistor area.
Preferably, the first, second, third, and fourth dummy interconnection lines are disconnected at the connection with the MOS transistor region.
Preferably, the gate pads of the plurality of MOS capacitors and the first interconnection line from the gate pad to the MOS transistor region are substantially the same in shape to ensure substantially similar parasitic capacitances.
Preferably, the connection pad of the gate G of each MOS capacitor/dummy MOS capacitor and the first interconnection line/first dummy interconnection line between the connection pad of the gate G and the MOS transistor section are not changed, and the width/length/interdigital of the MOS transistor section are set according to different situations.
Preferably, the MOS transistor area width W and length L are each set to NW/NLValue, finger NF set to NNFValue according to which N is designedW*NL*NNFAnd a wide-long interdigital is placed as the MOS capacitor corresponding to the middle value of the value range, and the first to fourth pseudo-internal connecting lines are disconnected at the connecting part with the MOS tube area to obtain the pseudo-MOS capacitor.
Preferably, when measuring the parasitic capacitance, the first to fourth dummy interconnection lines are disconnected at the connection points between the first to fourth dummy interconnection lines between the connection pad of the dummy MOS capacitance gate G and the MOS transistor region, and the parasitic capacitance between the gate pad and the other pad is measured at the connection pad of the gate G.
In order to achieve the above object, the present invention further provides a method for implementing a MOS capacitor test structure in an SOI process, including the following steps:
step S1, generating a matrix according to the W/L/NF of the MOS capacitor in the circuit design;
step S2, generating MOS capacitors corresponding to different W/L/NF matrix elements;
step S3, generating MOS capacitor internal connection wires;
step S4, judging whether all elements are generated, if so, entering step S5, otherwise, returning to step S2;
in step S5, a pseudo MOS capacitor is generated.
Preferably, in step S2, N is set for each of the MOS transistor area width W and length LW/NLValue, finger NF set to NNFValue according to which N is designedW*NL*NNFAnd a MOS capacitor.
Compared with the prior art, the MOS capacitor test structure in the SOI process and the implementation method thereof have the advantages that the parasitic capacitors of the MOS capacitors with different sizes and the parasitic capacitor of one pseudo MOS capacitor are basically set to be similar, the MOS capacitors corresponding to different W/L/NF matrix elements are generated according to the W/L/NF generating matrix of the MOS capacitor in the circuit design, and the parasitic capacitors and the MOS capacitors of the pseudo MOS capacitor are obtained through measurement.
Drawings
FIG. 1 is a diagram of a conventional MOS capacitor test circuit;
FIG. 2 is a schematic diagram of a test structure of the prior art;
FIG. 3 is a diagram illustrating a test structure of a MOS capacitor with different structures;
FIG. 4 is a schematic structural diagram of a MOS capacitor test structure in an SOI process according to the present invention;
FIG. 5 is a flowchart illustrating steps of a method for implementing a MOS capacitor test structure in an SOI process according to the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
FIG. 4 is a schematic structural diagram of a MOS capacitor test structure in an SOI process according to the present invention. As shown in fig. 4, the MOS capacitor test structure in an SOI process of the present invention includes a plurality of MOS capacitors 1 and a Dummy MOS capacitor (Dummy) 2.
Each MOS capacitor 1 consists of an MOS tube region 10 of the MOS capacitor, a grid G connecting pad, a drain D connecting pad, a source S connecting pad, a body end B connecting pad, a first internal connecting wire 11 from the grid G connecting pad to the MOS tube region 10, a second internal connecting wire 12 from the drain D connecting pad to the MOS tube region 10, a third internal connecting wire 13 from the source connecting pad S to the MOS tube region 10 and a fourth internal connecting wire 14 from the body end connecting pad B to the MOS tube region 10, and is used for simulating the MOS capacitor designed by a user; the Dummy MOS capacitor (Dummy)2 is composed of a MOS tube region 20 of the MOS capacitor, a gate G connection pad, a drain D connection pad, a source S connection pad, a body terminal B connection pad, a first Dummy interconnection line 21 between the gate G connection pad and the MOS tube region 20, a second Dummy interconnection line 22 between the drain D connection pad and the MOS tube region 20, a third Dummy interconnection line 23 between the source connection pad S and the MOS tube region 20, and a fourth Dummy interconnection line 24 between the body terminal connection pad B and the MOS tube region 20, wherein the Dummy interconnection lines 21-24 are disconnected at the connection with the MOS tube region 20, are disposed near the MOS capacitor test structure, and are used for measuring the parasitic capacitance from the gate pad (pad) to other pads.
Specifically, the gate pads of the MOS capacitors 1 and the dummy MOS capacitors 2 of different sizes and the first interconnection line/first dummy interconnection line from the gate Pad to the MOS transistor area are set to be substantially the same in shape to ensure that the parasitic capacitances are substantially similar, i.e., the connection Pad (Pad) of the gate G (gate) and the connection Pad of the gate G to the MOS transistor area 10/20 are maintained to be substantially similarThe first interconnection line 11/the first dummy interconnection line 21 are not changed, and the width/length/interdigital (W/L/NF) change of the MOS transistor area 10 is set as shown in FIG. 4, i.e. the width W (20-100 um) and the length L (0-20 um) are set to be NW/NLSetting value of NF (1-100) as NNFValues, designing N according to the valuesW*NL*NNFAnd then placing a wide-long interdigital as an MOS capacitor corresponding to a middle value of a value range (such as the width, the length and the interdigital are respectively about 60um, 10um and 50, which generally cannot be too large or too small) on the MOS capacitor 1, and disconnecting the internal connecting lines 21-24 at the connecting part with the MOS tube area 20 to obtain a pseudo MOS capacitor (Dummy), so that the parasitic capacitances of the MOS capacitors of all sizes are consistent, and the purpose of removing the parasitic capacitances of all the MOS capacitors by using the same Dummy capacitor structure is realized.
In the measurement of the parasitic capacitance, referring to the conventional structure of fig. 2, the first to fourth dummy interconnection lines 21 to 24 are disconnected at the connection points between the first to fourth dummy interconnection lines 21 to 24 between the connection pad of the gate G and the MOS transistor area 20, and the parasitic capacitance from the gate pad to the other pads is measured at the connection pad of the gate G.
The tape-out data shows that the parasitic capacitance removal effect corresponding to the original one-to-one method is only slightly different when the structure of the invention is used for removing the parasitic capacitance of all MOS capacitors, and the capacitance error is +/-2 fF (1fF is 1 x 10) according to the analysis of the experimental result of the invention-15F) But saves the area of the wafer and can meet the requirement of cutting channels which are continuously reduced.
FIG. 5 is a flowchart illustrating steps of a method for implementing a MOS capacitor test structure in an SOI process according to the present invention. As shown in fig. 5, the method for implementing a MOS capacitor test structure in an SOI process of the present invention includes the following steps:
step S1, generating a matrix according to W/L/NF (width/length/interdigital) of the MOS capacitor in the circuit design;
step S2, generating MOS capacitors corresponding to different W/L/NF matrix elements;
step S3, generating MOS capacitor internal connection wires;
step S4, judging whether all elements are generated, if so, entering step S5, otherwise, returning to step S2;
in step S5, a Dummy MOS capacitor (Dummy) is generated.
In summary, the MOS capacitor test structure in the SOI process and the implementation method thereof of the present invention set the gate pads of the MOS capacitors and the dummy MOS capacitor with different sizes and the first interconnection line/the first dummy interconnection line from the gate pad to the MOS transistor area to be substantially the same in shape to ensure that the parasitic capacitances are substantially similar, generate the MOS capacitors corresponding to different W/L/NF matrix elements according to the W/L/NF generation matrix of the MOS capacitors in the circuit design, and measure and obtain the parasitic capacitances from the dummy MOS capacitor gate pad to other pads and the respective MOS capacitances.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (7)
1. A MOS capacitor test structure in SOI process is characterized in that the MOS capacitor test structure comprises a plurality of MOS capacitors and a pseudo MOS capacitor,
each MOS capacitor consists of an MOS tube region, a grid G connecting pad, a drain D connecting pad, a source S connecting pad, a body end B connecting pad, a first internal connecting wire from the grid G connecting pad to the MOS tube region, a second internal connecting wire from the drain D connecting pad to the MOS tube region, a third internal connecting wire from the source S connecting pad to the MOS tube region and a fourth internal connecting wire from the body end B connecting pad to the MOS tube region, and each MOS capacitor is used for simulating an MOS capacitor designed by a user;
the pseudo MOS capacitor consists of an MOS tube region, a grid G connecting pad, a drain D connecting pad, a source S connecting pad, a body end B connecting pad, a first pseudo-internal connection wire between the grid G connecting pad and the MOS tube region, a second pseudo-internal connection wire between the drain D connecting pad and the MOS tube region, a third pseudo-internal connection wire between the source S connecting pad and the MOS tube region, and a fourth pseudo-internal connection wire between the body end B connecting pad and the MOS tube region, and is used for measuring the parasitic capacitance of the grid G connecting pad to the drain D connecting pad, the source S connecting pad and the body end B connecting pad so as to remove the parasitic capacitance of all the MOS capacitors by using the same pseudo-MOS capacitor structure;
the gate G connection pad of each MOS capacitor and the first interconnection line are substantially the same in shape, and the gate G connection pad of each MOS capacitor and the first interconnection line are substantially the same in shape as the gate G connection pad of the dummy MOS capacitor and the first dummy interconnection line.
2. The MOS capacitance test structure of claim 1, wherein the first, second, third and fourth dummy interconnection lines are disconnected at a connection with the MOS transistor region.
3. The MOS capacitance test structure of claim 1, wherein the width, length and interdigitation of the MOS transistor regions are arranged on a case-by-case basis.
4. The MOS capacitance test structure of claim 3,
the width W and/or the length L and/or the interdigital NF of the MOS tube area of all the MOS capacitors are different, and the width W of the MOS tube area of all the MOS capacitors is NWEach value, length L, has NLIndividual value and interdigital NF has NNFA plurality of values, the number of the MOS capacitors is NW×NL×NNF；
The width W and the length L of the MOS tube area of the pseudo MOS capacitor and the value of the interdigital NF are preset values.
5. A method for testing parasitic capacitance by using the MOS capacitance test structure as claimed in any one of claims 1 to 4, wherein the method for testing parasitic capacitance comprises: disconnecting the first to fourth pseudo-internal connection lines of the pseudo-MOS capacitor at the connection positions of the first to fourth pseudo-internal connection lines and the MOS tube region; parasitic capacitances from the gate G connection pad to the drain D connection pad, the source S connection pad and the bulk terminal B connection pad are measured at the gate G connection pad.
6. A method for realizing a MOS capacitance test structure according to any one of claims 1 to 4, characterized in that the method for realizing the MOS capacitance test structure comprises the following steps:
step S1, generating a matrix according to the width W and the length L of an MOS tube area of an MOS capacitor in circuit design and an interdigital NF;
step S2, generating a plurality of MOS capacitors of MOS tube areas corresponding to the elements of the interdigital NF matrix and with different widths W and lengths L;
step S3, generating MOS capacitor internal connection wires;
step S4, judging whether all elements are generated, if so, entering step S5, otherwise, returning to step S2;
in step S5, a pseudo MOS capacitor is generated.
7. The method of claim 6, wherein in step S2, N is respectively set for the width W, the length L and the finger NF of the MOS transistor areaW、NLAnd NNFValue to design NW×NL×NNFAnd a MOS capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811217612.0A CN109473367B (en) | 2018-10-18 | 2018-10-18 | MOS capacitor test structure in SOI process and implementation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811217612.0A CN109473367B (en) | 2018-10-18 | 2018-10-18 | MOS capacitor test structure in SOI process and implementation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109473367A CN109473367A (en) | 2019-03-15 |
| CN109473367B true CN109473367B (en) | 2020-08-25 |
Family
ID=65663893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811217612.0A Active CN109473367B (en) | 2018-10-18 | 2018-10-18 | MOS capacitor test structure in SOI process and implementation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109473367B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3993028A4 (en) | 2019-06-29 | 2022-07-27 | Huawei Technologies Co., Ltd. | Interdigital capacitor and multiplying digital-to-analog conversion circuit |
| CN112989743B (en) * | 2021-02-05 | 2024-05-28 | 上海华虹宏力半导体制造有限公司 | System and method for verifying capacitor mismatch test result |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1462068A (en) * | 2002-05-27 | 2003-12-17 | 松下电器产业株式会社 | Semiconductor device and capacitance measuring method |
| US6872583B1 (en) * | 2000-02-15 | 2005-03-29 | Advanced Micro Devices, Inc. | Test structure for high precision analysis of a semiconductor |
| CN203774313U (en) * | 2014-03-26 | 2014-08-13 | 中芯国际集成电路制造(北京)有限公司 | Interconnected metal capacitance testing structure |
-
2018
- 2018-10-18 CN CN201811217612.0A patent/CN109473367B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6872583B1 (en) * | 2000-02-15 | 2005-03-29 | Advanced Micro Devices, Inc. | Test structure for high precision analysis of a semiconductor |
| CN1462068A (en) * | 2002-05-27 | 2003-12-17 | 松下电器产业株式会社 | Semiconductor device and capacitance measuring method |
| CN203774313U (en) * | 2014-03-26 | 2014-08-13 | 中芯国际集成电路制造(北京)有限公司 | Interconnected metal capacitance testing structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109473367A (en) | 2019-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101447482B (en) | Calibration technique for measuring gate resistance of power mos gate device at wafer level | |
| CN107679261B (en) | Modeling method for parasitic resistance between source and drain of MOS device and substrate | |
| CN109473367B (en) | MOS capacitor test structure in SOI process and implementation method thereof | |
| US8691599B2 (en) | Parameter extraction method for semiconductor device | |
| US20020116696A1 (en) | Capacitance and transmission line measurements for an integrated circuit | |
| Issaoun et al. | On the deembedding issue of CMOS multigigahertz measurements | |
| KR20210038685A (en) | Power device and its resistance simulation method, and power device simulation tool | |
| CN107195563B (en) | Method for extracting parasitic RC network | |
| CN107167724B (en) | A kind of small measuring signal goes embedding method | |
| CN110265315B (en) | Method for accurately testing equivalent thickness of gate oxide layer | |
| CN111368500A (en) | Method for establishing metal interconnection layer capacitance prediction model and model system | |
| US7098049B2 (en) | Shallow trench isolation void detecting method and structure for the same | |
| US8108175B2 (en) | Method for determining self-heating free I-V characterstics of a transistor | |
| CN105548713A (en) | Impedance regulator calibration system and calibration method thereof | |
| US20210102990A1 (en) | Testing structure and testing method | |
| US20130027066A1 (en) | Transistor test structure | |
| CN110364447B (en) | Monitoring structure and monitoring method for critical dimension of semiconductor process | |
| CN112366145B (en) | Test structure and test method for AC calibration | |
| WO2023019655A1 (en) | Semiconductor structure and fabrication method therefor | |
| CN101446606A (en) | Junction capacitance test circuit and method for bipolar transistor | |
| CN111916444B (en) | Electrical property analysis layout for finger-like structure fin field effect transistor | |
| CN114446378B (en) | Parasitic capacitance detection method, memory, and readable storage medium | |
| US9147020B2 (en) | Transmission line characterization using EM calibration | |
| CN104838587A (en) | Reducing the effect of parasitic mismatch at amplifier inputs | |
| US20060038576A1 (en) | Sort interface unit having probe capacitors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |