CN109473367A - Mos capacitance test structure and its implementation in a kind of SOI technology - Google Patents
Mos capacitance test structure and its implementation in a kind of SOI technology Download PDFInfo
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- CN109473367A CN109473367A CN201811217612.0A CN201811217612A CN109473367A CN 109473367 A CN109473367 A CN 109473367A CN 201811217612 A CN201811217612 A CN 201811217612A CN 109473367 A CN109473367 A CN 109473367A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract
The invention discloses mos capacitance test structure and its implementation in a kind of SOI technology, the structure includes: multiple mos capacitances, and each mos capacitance is used for the mos capacitance of analog subscriber design；Pseudo- mos capacitance, the parasitic capacitance for measuring gate pads to other pads through the invention, can keep the accuracy of measurement mos capacitance to remove the parasitic capacitance of all mos capacitances using the same pseudo- MOS capacitance structure while reducing and occupying wafer area.
Description
Technical field
The present invention relates to mos capacitance the field of test technology, more particularly to a kind of SOI (Silicon-On-Insulator,
Silicon i.e. in insulating substrate) mos capacitance test structure and its implementation in technique.
Background technique
As shown in Figure 1, existing mos capacitance test circuit is all a kind of corresponding one pseudo- mos capacitance of MOS capacitance structure.Such as
Shown in Fig. 2, connection wire (interconnection) is disconnected to measure MOS electricity from the junction of metal connecting line and MOS when test
The parasitic capacitance (extra capacitor that Parasitic Capacitance, Pad and line introduce) of appearance, metal connecting line is introduced
Extra capacitor and MOS intrinsic capacity separate.
User can design the mos capacitance of different structure, the most important area of the mos capacitance of these different structures when being routed
Be not that connection wire shape is different and connection wire with a distance from device difference, Fig. 3 three kinds of structures are shown, every kind of structure is all
There are 4 connection pads: grid G, drain D, source S and body end B, the most intermediate metal-oxide-semiconductor area for mos capacitance, grid G to MOS
Pipe is laid with the first connection wire, and drain D to metal-oxide-semiconductor is laid with the second connection wire, and source S is laid in third to metal-oxide-semiconductor
Connecting line, body end B to metal-oxide-semiconductor are laid with the 4th connection wire, the shape of the first connection wire of grid G to metal-oxide-semiconductor and its
Distance to the drain pad D of metal-oxide-semiconductor is to generate the key point of parasitic capacitance, connection in the first of three kinds of structures from top to bottom
102.595,32.525,7um, the interior connection of three kinds of structures are followed successively by with a distance from the drain pad D of metal-oxide-semiconductor of the line from mos capacitance
The shape of line is also not quite similar, this can generate different parasitic capacitances.
Summary of the invention
In order to overcome the deficiencies of the above existing technologies, purpose of the present invention is to provide mos capacitances in a kind of SOI technology
Structure and its implementation are tested, the accuracy of assessment mos capacitance is kept while wafer area is occupied to reduce.
In view of the above and other objects, the present invention proposes mos capacitance test structure in a kind of SOI technology, including
Multiple mos capacitances, each mos capacitance are used for the mos capacitance of analog subscriber design；
Pseudo- mos capacitance, the parasitic capacitance for measuring gate pads to other pads, to utilize the same pseudo- mos capacitance
Structure removes the parasitic capacitance of all mos capacitances.
Preferably, each mos capacitance connects pad, drain D connection pad, source electrode by the metal-oxide-semiconductor area of mos capacitance, grid G
S connection pad, body end B connection pad and grid G connect pad and connect to first connection wire in the metal-oxide-semiconductor section, drain D
The second connection wire, the source electrode for connecing pad to the metal-oxide-semiconductor section connect pad S to third connection wire, the body in metal-oxide-semiconductor section
4th connection wire in end connection pad B to metal-oxide-semiconductor section forms.
Preferably, the pseudo- mos capacitance connects pad, drain D connection pad, source by the metal-oxide-semiconductor area of mos capacitance, grid G
Pole S connection pad, body end B connection pad and grid G connect pad and connect to the first pseudo- connection wire in metal-oxide-semiconductor section, drain D
The second pseudo- connection wire, the source electrode for connecing pad to metal-oxide-semiconductor section connect pad S to third puppet connection wire, the body in metal-oxide-semiconductor section
Fourth pseudo- connection wire composition of the end connection pad B to metal-oxide-semiconductor section.
Preferably, the described first, second, third, fourth pseudo- connection wire is disconnected with metal-oxide-semiconductor area connecting place.
Preferably, first connection wire shape of the gate pads and gate pads of multiple mos capacitance to metal-oxide-semiconductor area
It is set as essentially identical to guarantee that parasitic capacitance is substantially similar.
Preferably, the connection pad of each mos capacitance/puppet mos capacitance grid G and the connection pad of grid G are to metal-oxide-semiconductor
The pseudo- connection wire of first connection wire in section/first is constant, and the width/length in metal-oxide-semiconductor area/interdigital is arranged according to different situations.
Preferably, the wide W in metal-oxide-semiconductor area and long L respectively takes setting NW/NLA value, interdigital NF take setting NNFA value is set by the value
Count NW*NL*NNFA mos capacitance, then place a wide long interdigital mos capacitance for corresponding value range median, by its first~
4th pseudo- connection wire disconnects obtaining pseudo- mos capacitance with metal-oxide-semiconductor area connecting place.
Preferably, when measuring parasitic capacitance, pseudo- mos capacitance grid G connection pad to the first~tetra- of metal-oxide-semiconductor section
The junction in pseudo- connection wire and metal-oxide-semiconductor area disconnects the first~tetra- pseudo- connection wire, obtains grid in the connection pad measurement of grid G
Parasitic capacitance of the pole pad to other pads.
In order to achieve the above objectives, the present invention also provides a kind of implementation method of mos capacitance test structure in SOI technology, packets
Include following steps:
Step S1, according to the W/L/NF generator matrix of mos capacitance in circuit design；
Step S2 generates the corresponding mos capacitance of different W/L/NF matrix elements；
Step S3 generates mos capacitance connection wire；
Step S4 judges whether all elements generate and finishes, and finishes if generating, enters step S5, otherwise return step
S2；
Step S5 generates pseudo- mos capacitance.
Preferably, in step S2, W wide to metal-oxide-semiconductor area and long L respectively take setting NW/NLA value, interdigital NF take setting NNFIt is a
Value designs N by the valueW*NL*NNFA mos capacitance.
Compared with prior art, in a kind of SOI technology of the present invention mos capacitance test structure and its implementation by will not
Parasitic capacitance with the mos capacitance of size and a pseudo- mos capacitance is set as substantially similar, according to mos capacitance in circuit design
W/L/NF generator matrix, generate the corresponding mos capacitance of different W/L/NF matrix elements, measurement obtains the parasitism of pseudo- mos capacitance
Capacitor and each mos capacitance.
Detailed description of the invention
Fig. 1 is the schematic diagram of existing mos capacitance test circuit structure；
Fig. 2 is the test schematic diagram of existing test structure；
Fig. 3 is the test structural schematic diagram of the mos capacitance of existing different structure；
Fig. 4 is the structural schematic diagram that mos capacitance tests structure in a kind of SOI technology of the present invention；
Fig. 5 is the step flow chart for the implementation method that mos capacitance tests structure in a kind of SOI technology of the present invention.
Specific embodiment
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand further advantage and effect of the invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under spirit of the invention.
Fig. 4 is the structural schematic diagram that mos capacitance tests structure in a kind of SOI technology of the present invention.As shown in figure 4, of the invention
Mos capacitance test structure includes multiple mos capacitances 1 and a pseudo- mos capacitance (Dummy) 2 in a kind of SOI technology.
Each mos capacitance 1 connects pad, drain D connection pad, source S by the metal-oxide-semiconductor area 10 of mos capacitance, grid G and connects
It connects pad, body end B connection pad and grid G and connects pad to the first connection wire 11 between metal-oxide-semiconductor area 10, drain D connection
Pad between metal-oxide-semiconductor area 10 the second connection wire 12, source electrode connect pad S between metal-oxide-semiconductor area 10 third connection wire 13,
Body end connects mos capacitance of the pad B to the 4th connection wire 14 composition between metal-oxide-semiconductor area 10, for analog subscriber design；It is pseudo-
Mos capacitance (Dummy) 2 connects pad, drain D connection pad, source S connection weldering by the metal-oxide-semiconductor area 20 of mos capacitance, grid G
Disk, body end B connection pad and grid G connect pad to the first pseudo- connection wire 21 between metal-oxide-semiconductor area 20, drain D connection weldering
Disk connects pad S to the third puppet connection wire between metal-oxide-semiconductor area 20 to the second pseudo- connection wire 22, the source electrode between metal-oxide-semiconductor area 20
23, body end connection pad B is formed to the 4th pseudo- connection wire 24 between metal-oxide-semiconductor area 20, puppet connection wire 21~24 with MOS
20 connecting place of area under control disconnects, and is placed near mos capacitance test structure, for measuring gate pads (pad) posting to other pads
Raw capacitor.
Specifically, by the gate pads and gate pads of various sizes of mos capacitance 1 and pseudo- mos capacitance 2 to metal-oxide-semiconductor
The pseudo- connection wire of first connection wire in area/first is shaped to essentially identical to guarantee that parasitic capacitance is substantially similar, that is, protects
The connection pad (Pad) of grid G (Gate) and the connection pad of grid G are held to the first connection wire between metal-oxide-semiconductor area 10/20
11/ first pseudo- connection wire 21 is constant, and width/length/interdigital (W/L/NF) variation in metal-oxide-semiconductor area 10 is arranged according to shown in Fig. 4, i.e., wide
W (20~100um) and long L (0~20um) respectively takes setting NW/NLA value, interdigital NF (1~100) take setting NNFA value, it is several by this
A value designs NW*NL*NNFA mos capacitance 1, then place one it is wide long it is interdigital for corresponding value range median (such as it is wide, long,
Interdigital is respectively 60um, 10um, 50 or so, generally cannot too greatly can not be too small) mos capacitance, by its connection wire 21~
24 disconnect obtaining a pseudo- mos capacitance (Dummy) with 20 connecting place of metal-oxide-semiconductor area, can thus accomplish the MOS of all sizes
The parasitic capacitance of capacitor is consistent, to realize the parasitic capacitance for removing all mos capacitances with the same Dummy capacitance structure
Purpose.
When measuring parasitic capacitance, referring to Fig. 2 existing structure, grid G connection pad to first between metal-oxide-semiconductor area 20~
The junction in four pseudo- connection wires 21~24 and metal-oxide-semiconductor area 20 disconnects the first~tetra- pseudo- connection wire 21~24, in the company of grid G
Connect pad measurement obtain gate pads to other pads parasitic capacitance.
Tape-out data shows the parasitic capacitance that all mos capacitances are removed using structure of the invention, with it is original one by one
The effect of corresponding removal parasitic capacitance only has nuance, analyzes from experimental result of the invention, the error of capacitor ±
2fF (1fF=1*10-15F), but wafer area is saved, is able to satisfy the Cutting Road requirement constantly reduced.
Fig. 5 is the step flow chart for the implementation method that mos capacitance tests structure in a kind of SOI technology of the present invention.Such as Fig. 5 institute
Show, the implementation method of mos capacitance test structure, includes the following steps: in a kind of SOI technology of the present invention
Step S1, according to W/L/NF (width/length/interdigital) generator matrix of mos capacitance in circuit design；
Step S2 generates the corresponding mos capacitance of different W/L/NF matrix elements；
Step S3 generates mos capacitance connection wire；
Step S4 judges whether all elements generate and finishes, and finishes if generating, enters step S5, otherwise return step
S2；
Step S5 generates pseudo- mos capacitance (Dummy).
In conclusion mos capacitance test structure and its implementation are by by different sizes in a kind of SOI technology of the present invention
Mos capacitance and pseudo- mos capacitance gate pads and gate pads to metal-oxide-semiconductor area the first connection wire/first puppet
Connection wire be shaped to it is essentially identical to guarantee that parasitic capacitance is substantially similar, according to the W/L/ of mos capacitance in circuit design
NF generator matrix, generates the corresponding mos capacitance of different W/L/NF matrix elements, and measurement obtains pseudo- mos capacitance gate pads and arrives it
The parasitic capacitance of his pad and each mos capacitance.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Without departing from the spirit and scope of the present invention, modifications and changes are made to the above embodiments by field technical staff.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (10)
1. mos capacitance tests structure in a kind of SOI technology, including
Multiple mos capacitances, each mos capacitance are used for the mos capacitance of analog subscriber design；
Pseudo- mos capacitance, the parasitic capacitance for measuring gate pads to other pads, to utilize the same pseudo- mos capacitance knot
Structure removes the parasitic capacitance of all mos capacitances.
2. mos capacitance tests structure in a kind of SOI technology as described in claim 1, it is characterised in that: each mos capacitance by
The metal-oxide-semiconductor area of mos capacitance, grid G connection pad, drain D connection pad, source S connection pad, body end B connection pad and
Grid G connects pad and connects pad to the second of the metal-oxide-semiconductor section to first connection wire in the metal-oxide-semiconductor section, drain D
Connection wire, the third connection wire of source electrode connection pad S to metal-oxide-semiconductor section, body end connection pad B to the of metal-oxide-semiconductor section
Four connection wires composition.
3. mos capacitance tests structure in a kind of SOI technology as described in claim 1, it is characterised in that: the puppet mos capacitance
By the metal-oxide-semiconductor area of mos capacitance, grid G connection pad, drain D connection pad, source S connection pad, body end B connection pad with
And grid G connects in pad to the first pseudo- connection wire, drain D connection pad to second puppet in metal-oxide-semiconductor section in metal-oxide-semiconductor section
Connecting line, the third puppet connection wire of source electrode connection pad S to metal-oxide-semiconductor section, body end connection pad B to the of metal-oxide-semiconductor section
Four pseudo- connection wire compositions.
4. mos capacitance tests structure in a kind of SOI technology as claimed in claim 3, it is characterised in that: described first, second,
Third, the 4th pseudo- connection wire are disconnected with metal-oxide-semiconductor area connecting place.
5. mos capacitance tests structure in a kind of SOI technology as described in claim 1, it is characterised in that: multiple mos capacitance
Gate pads and gate pads to metal-oxide-semiconductor area the first connection wire be shaped to it is essentially identical to guarantee parasitic capacitance
Substantially similar.
6. mos capacitance tests structure in a kind of SOI technology as claimed in claim 5, it is characterised in that: each mos capacitance/puppet
In the connection pad of the grid G of mos capacitance and the connection pad to the first connection wire/first puppet in metal-oxide-semiconductor section of grid G
Connecting line is constant, and the width/length in metal-oxide-semiconductor area/interdigital is arranged according to different situations.
7. mos capacitance tests structure in a kind of SOI technology as claimed in claim 6, it is characterised in that: the wide W in metal-oxide-semiconductor area and length
L respectively takes setting NW/NLA value, interdigital NF take setting NNFA value designs N by the valueW*NL*NNFA mos capacitance, then to place one wide
The long interdigital mos capacitance for corresponding value range median, by its first~the 4th pseudo- connection wire with metal-oxide-semiconductor area connecting place
Disconnection obtains pseudo- mos capacitance.
8. mos capacitance tests structure in a kind of SOI technology as claimed in claim 7, it is characterised in that: measurement parasitic capacitance
When, pseudo- mos capacitance grid G connection pad to metal-oxide-semiconductor section the first~tetra- puppet connection wire and metal-oxide-semiconductor area junction
Disconnect the first~tetra- pseudo- connection wire, the connection pad measurement of grid G obtain gate pads to other pads parasitic capacitance.
9. the implementation method of mos capacitance test structure, includes the following steps: in a kind of SOI technology
Step S1, according to the W/L/NF generator matrix of mos capacitance in circuit design；
Step S2 generates the corresponding mos capacitance of different W/L/NF matrix elements；
Step S3 generates mos capacitance connection wire；
Step S4 judges whether all elements generate and finishes, and finishes if generating, enters step S5, otherwise return step S2；
Step S5 generates pseudo- mos capacitance.
10. the implementation method of mos capacitance test structure in a kind of SOI technology as claimed in claim 9, it is characterised in that: in
In step S2, W wide to metal-oxide-semiconductor area and long L respectively take setting NW/NLA value, interdigital NF take setting NNFA value designs N by the valueW*
NL*NNFA mos capacitance.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811217612.0A CN109473367B (en) | 2018-10-18 | 2018-10-18 | MOS capacitor test structure in SOI process and implementation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811217612.0A CN109473367B (en) | 2018-10-18 | 2018-10-18 | MOS capacitor test structure in SOI process and implementation method thereof |
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| CN109473367B CN109473367B (en) | 2020-08-25 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021000111A1 (en) * | 2019-06-29 | 2021-01-07 | 华为技术有限公司 | Interdigital capacitor and multiplying digital-to-analog conversion circuit |
| CN112989743A (en) * | 2021-02-05 | 2021-06-18 | 上海华虹宏力半导体制造有限公司 | System and method for verifying capacitor mismatch test result |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1462068A (en) * | 2002-05-27 | 2003-12-17 | 松下电器产业株式会社 | Semiconductor device and capacitance measuring method |
| US6872583B1 (en) * | 2000-02-15 | 2005-03-29 | Advanced Micro Devices, Inc. | Test structure for high precision analysis of a semiconductor |
| CN203774313U (en) * | 2014-03-26 | 2014-08-13 | 中芯国际集成电路制造(北京)有限公司 | Interconnected metal capacitance testing structure |
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2018
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6872583B1 (en) * | 2000-02-15 | 2005-03-29 | Advanced Micro Devices, Inc. | Test structure for high precision analysis of a semiconductor |
| CN1462068A (en) * | 2002-05-27 | 2003-12-17 | 松下电器产业株式会社 | Semiconductor device and capacitance measuring method |
| CN203774313U (en) * | 2014-03-26 | 2014-08-13 | 中芯国际集成电路制造(北京)有限公司 | Interconnected metal capacitance testing structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021000111A1 (en) * | 2019-06-29 | 2021-01-07 | 华为技术有限公司 | Interdigital capacitor and multiplying digital-to-analog conversion circuit |
| US11736116B2 (en) | 2019-06-29 | 2023-08-22 | Huawei Technologies Co., Ltd. | Interdigital capacitor and multiplying digital-to-analog conversion circuit |
| CN112989743A (en) * | 2021-02-05 | 2021-06-18 | 上海华虹宏力半导体制造有限公司 | System and method for verifying capacitor mismatch test result |
| CN112989743B (en) * | 2021-02-05 | 2024-05-28 | 上海华虹宏力半导体制造有限公司 | System and method for verifying capacitor mismatch test result |
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| CN109473367B (en) | 2020-08-25 |
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