CN112989743B - System and method for verifying capacitor mismatch test result - Google Patents
System and method for verifying capacitor mismatch test result Download PDFInfo
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- CN112989743B CN112989743B CN202110170193.5A CN202110170193A CN112989743B CN 112989743 B CN112989743 B CN 112989743B CN 202110170193 A CN202110170193 A CN 202110170193A CN 112989743 B CN112989743 B CN 112989743B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 79
- 238000012360 testing method Methods 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 34
- 101000872083 Danio rerio Delta-like protein C Proteins 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2605—Measuring capacitance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention discloses a system and a method for verifying a capacitor mismatch test result, wherein the system comprises the following steps: the device comprises a plurality of groups of actual capacitors and a plurality of groups of redundant analog capacitors, wherein each group of actual capacitors comprises a first interdigital structure (10), a second interdigital structure (20) and a metal wire, and are used for forming capacitors to be measured; each group of redundant analog capacitors comprises a third interdigital structure (100), a fourth interdigital structure (200) and a metal wire, wherein the metal wires of the redundant analog capacitors are disconnected with the interdigital structures corresponding to the metal wires at the connection positions, and the connection wires are used for forming the connecting wires of the test structures corresponding to the capacitors to be measured and the parasitic capacitors of the test system.
Description
Technical Field
The invention relates to the technical field of capacitance mismatch test, in particular to a system and a method for verifying a capacitance mismatch test result.
Background
Three types of capacitance are often encountered in integrated circuit design and routing (IC layout): a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) capacitor (MOS capacitor), a Metal Oxide Metal (Metal Oxide Metal capicator, MOM) capacitor, and a Metal injection molded (Metal injection Molding, MIM) capacitor.
The MOS capacitor is a MOS tube with a structure at two ends, the capacitance value is inaccurate, the capacitance value which changes along with the change of control voltage can be realized, and the connection method of the upper polar plate and the lower polar plate is not interchangeable; the MOM capacitor is generally an interdigital (finger) capacitor, namely, the capacitor between edges of the same-layer metal (metal) is utilized, multiple layers of metal (metal) can be overlapped for saving area, the number of layers of metal (metal) in the PDK can be selected and is generally only used in the advanced process of the multiple layers of metal, the obtained capacitor value is not deterministic and stable like the MIM capacitor because the capacitor value is realized through the layout of multiple layers of wiring, the capacitor value can be generally used in application scenes such as low requirement on the capacitor value and only use of relative ratio, and the upper polar plate and lower polar plate connection method can be exchanged; MIM capacitors are similar to plate capacitors, the capacitance is relatively accurate, the capacitance does not change with bias voltage, the capacitance is generally manufactured by mTOPl and mTOP-1, the capacitance can be estimated by using (the area of the upper electrode plate is the unit capacitance), the connection method of the upper electrode plate and the lower electrode plate is not interchangeable, and the MIM capacitors are generally used in analog (analog) and Radio Frequency (RF) circuit design processes. Three capacitors with the same area have MIM capacitance value < MOM capacitance value, and MIM capacitance value is about 1/3 times MOS capacitance value.
The MOM capacitor has the advantages that an additional photomask (mask) is not needed, the MIM capacitor can be realized by the additional photomask (mask) and the process, and under the condition that the current process size is smaller, the capacitor with larger capacitance and higher precision is obtained by using a smaller area, so that the capacitor has larger use value, and the mismatching of the MOM capacitor is made, so that the capacitor has larger significance.
Fig. 1 is a typical MOM capacitor structure, which is illustrated as two capacitors C1, C2, the left finger structure 10 forming the capacitor C1, the right finger structure 20 forming the capacitor C2, and the metal lines 31-33 being the outgoing lines of the capacitors. In the prior art, a probe is generally directly used for testing the designed capacitor, and under the scene of matching, the matching of the capacitor is visual and important, and the traditional method is to process data of a measurement result and judge a capacitor mismatch test result by combining system budget.
The specific mismatch verification process is as follows:
First, calculate the difference of the capacitances
Capacitance difference
Then, the standard deviation of the capacitance difference, i.e. mismatch, is calculated
Capacitance Mismatch mismatch=stdev (Δc)
When Mismatch epsilon [0.05%,1% ] is satisfied, the capacitance Mismatch test result is considered to be satisfactory.
Fig. 2 is a schematic diagram of 3 sets of measurement results of MOM capacitors of different configuration test systems on the same design parameter, wherein the square is test 1 (Mea a), the triangle is test 2 (Mea a), the fork is test 3 (Mea a 3), the horizontal axis is area, the vertical axis is capacitance mismatch, and the 3 kinds of test data all meet the requirement that the mismatch is less than 1%, so that it is impossible to determine which configuration test system is better.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a system and a method for verifying a capacitor mismatch test result so as to rapidly judge the conditions of MOM capacitor mismatch test systems with different configurations.
To achieve the above object, the present invention provides a system for verifying a capacitance mismatch test result, comprising: a plurality of groups of actual capacitors and a plurality of groups of redundant analog (dummy) capacitors, each group of actual capacitors comprising a first interdigital structure (10), a second interdigital structure (20) and metal wires for forming a capacitor to be measured; each group of redundant analog capacitors comprises a third interdigital structure (100), a fourth interdigital structure (200) and a metal wire, wherein the metal wires of the redundant analog capacitors are disconnected with the interdigital structures corresponding to the metal wires at the connection positions, and the connection wires are used for forming the connecting wires of the test structures corresponding to the capacitors to be measured and the parasitic capacitors of the test system.
Preferably, the third finger structure (100), the fourth finger structure (200) are identical to the first finger structure (10), the second finger structure (20).
Preferably, the metal lines of the redundant analog capacitors are the same as the metal lines, the through holes, the spacing and the layout size of the actual capacitors, and only the metal lines are disconnected.
In order to achieve the above objective, the present invention further provides a method for verifying a capacitance mismatch test result, comprising the following steps:
Step S1, calculating the difference values of a plurality of groups of actual capacitances and redundant analog capacitances respectively;
Step S2, calculating standard deviations of differences of the actual capacitances and the redundant analog capacitances by using differences of the actual capacitances and the redundant analog capacitances;
And S3, determining a capacitor Mismatch Mismatch test result according to the standard deviation of the actual capacitor and the redundant analog capacitor difference value.
Preferably, in step S1, the differences between the actual capacitances and the redundant analog capacitances are respectively:
Actual capacitance difference DeltaC i＝(C1-C2)i
Redundant analog capacitance difference ΔC_0 i＝(C1_0-C2_0)i
Wherein Δc i is the actual capacitance difference, Δc— i is the redundant analog capacitance difference, C1, C2 are the actual capacitances, c1_0, c2_0 are the redundant analog capacitances.
Preferably, standard deviations of differences between actual capacitances and redundant analog capacitances of each group are respectively:
Standard deviation of actual capacitance difference
Standard deviation of redundant analog capacitance difference
Wherein, in the formulaFor the average value of the actual capacitance difference value and the average value of the redundant analog capacitance difference value, STDEV (Δc) is the standard deviation of the actual capacitance difference value, and STDEV (Δc—0) is the standard deviation of the redundant analog capacitance difference value.
Preferably, the average value of the actual capacitance difference value and the average value of the redundant analog capacitance difference value are respectively:
preferably, when STDEV (Δc) > > STDEV (Δc—0) is satisfied, the capacitance mismatch test result is considered satisfactory.
Preferably, STDEV (Δc) is greater than STDEV (Δc—0) ×sqrt (2) or 1.414 times or more.
Compared with the prior art, the system and the method for verifying the capacitor mismatch test result can rapidly judge the conditions of MOM capacitor mismatch test systems with different configurations.
Drawings
FIG. 1 is a block diagram of a system for verifying capacitance mismatch test results in the prior art;
FIG. 2 is a graph showing 3 sets of MOM capacitors measured by different test systems for the same design parameters;
FIG. 3 is a system block diagram of a system for verifying capacitance mismatch test results according to the present invention;
fig. 4 is a flow chart of steps of a method for verifying a capacitance mismatch test result according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the following disclosure, when considered in light of the accompanying drawings, by describing embodiments of the present invention with specific embodiments thereof. The invention may be practiced or carried out in other embodiments and details within the scope and range of equivalents of the various features and advantages of the invention.
Fig. 3 is a system configuration diagram of a system for verifying a capacitor mismatch test result according to the present invention. As shown in FIG. 3, a system for verifying a capacitance mismatch test result according to the present invention includes a plurality of sets of actual capacitances and a plurality of sets of redundant analog capacitances.
The actual capacitance consists of an interdigital structure 10, an interdigital structure 20 and metal wires 31-33, and is used for forming the capacitance required to be measured; the redundant analog capacitor is composed of an interdigital structure 100, an interdigital structure 200 and metal wires 310-330, and is used for forming the connecting wire of a test structure corresponding to the capacitance to be measured and the parasitic capacitance of the test system, the interdigital structure 100 and the interdigital structure 200 are completely the same as the interdigital structure 10 and the interdigital structure 20, the size of the metal wires 310-330 is the same as that of the metal wires 31-33, but the connecting part of the interdigital structure 100 and the interdigital structure 200 is disconnected, namely, the redundant analog capacitor is the same as that of the metal wires, through holes, spacing, layout size and the like of the actual capacitance, only the metal wires are disconnected, and the disconnected position is close to the interdigital structure such as the minimum line width or other set values as much as possible.
Fig. 4 is a flow chart of steps of a method for verifying a capacitance mismatch test result according to the present invention. As shown in fig. 4, a method for verifying a capacitor mismatch test result according to the present invention includes the following steps:
in step S1, the differences between the actual capacitances and the redundant analog capacitances are calculated.
Specifically, the calculation is as follows:
Actual capacitance difference DeltaC i＝(C1-C2)i
Redundant analog capacitance difference ΔC_0 i＝(C1_0-C2_0)i
In step S2, a standard deviation of the differences between the actual capacitances (assumed to be n) and the redundant analog capacitances is calculated.
Specifically, the calculation is as follows:
Standard deviation of actual capacitance difference
Standard deviation of redundant analog capacitance difference
Wherein, in the formulaIs the average of the actual capacitance difference, the average of the redundant analog capacitance difference, that is,
And S3, determining a capacitor Mismatch Mismatch test result according to the standard deviation of the actual capacitor and the redundant analog capacitor difference value. Specifically, when STDEV (Δc) > > STDEV (Δc—0) is satisfied, the capacitance Mismatch test result is considered to be satisfactory, and it is sufficient to be greater than about-Sqrt (2) or 1.414 times or more.
Examples
Table 1 below shows the results of the calculation of the data of test 3 (Mea 3) using the method of the present invention (more data are actually tested, the present invention is merely illustrative), and the standard deviation of the actual capacitance difference ΔC=C1-C2 of the test system corresponding to test 3 (Mea 3) is far greater than the standard deviation of the redundancy analog capacitance difference ΔC_0=C1_0-C2_0, that is, STDEV (C1-C2) > > STDEV (C1_0-C2_0) or STDEV (ΔC) > > STDEV (ΔC_0), and the test result is judged to be correct (Measurement Ok) according to the method of the present invention, that is, the test system corresponding to test 3 is correctly configured.
TABLE 1 standard deviation of actual capacitance values C1-C2 > standard deviation of redundant analog capacitance values C1_0-C2_0
TABLE 2 standard deviation of actual capacitance values C1-C2-standard deviation of redundant analog capacitance values C1_0-C2_0
Table 2 shows the results of the calculation of the data of test 1 (Mea 1) of another test system with different configuration by the method of the present invention, showing that the standard deviation of the actual capacitance difference ΔC=c1-C2 of the test system corresponding to test 1 (Mea 1) is similar to the standard deviation of the redundancy analog capacitance difference ΔC_0=c1_0-c2_0, that is, the standard deviation of STDEVs (C1-C2) to STDEVs (C1_0-c2_0) or STDEVs (ΔC) to STDEVs (ΔC_0), and the method of the present invention determines that the test result is incorrect (Measurement not Ok), that is, the configuration of the test system corresponding to test 1 is not reasonable.
Therefore, the test results of the invention are obviously different from the test results of the MOM capacitance test of the same design of the 3 different test systems 1/2/3 (Mea 1/2/3) shown in FIG. 2, the test results according to FIG. 2 are not easy to judge whether the test systems are good or not, and according to the test results (Table 1 and Table 2) of the invention, the mismatch of the test system corresponding to the test 3 (Mea, table 1) is smaller than that of the test 1 (Mea 1, table 2), and the corresponding test system is easy to judge whether the test system is good or not according to the test results.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is to be indicated by the appended claims.
Claims (7)
1. A system for verifying a capacitance mismatch test result, comprising: the device comprises a plurality of groups of actual capacitors and a plurality of groups of redundant analog capacitors, wherein each group of actual capacitors comprises a first interdigital structure (10), a second interdigital structure (20) and a metal wire, and are used for forming capacitors to be measured; each group of redundant analog capacitors comprises a third interdigital structure (100), a fourth interdigital structure (200) and metal wires, wherein the third interdigital structure (100), the fourth interdigital structure (200) and the first interdigital structure (10) and the second interdigital structure (20) are identical, the metal wires of the redundant analog capacitors are disconnected with the corresponding interdigital structures at the connection positions, and the redundant analog capacitors are identical to the metal wires, the through holes, the spacing and the layout size of the actual capacitors, and only the metal wires are disconnected.
2. A method of verifying a capacitance mismatch test result, applied to the system for verifying a capacitance mismatch test result of claim 1, the method of verifying a capacitance mismatch test result comprising the steps of:
Step S1, calculating the difference values of a plurality of groups of actual capacitances and redundant analog capacitances respectively;
Step S2, calculating standard deviations of differences of the actual capacitances and the redundant analog capacitances by using differences of the actual capacitances and the redundant analog capacitances;
And S3, determining a capacitor Mismatch Mismatch test result according to the standard deviation of the actual capacitor and the redundant analog capacitor difference value.
3. The method of claim 2, wherein in step S1, differences between actual capacitances and redundant analog capacitances of each set are respectively:
Actual capacitance difference DeltaC i＝(C1-C2)i
Redundant analog capacitance difference ΔC_0 i＝(C1_0-C2_0)i
Wherein Δc i is the actual capacitance difference, Δc— i is the redundant analog capacitance difference, C1, C2 are the actual capacitances, c1_0, c2_0 are the redundant analog capacitances.
4. The method of verifying a capacitance mismatch test result as defined in claim 2, wherein standard deviations of differences between actual capacitances and redundant analog capacitances of each group are respectively:
Standard deviation of actual capacitance difference
Standard deviation of redundant analog capacitance difference
Wherein, in the formulaFor the average value of the actual capacitance difference value and the average value of the redundant analog capacitance difference value, STDEV (Δc) is the standard deviation of the actual capacitance difference value, and STDEV (Δc—0) is the standard deviation of the redundant analog capacitance difference value.
5. The method of verifying a capacitance mismatch test result as defined in claim 4, wherein the average value of the actual capacitance difference values and the average value of the redundant analog capacitance difference values are respectively:
6. A method of validating results of a capacitive mismatch test as claimed in claim 2, wherein: when STDEV (Δc) > > STDEV (Δc—0) is satisfied, the capacitance mismatch test result is considered satisfactory.
7. The method of verifying a capacitance mismatch test result of claim 6, wherein: STDEV (Δc) is greater than STDEV (Δc—0) ×sqrt (2) or 1.414 times or more.
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| CN109473367A (en) * | 2018-10-18 | 2019-03-15 | 上海华虹宏力半导体制造有限公司 | Mos capacitance test structure and its implementation in a kind of SOI technology |
| CN109711038A (en) * | 2018-12-24 | 2019-05-03 | 上海华力集成电路制造有限公司 | MOM capacitor mismatch model and its extracting method |
| WO2021000111A1 (en) * | 2019-06-29 | 2021-01-07 | 华为技术有限公司 | Interdigital capacitor and multiplying digital-to-analog conversion circuit |
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| US9177908B2 (en) * | 2007-04-30 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Limited | Stacked semiconductor capacitor structure |
| KR20100069115A (en) * | 2008-12-16 | 2010-06-24 | 주식회사 동부하이텍 | Mismatch modeling method of a capacitor |
| US8766403B2 (en) * | 2012-02-06 | 2014-07-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Capacitor arrays for minimizing gradient effects and methods of forming the same |
| US9209238B2 (en) * | 2012-06-19 | 2015-12-08 | Maxlinear, Inc. | Method and system for improved matching for on-chip capacitors |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104917527A (en) * | 2015-06-30 | 2015-09-16 | 东南大学 | Capacitance mismatch calibrating circuit and calibrating method applied to single-end SAR ADC |
| CN106253904A (en) * | 2016-08-04 | 2016-12-21 | 成都博思微科技有限公司 | A kind of layout design method of MOM capacitor of sampling in pipeline ADC system |
| CN109473367A (en) * | 2018-10-18 | 2019-03-15 | 上海华虹宏力半导体制造有限公司 | Mos capacitance test structure and its implementation in a kind of SOI technology |
| CN109711038A (en) * | 2018-12-24 | 2019-05-03 | 上海华力集成电路制造有限公司 | MOM capacitor mismatch model and its extracting method |
| WO2021000111A1 (en) * | 2019-06-29 | 2021-01-07 | 华为技术有限公司 | Interdigital capacitor and multiplying digital-to-analog conversion circuit |
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