CN100403038C - Test circuit of double Rutherford horizontal dual diffusion field-effect transistor conducting resistor - Google Patents
Test circuit of double Rutherford horizontal dual diffusion field-effect transistor conducting resistor Download PDFInfo
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- CN100403038C CN100403038C CNB2003101220956A CN200310122095A CN100403038C CN 100403038 C CN100403038 C CN 100403038C CN B2003101220956 A CNB2003101220956 A CN B2003101220956A CN 200310122095 A CN200310122095 A CN 200310122095A CN 100403038 C CN100403038 C CN 100403038C
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Abstract
The present invention relates to a test circuit of a double Rutherford horizontal dual diffusion field-effect transistor conducting resistor, which comprises a direct current power supply of 40 volts and a seat for a tested device, wherein the seat for the tested device has a C end, a D end and an S end connected with the gate electrode, the leak electrode and the source electrode of the tested device. The present invention is characterized in that a resistor R2 and a switch S2 are connected in series between the D end and the direct current power supply of 40 volts. One end of the resistor R2 is connected with the D end, and one end of the switch S2 is connected with the direct current power supply of 40 volts. The C end is orderly connected in series with a switch S1, a resistor R1 and an adjustable power supply, and two capacitors C1 and C2 are connected in parallel between the C end and the grounding end. A capacitor C3 is connected in parallel between the D end and the grounding end. Because the high voltage capacitor with large capacity is connected in parallel between the D end and the grounding end, output level can be tested, and the conducting resistor is obtained by a comparison table. The present invention has the advantages of simple method and reduced testing time. Meanwhile, the present invention overcomes burr influence. In addition, because the two capacitors with different capacities are connected in parallel between the C end and the grounding end, the present invention can filter interference signals of the high frequency and the low frequency of the power supply. Therefore, the present invention has large practicability.
Description
Technical field
The present invention relates to a kind of microelectronic component electric performance test technology, relate in particular to a kind of test circuit that is used for two rutherford's horizontal dual pervasion field effect transistor conducting resistance of electric power management circuit.
Background technology
When at present the measuring equipment of prior art is to the test of the conducting resistance of the two rutherford's horizontal dual pervasion field effect transistors in the electric power management circuit (abbreviation LDMOS), all LDMOS is operated under the higher voltage, the supply voltage during test is up to 40V.The defective that exists when actual measurement is:
1. because the LDMOS of electric power management circuit is operated under the higher voltage, therefore testing apparatus is brought higher requirement;
2. because device LDMOS device can only be imported square-wave signal when measuring, so cumbersome during test conduction resistance, bottom level that promptly can only first test signal, and then, just draw resistance value at last divided by the electric current of this moment; But because output signal often is not a direct current signal, therefore still can't test the bottom level with the direct current method, thereby can't measure or obtain real resistance value, people can only constantly approach actual test value with the comparative level method for this reason, this method of testing, not only be difficult to correct obtain real resistance value, and must spend the more time and measure and calculate;
3. owing to tester in producing is had an appointment two meters long to the cabling of testing circuit board, the undesired signal between the unavoidable ground cabling has produced " burr ", and the generation of being somebody's turn to do " burr " certainly will influence the authenticity of test result; Because measured signal lower (having only about 0.7v) and measuring accuracy require high, the circuit of filtering burr need be set in surveying instrument for this reason.
Summary of the invention
The object of the present invention is to provide the test circuit of a kind of pair of rutherford's horizontal dual pervasion field effect transistor conducting resistance, it can solve prior art and cause the test result problem on the low side with respect to actual value because of avoiding the signal burr to influence when the LDMOS conducting resistance is tested, and makes the simple time of measurement short.
The object of the present invention is achieved like this:
The test circuit of a kind of LDMOS pipe conducting resistance comprises: 40 volts direct supplys and measured device seat, this measured device seat have the C end that is connected with the measured device grid, hold with the measured device S that the D that is connected holds, is connected with the measured device source electrode that drains; Be characterized in:
Series resistor R2 and switch S 2 between described measured device seat D end and 40 volts of direct supplys, an end of resistance R 2 is held with measured device seat D and is connected, and an end of switch S 2 is connected with 40 volts of direct supplys;
Be connected in series switch S 1, resistance R 1 and scalable power supply successively at described measured device seat C end, two capacitor C 1 and C2 are connected in parallel between measured device seat C end and common ground end;
A capacitor C 3 is connected in parallel between described measured device seat D end and common ground end.
In the test circuit of above-mentioned LDMOS pipe conducting resistance, wherein, the described capacitor C 3 that is arranged between measured device seat D end and the common ground end is high-voltage capacitances of a 470uF.
In the test circuit of above-mentioned LDMOS pipe conducting resistance, wherein, it is described that to be arranged on two capacitor C 2 and C1 between measured device seat C end and the common ground end be respectively one less than the electric capacity of 1uF with greater than the electric capacity of 45uF, in order to the power supply undesired signal of elimination high and low frequency.
The present invention, the test circuit of LDMOS pipe conducting resistance owing to adopted above-mentioned technical scheme, makes it compared with prior art, has following advantage and good effect:
1. the present invention is because between the D of measured device seat end and common ground and connect a high capacity high-voltage capacitance, make output signal become a level and smooth straight line by square wave, therefore just can simply record this output level with DC-method, search the conducting resistance that the contrast table that obtains can draw the correspondence of this device according to this level under the same test environment of laboratory, therefore not only measuring method becomes simple, and once test can obtain data, and the time that has reduced measurement was reduced to Millisecond with Measuring Time from 2 seconds;
The present invention since between the C of measured device seat end and common ground end the capacitor C 2 of in parallel one jumbo capacitor C 1 and a low capacity, thereby high and low frequency undesired signal that can the elimination power supply; Also avoided the appearance influence of burr.
Description of drawings
Embodiment by following test circuit to LDMOS of the present invention pipe conducting resistance can further understand purpose of the present invention, specific structural features and advantage in conjunction with the description of its accompanying drawing.Wherein, accompanying drawing is:
Fig. 1 is the electrical schematic diagram of the test circuit of LDMOS pipe conducting resistance of the present invention.
Embodiment
See also shown in Figure 1ly, this is the electrical schematic diagram of the test circuit of LDMOS of the present invention pipe conducting resistance.The test circuit of LDMOS conducting resistance of the present invention comprises 40 volts of direct supplys 1 and measured device seat 2, and this measured device seat 2 has the S that the C end that is connected with the measured device grid, the D that is connected with the measured device drain electrode hold, be connected with the measured device source electrode and holds; Series resistor R2 and switch S 2 between the D of measured device seat 2 end and 40 volts of direct supplys 1, an end of resistance R 2 is held with the D of measured device seat 2 and is connected, and the other end is connected with an end of switch S 2, and the other end of switch S 2 is connected with 40 volts of direct supplys 1; Be connected in series switch S 1, resistance R 1 and scalable power supply 3 successively at the C of measured device seat 2 end, the other end ground connection of scalable power supply 3, two capacitor C 1 and C2 also are connected in parallel between the C of measured device seat 2 end and common ground end, capacitor C 1 is the electric capacity greater than 45uF, in the present embodiment, what capacitor C 1 adopted is the electric capacity of a 47uF, low-frequency interference signal in order to the elimination power supply, capacitor C 2 is the electric capacity less than 1uF, in the present embodiment, what capacitor C 2 adopted is the electric capacity of a 0.1uF, in order to the high-frequency interferencing signal of elimination power supply; A capacitor C 3 that between the D of measured device seat 2 end and common ground end, is connected in parallel, the high pressure resistant electric capacity of high capacity that this capacitor C 3 is 1000uF.
The test circuit of LDMOS pipe conducting resistance of the present invention is work like this:
When to the testing of the conducting resistance of LDMOS, the LDMOS device is placed in the measured device seat 2, the grid, drain electrode, source electrode that makes measured device LDMOS be C end, D end and the S end of corresponding measured device seat 2 respectively; Between the D of measured device seat 2 end and common ground and connect the high pressure resistant capacitor C 3 of high capacity of a 1000uF; Measure routinely then.Owing to hold over the ground the also high pressure resistant capacitor C 3 of high capacity of a 1000uF at D, make output signal become a level and smooth straight line by square wave, therefore just can simply record output level with DC-method, search the conducting resistance that the contrast table that obtains can draw the correspondence of this device under the same test environment of laboratory according to this level.
In sum, the present invention, the test circuit of LDMOS pipe conducting resistance, because between the D of measured device seat end and common ground and connect a high capacity high-voltage capacitance, can simply record this output level thus, can draw the conducting resistance of the correspondence of this device by contrast table, so measuring method is simple and reduced the time of measuring; Simultaneously since between the C of measured device seat end and common ground end a large bulk capacitance in parallel and a low capacity electric capacity, thereby high and low frequency undesired signal that can the elimination power supply has guaranteed that test result is true and reliable, therefore very practicality.
Claims (3)
1. the test circuit of LDMOS pipe conducting resistance, comprise: 40 volts of direct supplys (1) and measured device seat (2), this measured device seat (2) have the S that the C end that is connected with the measured device grid, the D that is connected with the measured device drain electrode hold, be connected with the measured device source electrode and hold; It is characterized in that:
Series resistor R2 and switch S 2 between described measured device seat (2) D end and 40 volts of direct supplys (1), an end of resistance R 2 is connected with measured device seat (2) D end, and an end of switch S 2 is connected with 40 volts of direct supplys (1);
Be connected in series switch S 1, resistance R 1 and scalable power supply (3) successively at described measured device seat (2) C end, two capacitor C 1 and C2 are connected in parallel between measured device seat (2) C end and common ground end;
A capacitor C 3 is connected in parallel between described measured device seat (2) D end and common ground end.
2. the test circuit of LDMOS pipe conducting resistance as claimed in claim 1 is characterized in that: the described capacitor C 3 that is arranged between measured device seat (2) D end and the common ground end is the high pressure resistant electric capacity of a 1000uF.
3. the test circuit of LDMOS pipe conducting resistance as claimed in claim 1, it is characterized in that: described to be arranged on two capacitor C 2 and C1 between measured device seat (2) C end and the common ground end be respectively one less than the electric capacity of 0.5uF with greater than the electric capacity of 45uF, in order to the power supply undesired signal of elimination high and low frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101220956A CN100403038C (en) | 2003-12-30 | 2003-12-30 | Test circuit of double Rutherford horizontal dual diffusion field-effect transistor conducting resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101220956A CN100403038C (en) | 2003-12-30 | 2003-12-30 | Test circuit of double Rutherford horizontal dual diffusion field-effect transistor conducting resistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1635390A CN1635390A (en) | 2005-07-06 |
| CN100403038C true CN100403038C (en) | 2008-07-16 |
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| CNB2003101220956A Expired - Fee Related CN100403038C (en) | 2003-12-30 | 2003-12-30 | Test circuit of double Rutherford horizontal dual diffusion field-effect transistor conducting resistor |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101566667B (en) * | 2008-04-24 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | MOS component testing method |
| CN101846723B (en) * | 2009-03-25 | 2012-12-19 | 普诚科技股份有限公司 | Measuring method of transconductance parameters |
| CN102478622B (en) * | 2010-11-25 | 2013-12-04 | 佛山市顺德区顺达电脑厂有限公司 | Field effect transistor (FET) test device and method |
| CN103487658B (en) * | 2012-06-11 | 2016-03-02 | 华润矽威科技（上海）有限公司 | The testing circuit of high terminal voltage bootstrap N-type switch conduction resistance |
| CN103293383B (en) * | 2013-06-04 | 2015-07-08 | 中国科学院微电子研究所 | Test circuit for series resistance in MOSFET (metal oxide semiconductor field-effect transistor) power devices |
| CN104764932B (en) * | 2014-01-07 | 2017-10-24 | 北大方正集团有限公司 | A kind of measurement apparatus and measuring method of metal-oxide-semiconductor trap resistance |
| CN111766495B (en) * | 2020-06-24 | 2021-03-19 | 珠海迈巨微电子有限责任公司 | Detection circuit and method of MOSFET (metal-oxide-semiconductor field effect transistor) on-resistance, chip and battery management system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6111423A (en) * | 1997-04-09 | 2000-08-29 | Sony Corporation | Method and apparatus for measuring pinch-off voltage of a field effect transistor |
| US20020118034A1 (en) * | 2000-12-26 | 2002-08-29 | Ericsson Inc. | Transistor device testing employing virtual device fixturing |
| US6518592B1 (en) * | 2000-05-01 | 2003-02-11 | Mitsubushi Denki Kabushiki Kaisha | Apparatus, method and pattern for evaluating semiconductor device characteristics |
-
2003
- 2003-12-30 CN CNB2003101220956A patent/CN100403038C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6111423A (en) * | 1997-04-09 | 2000-08-29 | Sony Corporation | Method and apparatus for measuring pinch-off voltage of a field effect transistor |
| US6518592B1 (en) * | 2000-05-01 | 2003-02-11 | Mitsubushi Denki Kabushiki Kaisha | Apparatus, method and pattern for evaluating semiconductor device characteristics |
| US20030126567A1 (en) * | 2000-05-01 | 2003-07-03 | Mitsubishi Denki Kabushiki Kaisha | Apparatus, method and pattern for evaluating semiconductor device characteristics |
| US20020118034A1 (en) * | 2000-12-26 | 2002-08-29 | Ericsson Inc. | Transistor device testing employing virtual device fixturing |
Non-Patent Citations (2)
| Title |
|---|
| 高温、高压LDMOS导通电阻的特性. 朱德智，柯导明，陈军宁.安徽大学学报，第26卷第4期. 2002 |
| 高温、高压LDMOS导通电阻的特性. 朱德智，柯导明，陈军宁.安徽大学学报，第26卷第4期. 2002 * |
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| CN1635390A (en) | 2005-07-06 |
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